EPC2010C

eGaN® FET DATASHEET EPC2010C EPC2010C – Enhancement Mode Power Transistor VDS , 200 V RDS(on) , 25 mΩ ID , 22 A D EFFICIENT POWER CONVERSION G HAL S Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings VALUE UNIT Drain-to-Source Voltage (Continuous) PARAMETER 200 V Continuous (TA = 25°C, RθJA = 5.3) 22 Pulsed (25°C, TPULSE = 300 µs) 90 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 VDS ID VGS A V °C EPC2010C eGaN® FETs are supplied only in passivated die form with solder bars Applications • High Speed DC-DC conversion • Class D Audio • Lidar Benefits • Ultra High Efficiency • Ultra Low RDS(on) • Ultra Low QG • Ultra Small Footprint Thermal Characteristics PARAMETER TYP RθJC Thermal Resistance, Junction-to-Case 1.1 RθJB Thermal Resistance, Junction-to-Board 2.7 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 56 UNIT °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN 200 TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 200 μA IDSS Drain-Source Leakage VGS = 0 V, VDS = 160 V 50 150 µA VGS = 5 V 1 3 mA IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage VGS = -4 V V 50 150 µA 1.4 2.5 V VGS = 5 V, ID = 12 A 18 25 mΩ IS = 0.5 A, VGS = 0 V 1.7 VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 3 mA RDS(on) Drain-Source On Resistance VSD Source-Drain Forward Voltage 0.8 V All measurements were done with substrate connected to source. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 1 eGaN® FET DATASHEET EPC2010C Dynamic Characteristics (TJ = 25°C unless otherwise stated) PARAMETER CISS Input Capacitance COSS Output Capacitance TEST CONDITIONS MIN VDS = 100 V, VGS = 0 V TYP MAX 380 540 240 320 2.7 CRSS Reverse Transfer Capacitance 1.8 RG Gate Resistance 0.4 QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge VDS = 100 V, ID = 12 A, VGS = 5 V 3.7 VDS = 100 V, ID = 12 A 0.7 UNIT pF Ω 5.3 1.3 1.3 nC 0.9 VDS = 100 V, VGS = 0 V 40 52 0 All measurements were done with substrate connected to source. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 1: Typical Output Characteristics at 25ºC Figure 2: Transfer Characteristics 90 90 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 80 70 60 ID – Drain Current (A) ID – Drain Current (A) 70 50 40 30 60 50 40 30 20 20 10 10 0 0 1 2 3 4 VDS – Drain-to-Source Voltage (V) 5 0 0.5 6 Figure 3: RDS(on) vs. VGS for Various Drain Current 60 RDS(ON) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 60 50 40 30 20 ID = 10 A ID = 20 A ID = 40 A ID = 60 A 10 0 2 2.5 3 3.5 4 VGS – Gate-to-Source Voltage (V) 4.5 25˚C 125˚C VDS = 6 V 80 5 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | 1 1.5 2 2.5 3 3.5 VGS – Gate-to-Source Voltage (V) 4 4.5 5 Figure 4: RDS(on) vs. VGS for Various Temperatures 25˚C 125˚C ID = 12 A 50 40 30 20 10 0 2 2.5 3 3.5 4 VGS – Gate-to-Source Voltage (V) 4.5 5 | 2 eGaN® FET DATASHEET EPC2010C Figure 5b: Capacitance Log Scale Figure 5a: Capacitance Linear Scale 1 1 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD Capacitance (nF) C – Capacitance (nF) 0.8 0.6 0.4 0.1 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 0.01 0.2 0 5 50 150 200 VDS – Drain-to-Source Voltage (V) 0.001 Figure 6: Gate Charge 45 ID = 12 A VDS = 100 V 4 VG – Gate Voltage (V) 100 0 50 3 2 1 100 150 200 VDS – Drain-to-Source Voltage (V) Figure 7: Reverse Drain-Source Characteristics 25˚C 125˚C VGS = 0 V 40 ISD – Source-to-Drain Current (A) 0 35 30 25 20 15 10 5 Normalized On-State Resistance – RDS(on) 3 0 1 2 3 QG – Gate Charge (nC) 0 4 Figure 8: Normalized On Resistance vs. Temperature 2.5 ID = 12 A VGS = 5 V 0 1.5 1 0.5 0.5 1 1.5 2 2.5 3 3.5 VSD – Source-to-Drain Voltage (V ) 4 4.5 5 Figure 9: Normalized Threshold Voltage vs. Temperature 1.3 2 0 -25 1.4 Normalized Threshold Voltage (V) 0 ID = 3 mA 1.2 1.1 1 0.9 0.8 0.7 0 25 50 75 100 125 TJ – Junction Temperature (˚C ) 150 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | 0.6 -25 0 25 50 75 100 125 150 TJ – Junction Temperature ( ˚C ) | 3 eGaN® FET DATASHEET EPC2010C 14 Figure 10: Gate Current 25˚C 125˚C IG – Gate Current (mA) 12 10 8 6 4 2 0 0 1 2 3 4 5 6 VGS – Gate-to-Source Voltage (V) Figure 11: Transient Thermal Response Curves Junction-to-Board ZθJB, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.1 0.01 0.1 0.05 PDM t1 0.02 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB Single Pulse 0.001 10-5 10-4 t2 10-3 10-2 10-1 0 1 tp, Rectangular Pulse Duration, seconds Junction-to-Case ZθJC, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 PDM t1 0.001 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.0001 10-6 t2 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 4 eGaN® FET DATASHEET EPC2010C Figure 12: Safe Operating Area I D- Drain Current (A) 100 10 Limited by RDS(on) Pulse Width 100 µs 1 ms 10 ms 100 ms 1 0.1 TJ = Max Rated, TC = +25°C, Single Pulse 0.1 1 10 100 VDS - Drain-Source Voltage (V) TAPE AND REEL CONFIGURATION 4 mm pitch, 12 mm wide tape on 7” reel 7” reel d e f g Loaded Tape Feed Direction Die orientation dot b 2010 YYYY ZZZZ a c DIM EPC2010 (Note 1) a b c (Note 2) d e f (Note 2) g Dimension (mm) Target MIN MAX 12.00 11.90 12.30 1.75 1.65 1.85 5.50 5.45 5.55 4.00 3.90 4.10 4.00 3.90 4.10 2.00 1.95 2.05 1.50 1.50 1.60 Gate solder bar is under this corner Die is placed into pocket solder bar side down (face side down) Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2010 Die orientation dot Gate Pad solder bar is under this corner YYYY ZZZZ EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | Part Number EPC2010C Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 2010 YYYY ZZZZ | 5 eGaN® FET DATASHEET EPC2010C DIE OUTLINE A f Solder Bar View DIM f x5 A B c d e f g c 3 4 5 6 7 B d x2 2 1 g e g x4 (685) 815 Max Side View MICROMETERS MIN Nominal MAX 3524 1602 1379 577 262 245 600 3554 1632 1382 580 277 250 600 3584 1662 1385 583 292 255 600 Pad no. 1 is Gate; Pads no. 3, 5, 7 are Drain; Pads no. 4, 6 are Source; Pad no. 2 is Substrate. * 100 +/- 20 *Substrate pin should be connected to Source Seating Plane RECOMMENDED LAND PATTERN The land pattern is solder mask defined. 3554 230 230 x5 Pad no. 1 is Gate; Pads no. 3, 5, 7 are Drain; Pads no. 4, 6 are Source; Pad no. 2 is Substrate. * 802 3 4 5 6 7 1632 1 1362 560 x2 (units in µm) *Substrate pin should be connected to Source 2 600 RECOMMENDED STENCIL DRAWING 600 x4 3554 230 230 x5 Recommended stencil should be 4 mil (100 μm) thick, must be laser cut , opening per drawing. The corner has a radius of R60. 3 4 5 6 7 1632 1 1362 560 x2 R6 0 (units in µm) 2 600 600 x4 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. Additional assembly resources available at https://www.epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx Information subject to change without notice. Revised April, 2021 | 6