EPC2012

eGaN® FET DATASHEET EPC2012 EPC2012 – Enhancement Mode Power Transistor VDSS , 200 V RDS(ON) , 100 mW ID , 3 A NEW PRODUCT EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(ON), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings Drain-to-Source Voltage VDS ID VGS TJ TSTG 200 Continuous (TA =25˚C, θJA = 70) 3 Pulsed (25˚C, Tpulse = 300 µs) 15 Gate-to-Source Voltage 6 Gate-to-Source Voltage -5 Operating Temperature -40 to 125 Storage Temperature -40 to 150 PARAMETER EPC2012 eGaN® FETs are supplied only in passivated die form with solder bars Applications • High Speed DC-DC conversion • Class D Audio • Hard Switched and High Frequency Circuits V A Benefits • Ultra High Efficiency • Ultra Low RDS(on) • Ultra low QG • Ultra small footprint V ˚C TEST CONDITIONS MIN 200 TYP MAX UNIT 10 50 µA Static Characteristics (TJ= 25˚C unless otherwise stated) BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 60 µA IDSS Drain Source Leakage VDS = 160 V, VGS = 0 V V Gate-Source Forward Leakage VGS = 5 V 0.2 1 Gate-Source Reverse Leakage VGS = -5 V 0.1 0.5 VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1 mA RDS(ON) Drain-Source On Resistance VGS = 5 V, ID = 3 A IGSS 0.7 mA 1.4 2.5 V 70 100 mΩ Source-Drain Characteristics (TJ= 25˚C unless otherwise stated) VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V, T = 25˚C 1.9 IS = 0.5 A, VGS = 0 V, T = 125˚C 2 V All measurements were done with substrate shorted to source. PARAMETER Thermal Characteristics TEST CONDITIONS MIN TYP MAX UNIT TYP Dynamic Characteristics (TJ= 25˚C unless otherwise stated) CRISSθJC Thermal Junction to Case InputResistance, Capacitance 128 7.6 145 CROSSθJB Thermal Resistance, Junction to Board VDS = 100 V, VGS = 0 V Output Capacitance 73 36 95 ˚C/W pF 3.3 85 4.4 ˚C/W 1.5 1.8 0.57 0.75 0.33 0.41 11 14 CRRSSθJA Thermal Resistance, Junction to Ambient (Note 1) Reverse Transfer Capacitance Note 1: RθJAQ isGdetermined with the device mounted on one(V square Total Gate Charge 5 V)of copper pad, single layer 2 oz copper on FR4 board. GS = inch See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. QGD Gate to Drain Charge VDS = 100 V, ID = 3 A QGS Gate to Source Charge EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | QOSS Output Charge VDS = 100 V, VGS = 0 V ˚C/W | nC PAGE 1 Source-Drain Characteristics (TJ= 25˚C unless otherwise stated) Source-Drain Forward Voltage SD eGaN®VFET DATASHEET IS = 0.5 A, VGS = 0 V, T = 25˚C 1.9 IS = 0.5 A, VGS = 0 V, T = 125˚C 2 V EPC2012 All measurements were done with substrate shorted to source. PARAMETER TEST CONDITIONS MIN TYP MAX 128 145 73 95 UNIT Dynamic Characteristics (TJ= 25˚C unless otherwise stated) CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance 3.3 4.4 QG Total Gate Charge (VGS = 5 V) 1.5 1.8 QGD Gate to Drain Charge 0.57 0.75 QGS Gate to Source Charge 0.33 0.41 QOSS Output Charge 11 14 QRR Source-Drain Recovery Charge VDS = 100 V, VGS = 0 V VDS = 100 V, ID = 3 A VDS = 100 V, VGS = 0 V pF nC 0 All measurements were done with substrate shorted to source. Figure 1: Typical Output Characteristics 15 Figure 2: Transfer Characteristics VGS = 5 VGS = 4 VGS = 3 VGS = 2 25˚C 125˚C VD = 3 V 10 ID – Drain Current (A) ID – Drain Current (A) 15 5 0 0 0.5 1 1.5 5 0 2 VDS – Drain to Source Voltage (V) 10 0 1.5 2 2.5 3 VGS – Gate to Source Voltage (V) 3.5 4 4.5 250 RDS(ON) – Drain to Source Resistance (mΩ) RDS(ON) – Drain to Source Resistance (mΩ) 1 Figure 4: RDS(ON) vs. VGS for Various Temperatures Figure 3: RDS(ON) vs. VGS for Various Drain Currents 200 150 100 ID = 3 A ID = 6 A ID = 10 A ID = 15 A 50 0 0.5 2 2.5 3 3.5 4 4.5 VGS – Gate to Source Voltage (V) 5 5.5 25˚C 125˚C 200 ID = 3 A 150 100 50 0 2 2.5 EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | 3 3.5 4 4.5 VGS – Gate to Source Voltage (V) 5 5.5 | PAGE 2 eGaN® FET DATASHEET EPC2012 Figure 5: Capacitance 5 0.25 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD ID = 3 A VD = 100 V 4 VG – Gate Voltage (V) C – Capacitance (nF) 0.2 0.15 0.1 0.05 0 50 100 150 VDS – Drain to Source Voltage (V) Figure 7: Reverse Drain-Source Characteristics 1.8 Normalized On-State Resistance – RDS(ON) ISD – Source to Drain Current (A) 25˚C 125˚C 10 5 0 0.5 1 1.5 2 2.5 3 VSD – Source to Drain Voltage (V) 3.5 4 0 Figure 9: Normalized Threshold Voltage vs. Temperature 0.8 1.5 2 1.4 1.2 1 .025 IG – Gate Current (A) 1 1 QG – Gate Charge (nC) ID = 3 A VGS = 5 V 1.6 0 20 40 60 80 100 120 TJ – Junction Temperature ( ˚C ) 140 Figure 10: Gate Current 25˚C 125˚C .02 1.2 0.5 Figure 8: Normalized On Resistance vs. Temperature 0.8 -20 4.5 1.4 Normalized Threshold Voltage (V) 2 0 200 15 1.6 3 1 0 0 Figure 6: Gate Charge .015 .01 0.6 0.4 0.2 -20 .005 ID = 1 mA 0 20 40 60 80 100 TJ – Junction Temperature ( ˚C ) 120 140 0 0 1 2 3 4 5 6 VGS – Gate-to-Source Voltage (V) All measurements were done with substrate shortened to source. EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 3 eGaN® FET DATASHEET EPC2012 Figure 11: Transient Thermal Response Curves Normalized Maximum Transient Thermal Impedance ZθJB, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.1 0.2 0.1 0.05 0.01 0.02 0.01 t1 Single Pulse 0.001 0.0001 PDM 10-5 10-4 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-3 10-2 10-1 1 10 100 tp, Rectangular Pulse Duration, seconds Normalized Maximum Transient Thermal Impedance ZθJC, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.1 0.2 0.1 PDM 0.05 t1 0.01 0.02 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.001 10-6 t2 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds Figure 12: Safe Operating Area 100 I D- Drain Current (A) 10 10 µs 1 100 µs limited by RDS(ON) 1 ms 0.1 0.01 10 ms 100 ms/DC TJ = Max Rated, TC = +25°C, Single Pulse 0.1 1 10 100 1000 VDS - Drain-Source Voltage (V) EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 4 eGaN® FET DATASHEET EPC2012 TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7” reel b e d f g Loaded Tape Feed Direction Die orientation dot 7” reel c a Gate solder bar is under this corner Die is placed into pocket solder bar side down (face side down) EPC2012 (note 1) Dimension (mm) target a b c (note 2) d e f (note 2) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 min max 7.90 8.30 1.65 1.85 3.45 3.55 3.90 4.10 3.90 4.10 1.95 2.05 1.5 1.6 Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2012 YYYY Die orientation dot ZZZZ Gate Pad solder bar is under this corner DIE OUTLINE Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 2012 YYYY ZZZZ EPC2012 A f x2 d Solder Bar View Part Number DIM 3 4 A B c d e f g c B d X2 2 1 e g g SEATING PLANE MAX 1.681 0.889 0.660 0.251 0.230 0.251 0.600 1.711 0.919 0.663 0.254 0.245 0.254 0.600 1.741 0.949 0.666 0.257 0.260 0.257 0.600 815 Max MILLIMETERS Nominal 100 +/- 20 (685) Side View MIN EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 5 eGaN® FET DATASHEET EPC2012 RECOMMENDED LAND PATTERN 1711 The land pattern is solder mask defined Pad no. 1 is Gate (units in µm) 234 1 4 643 409 3 Pad no. 2 is Substrate 1 Pad no. 3 is Drain Pad no. 4 is Source 3 4 2 2 600 234 600 234 X2 4 3 4 919 3 1 643 234 1711 2 600 234 234 X2 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any productor circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | Information subject to change without notice. Revised October, 2012 | PAGE 6