EPC2014C

eGaN® FET DATASHEET EPC2014C EPC2014C – Enhancement Mode Power Transistor VDS , 40 V RDS(on) , 16 mΩ ID , 10 A D EFFICIENT POWER CONVERSION G HAL S Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VDS VALUE Drain-to-Source Voltage (Continuous) 40 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 48 V Continuous (TA = 25°C, RθJA = 43°C/W) 10 Pulsed (25°C, TPULSE = 300 µs) 60 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 ID VGS UNIT A V °C EPC2014C eGaN® FETs are supplied only in passivated die form with solder bumps Applications • High Frequency DC-DC conversion • Class-D Audio • Wireless Power Transfer • Lidar Benefits • Ultra High Efficiency • Ultra Low RDS(on) • Ultra Low QG • Ultra Small Footprint Thermal Characteristics PARAMETER TYP RθJC Thermal Resistance, Junction-to-Case 3.6 RθJB Thermal Resistance, Junction-to-Board 9.3 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 80 UNIT °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25°C unless otherwise stated) TEST CONDITIONS MIN BVDSS Drain-to-Source Voltage PARAMETER VGS = 0 V, ID = 125 μA 40 IDSS Drain-Source Leakage VGS = 0 V, VDS = 32 V 50 Gate-to-Source Forward Leakage VGS = 5 V Gate-to-Source Reverse Leakage VGS = -4 V IGSS TYP UNIT V 100 µA 0.4 2 mA 50 100 µA 1.4 2.5 V 16 mΩ VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 2 mA RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 10 A 12 VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 0.8 MAX V All measurements were done with substrate connected to source. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 1 eGaN® FET DATASHEET EPC2014C Dynamic Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX 220 300 6.5 9.5 210 CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance 150 RG Gate Resistance 0.4 QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge VDS = 20 V, VGS = 0 V VDS = 20 V, VGS = 5 V, ID = 10 A UNIT pF Ω 2 2.5 0.7 VDS = 20 V, ID = 10 A 0.3 0.5 nC 0.5 VDS = 20 V, VGS = 0 V 4 6 0 All measurements were done with substrate connected to source. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 1: Typical Output Characteristics Figure 2: Transfer Characteristics 60 60 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 45 ID – Drain Current (A) ID – Drain Current (A) 45 30 VDS = 3 V 15 15 0 0 0.5 1.0 1.5 2.0 VDS – Drain-to-Source Voltage (V) 2.5 0 3.0 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 50 ID = 5 A ID = 10 A ID = 15 A ID = 30 A 40 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 0.5 Figure 4: RDS(on) vs. VGS for Various Temperatures Figure 3: RDS(on) vs. VGS for Various Drain Currents 50 30 20 10 0 25˚C 125˚C 30 2.0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | 40 30 25˚C 125˚C 20 ID = 10 A 10 0 2.0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2014C Figure 5b: Capacitance Figure 5a: Capacitance 300 250 Capacitance (pF) Capacitance (pF) 100 200 150 100 10 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 50 0 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 0 5 10 15 20 25 VDS – Drain-to-Source Voltage (V) 30 35 0 40 Figure 6: Gate Charge ISD – Source-to-Drain Current (A) VGS – Gate-to-Source Voltage (V) ID = 10 A VDS = 20 V 2 1 0 0.5 1.0 QG – Gate Charge (nC) 1.5 20 25 30 35 40 25˚C 125˚C VGS = 0 V 45 30 15 0 2.0 Figure 8: Normalized On Resistance vs. Temperature 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 4.5 5.0 Figure 9: Normalized Threshold Voltage vs. Temperature 2 1.4 1.3 ID = 10 A VGS = 5 V Normalized Threshold Voltage Normalized On-State Resistance RDS(on) 15 Figure 7: Reverse Drain-Source Characteristics 3 1.6 1.4 1.2 1.0 0.8 10 60 4 1.8 5 VDS – Drain-to-Source Voltage (V) 5 0 0 ID = 2 mA 1.2 1.1 1.0 0.9 0.8 0.7 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 0.6 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 All measurements were done with substrate shortened to source. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 3 eGaN® FET DATASHEET EPC2014C Figure 10: Gate Current 9 8 25˚C 125˚C IG – Gate Current (mA) 7 6 5 4 3 2 1 0 0 1 2 3 4 5 VGS – Gate-to-Source Voltage (V) 6 Figure 11: Transient Thermal Response Curves Junction-to-Board ZθJB, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.1 0.1 PDM 0.05 t1 0.02 0.01 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB Single Pulse 0.001 10-5 t2 10-4 10-3 10-2 10-1 1 10+1 tp, Rectangular Pulse Duration, seconds Junction-to-Case ZθJC, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 PDM t1 0.001 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.0001 10-6 t2 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 4 eGaN® FET DATASHEET EPC2014C Figure 12: Safe Operating Area 100 I D – Drain Current (A) 100 µs 10 Limited by RDS(on) Pulse Width 100 ms 10 ms 1 ms 100 µs 1 0.1 1 ms 10 ms 100 ms TJ = Max Rated, TC = +25°C, Single Pulse 0.1 1 10 100 VDS - Drain-Source Voltage (V) TAPE AND REEL CONFIGURATION 4 mm pitch, 8 mm wide tape on 7” reel 7” reel d e f g Loaded Tape Feed Direction Die orientation dot b 2014 YYYY ZZZZ a c Die is placed into pocket solder bar side down (face side down) EPC2014C (note 1) Dimension (mm) target min max a b c (note 2) d e f (note 2) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Gate solder bar is under this corner Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2014 Die orientation dot Gate Pad bump is under this corner YYYY ZZZZ EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | Part Number EPC2014C Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 2014 YYYY ZZZZ | 5 eGaN® FET DATASHEET EPC2014C A DIE OUTLINE f Solder Bar View f x3 DIM A B c d e f g 4 c 3 5 B d x2 2 1 Seating Plane 180 x3 (measurements in µm) MAX 1702 1087 834 316 250 200 400 1732 1117 839 321 265 205 400 *Substrate pin should be connected to Source The land pattern is solder mask defined Solder mask is 10 µm smaller per side than bump 1702 180 Nominal 100 +/- 20 Side View RECOMMENDED LAND PATTERN MIN 1672 1057 829 311 235 195 400 Pad no. 1 is Gate; Pad no. 2 is Substrate;* Pads no. 3 and 5 are Drain; Pad no. 4 is Source g x2 (685) g 815 Max e MICROMETERS 1 Pad no. 2 is Substrate;* 4 814 3 5 1087 296 x2 Pad no. 1 is Gate; 2 Pad no. 4 is Source *Substrate pin should be connected to Source 400 RECOMMENDED STENCIL DRAWING Pads no. 3 and 5 are Drain; 400 x2 1732 180 Recommended stencil should be 4 mil (100 μm) thick, must be laser cut , opening per drawing. The corner has a radius of R60. 180 x3 (units in µm) 4 5 1087 3 814 296 x2 0 R6 1 Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. Additional assembly resources available at https://www.epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx 2 400 400 x2 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | Information subject to change without notice. Revised April, 2021 | 6