eGaN® FET DATASHEET
EPC2022
EPC2022 – Enhancement Mode Power Transistor
VDS , 100 V
RDS(on) , 3.2 mΩ
ID , 90 A
D
EFFICIENT POWER CONVERSION
G
HAL
S
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
Maximum Ratings
PARAMETER
VDS
ID
VALUE
Drain-to-Source Voltage (Continuous)
100
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
120
Continuous (TA = 25°C, RθJA = 2.5°C/W)
90
Pulsed (25°C, TPULSE = 300 µs)
390
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
TJ
Operating Temperature
-40 to 150
TSTG
Storage Temperature
-40 to 150
VGS
UNIT
V
A
V
EPC2022 eGaN® FETs are supplied only in
passivated die form with solder bumps.
Die Size: 6.05 mm x 2.3 mm
• High Speed DC-DC Conversion
• Motor Drive
• Industrial Automation
• Synchronous Rectification
• Inrush Protection
• Class-D Audio
°C
Thermal Characteristics
PARAMETER
TYP
RθJC
Thermal Resistance, Junction-to-Case
0.4
RθJB
Thermal Resistance, Junction-to-Board
1.1
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
42
UNIT
°C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
100
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 0.9 mA
IDSS
Drain-Source Leakage
VDS = 80 V, VGS = 0 V
IGSS
TYP
MAX
UNIT
V
0.1
0.7
mA
Gate-to-Source Forward Leakage
VGS = 5 V
1
9
mA
Gate-to-Source Reverse Leakage
VGS = -4 V
0.1
0.7
mA
1.4
2.5
V
3.2
mΩ
VGS(TH)
Gate Threshold Voltage
RDS(on)
Drain-Source On Resistance
VGS = 5 V, ID = 25 A
2.4
VSD
Source-Drain Forward Voltage
IS = 0.5 A, VGS = 0 V
1.8
VDS = VGS, ID = 13 mA
0.8
V
All measurements were done with substrate connected to source.
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| 1
eGaN® FET DATASHEET
EPC2022
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
RG
Gate Resistance
QG
Total Gate Charge
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
MIN
VDS = 50 V, VGS = 0 V
TYP
MAX
1400
1690
840
1260
UNIT
7
pF
1090
VDS = 0 to 50 V, VGS = 0 V
1410
0.3
VDS = 50 V, VGS = 5 V, ID = 25 A
Ω
13
16
3.4
VDS = 50 V, ID = 25 A
2.4
nC
2.1
VDS = 50 V, VGS = 0 V
71
107
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
Figure 2: Transfer Characteristics
Figure 1: Typical Output Characteristics at 25°C
ID – Drain Current (A)
ID – Drain Current (A)
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
200
VDS = 3 V
200
100
100
0
0
0.5
1.0
1.5
2.0
2.5
VDS – Drain-to-Source Voltage (V)
0
3.0
8
ID = 25 A
ID = 50 A
ID = 100 A
ID = 150 A
6
4
2
2.5
3.0
3.5
4.0
4.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
4.0
4.5
5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
0
25˚C
125˚C
300
300
5.0
VGS – Gate-to-Source Voltage (V)
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8
25˚C
125˚C
IVDDS==253 AV
6
4
2
0
2.0
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
| 2
eGaN® FET DATASHEET
EPC2022
Figure 5b: Capacitance (Log Scale)
Figure 5a: Capacitance (Linear Scale)
2500
Capacitance (pF)
2000
Capacitance (pF)
1000
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
1500
1000
100
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
10
500
0
0
20
40
60
80
1
100
0
20
40
60
80
100
VDS – Drain-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V)
Figure 7: Reverse Drain-Source Characteristics
Figure 6: Gate Charge
ID = 25 A
VDS = 50 V
4
ISD – Source-to-Drain Current (A)
VGS – Gate-to-Source Voltage (V)
5
3
2
1
0
0
5
10
VGS = 0 V
200
100
0
15
QG – Gate Charge (nC)
Figure 8: Normalized On-State Resistance vs. Temperature
1.30
ID = 25 A
VGS = 5 V
Normalized Threshold Voltage
Normalized On-State Resistance RDS(on)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VSD – Source-to-Drain Voltage (V)
4.5
5.0
1.40
1.6
1.4
1.2
1.0
0.8
0
Figure 9: Normalized Threshold Voltage vs. Temperature
2.0
1.8
25˚C
125˚C
300
ID = 13 mA
1.20
1.10
1.00
0.90
0.80
0.70
0
25
50
75
100
TJ – Junction Temperature (°C)
125
150
0.60
0
25
50
75
100
TJ – Junction Temperature (°C)
125
150
All measurements were done with substrate shortened to source.
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| 3
eGaN® FET DATASHEET
EPC2022
Figure 11: Safe Operating Area
Figure 10: Gate Leakage Current
1000
60
IG – Gate Current (mA)
I D – Drain Current (A)
25˚C
125˚C
50
40
30
20
100
Limited by RDS(on)
10
Pulse Width
100 ms
10 ms
1 ms
1
10
0
100 µs
0
1
2
3
4
VGS – Gate-to-Source Voltage (V)
5
0.1
0.1
6
1
10
100
VDS - Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
Figure 12: Transient Thermal Response Curves
ZθJB, Normalized Thermal Impedance
Junction-to-Board
1 Duty Cycle:
0.5
0.1
0.1
0.05
0.02
0.01 0.01
PDM
t1
0.001 Single Pulse
0.0001
10-5
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
10-4
10-3
10-2
10-1
1
10+1
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
Junction-to-Case
1 Duty Cycle:
0.5
0.2
0.1
0.1
0.05
0.02
0.01 0.01
0.001
PDM
t1
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
0.0001
10-6
t2
10-5
10-4
10-3
10-2
10-1
1
tp, Rectangular Pulse Duration, seconds
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
| 4
eGaN® FET DATASHEET
EPC2022
TAPE AND REEL CONFIGURATION
e
8 mm pitch, 12 mm wide tape on 7” reel
d
f
Loaded Tape Feed Direction
Die
orientation
dot
2022
YYYY
ZZZZ
7” inch reel
g
a b c
h
DIM
EPC2022 (Note 1)
a
b
c (Note 2)
d
e
f (Note 2)
g
h
Dimension (mm)
Target MIN MAX
12.00 11.90 12.30
1.75
1.65 1.85
5.50
5.45 5.55
4.00
3.90 4.10
8.00
7.90 8.10
2.00
1.95 2.05
1.50
1.50 1.60
1.50
1.50 1.75
Gate
solder bump is
under this
corner
Die is placed into pocket
solder bump side down
(face side down)
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
DIE MARKINGS
2023
YYYY
Die orientation dot
ZZZZ
Gate Pad bump is
under this corner
Laser Markings
Part
Number
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
2022
YYYY
ZZZZ
EPC2022
DIE OUTLINE
Solder Bump View
Micrometers
A
f
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
B
g
X28
(685)
Side View
Seating plane
(785)
e
X4
100 ± 20
d
2
c
X30
X30
DIM
MIN
Nominal
MAX
A
B
c
d
e
f
g
6020
2270
2047
717
210
195
400
6050
2300
2050
720
225
200
400
6080
2330
2053
723
240
205
400
Pad 1 is Gate;
Pads 2 ,5, 6, 9, 10, 13, 14, 17, 18, 21, 22,
25, 26, 29 are Source;
Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23,
24, 27, 28 are Drain;
Pad 30 is Substrate.*
*Substrate pin should be connected to Source
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| 5
eGaN® FET DATASHEET
EPC2022
RECOMMENDED
LAND PATTERN
(units in µm)
Land pattern is solder mask defined
Solder mask opening is 180 µm
It is recommended to have on-Cu trace PCB vias
6050
180
X30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2300
2030
700
X30
Pad 1 is Gate;
Pads 2, 5, 6, 9,10,13,14, 17, 18, 21, 22,
25, 26, 29 are Source;
Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23,
24, 27, 28 are Drain;
Pad 30 is Substrate.*
*Substrate pin should be connected to Source
400
X28
RECOMMENDED
STENCIL DRAWING
Recommended stencil should be 4 mil
(100 µm) thick, must be laser cut, openings
per drawing.
(units in µm)
6050
3
5
7
2
4
6
8
R60
9
11
13
15
17
19
21
23
25
27
29
10
12
14
16
18
20
22
24
26
28
30
2300
1
2030
700
Intended for use with SAC305 Type 4 solder,
reference 88.5% metals content.
400
X28
Additional assembly resources available at
https://www.epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
180
X30
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
Information subject to
change without notice.
Revised May 2022
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