EPC2023

eGaN® FET DATASHEET EPC2023 EPC2023 – Enhancement Mode Power Transistor VDS , 30 V RDS(on) , 1.45 mΩ ID , 90 A D EFFICIENT POWER CONVERSION G HAL S Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VDS ID VALUE Drain-to-Source Voltage (Continuous) 30 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 36 Continuous (TA = 25°C, RθJA = 6°C/W) 90 Pulsed (25°C, TPULSE = 300 µs) 590 V Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 VGS UNIT A V EPC2023 eGaN® FETs are supplied only in passivated die form with solder bumps. Die Size: 6.05 mm x 2.3 mm Applications: • High Frequency DC-DC Conversion • Point-of-Load (POL) Converters • Motor Drive • Industrial Automation °C Thermal Characteristics PARAMETER TYP RθJC Thermal Resistance, Junction-to-Case 0.4 RθJB Thermal Resistance, Junction-to-Board 1.1 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 42 UNIT °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN 30 TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 1.3 mA IDSS Drain-Source Leakage VGS = 0 V, VDS = 24 V 0.1 1 mA Gate-to-Source Forward Leakage VGS = 5 V 1 9 mA Gate-to-Source Reverse Leakage VGS = -4 V 0.1 1 mA IGSS V VGS(TH) Gate Threshold Voltage 1.4 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 40 A 1.15 1.45 mΩ VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.5 VDS = VGS, ID = 20 mA 0.8 V All measurements were done with substrate connected to source. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1 eGaN® FET DATASHEET EPC2023 Dynamic Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) RG Gate Resistance QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge MIN VDS = 15 V, VGS = 0 V TYP MAX UNIT 2150 2600 1530 2300 100 pF 1850 VDS = 0 to 15 V, VGS = 0 V 2020 0.3 VDS = 15 V, VGS = 5 V, ID = 40 A Ω 19 25 5.7 VDS = 15 V, ID = 40 A 3.2 nC 4 VDS = 15 V, VGS = 0 V 30 45 0 All measurements were done with substrate connected to source. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 2: Transfer Characteristics Figure 1: Typical Output Characteristics at 25°C VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 400 500 ID – Drain Current (A) ID – Drain Current (A) 500 300 200 100 0 300 200 100 0 0.5 1.0 1.5 2.0 2.5 VDS – Drain-to-Source Voltage (V) 0 3.0 4 ID = 20 A ID = 40 A ID = 60 A ID = 80 A 3 2 1 2.5 3.0 3.5 4.0 4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 Figure 4: RDS(on) vs. VGS for Various Temperatures RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) VDS = 3 V 400 Figure 3: RDS(on) vs. VGS for Various Drain Currents 0 25˚C 125˚C 5.0 VGS – Gate-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 4 25˚C 125˚C IVDDS==403 AV 3 2 1 0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2023 Figure 5b: Capacitance (Log Scale) Figure 5a: Capacitance (Linear Scale) 4000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1000 Capacitance (pF) Capacitance (pF) 3000 2000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 100 1000 0 0 5 10 15 20 25 10 30 0 5 10 40 0.8 4 30 0.6 20 0.4 10 0.2 5 10 15 20 VGS – Gate-to-Source Voltage (V) 5 EOSS – COSS Stored Energy (μJ) QOSS – Output Charge (nC) 1.0 0 20 25 30 Figure 7: Gate Charge Figure 6: Output Charge and COSS Stored Energy 50 0 15 VDS – Drain-to-Source Voltage (V) VDS – Drain-to-Source Voltage (V) 3 2 1 0 0.0 30 25 ID = 40 A VDS = 15 V VDS – Drain to Source Voltage (V) Figure 8: Reverse Drain-Source Characteristics 0 5 10 QG – Gate Charge (nC) 15 20 Figure 9: Normalized On-State Resistance vs. Temperature 2.0 Normalized On-State Resistance RDS(on) ISD – Source-to-Drain Current (A) 500 25˚C 125˚C 400 VGS = 0 V 300 200 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 4.5 5.0 1.8 ID = 40 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 All measurements were done with substrate shortened to source. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 3 eGaN® FET DATASHEET EPC2023 Figure 10: Normalized Threshold Voltage vs. Temperature Figure 11: Safe Operating Area 1000 1.40 ID = 20 mA I D – Drain Current (A) Normalized Threshold Voltage 1.30 1.20 1.10 1.00 0.90 100 Limited by RDS(on) 10 Pulse Width 0.80 1 ms 1 100 µs 0.70 0.60 0 25 50 75 100 TJ – Junction Temperature (°C) 125 0.1 0.1 150 1 10 VDS - Drain-Source Voltage (V) 100 Figure 12: Transient Thermal Response Curves ZθJB, Normalized Thermal Impedance Junction-to-Board 1 Duty Cycle: 0.5 0.1 0.1 0.05 0.02 0.01 0.01 PDM t1 0.001 Single Pulse 0.0001 10-5 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-4 10-3 10-2 10-1 1 10+1 tp, Rectangular Pulse Duration, seconds ZθJC, Normalized Thermal Impedance Junction-to-Case 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 PDM t1 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.0001 10-6 t2 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 4 eGaN® FET DATASHEET EPC2023 TAPE AND REEL CONFIGURATION e 8 mm pitch, 12 mm wide tape on 7” reel d f Loaded Tape Feed Direction Die orientation dot 2023 YYYY ZZZZ 7” inch reel g a b c h DIM EPC2023 (Note 1) a b c (Note 2) d e f (Note 2) g h Dimension (mm) Target MIN MAX 12.00 11.90 12.30 1.75 1.65 1.85 5.50 5.45 5.55 4.00 3.90 4.10 8.00 7.90 8.10 2.00 1.95 2.05 1.50 1.50 1.60 1.50 1.50 1.75 Gate solder bump is under this corner Die is placed into pocket solder bump side down (face side down) Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2023 YYYY Die orientation dot ZZZZ Gate Pad bump is under this corner Laser Markings Part Number Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 2023 YYYY ZZZZ EPC2023 DIE OUTLINE Solder Bump View Micrometers A f 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 B g X28 (685) Side View Seating plane (785) e X4 100 ± 20 d 2 c X30 X30 DIM MIN Nominal MAX A B c d e f g 6020 2270 2047 717 210 195 400 6050 2300 2050 720 225 200 400 6080 2330 2053 723 240 205 400 Pad 1 is Gate; Pads 2 ,5, 6, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29 are Source; Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28 are Drain; Pad 30 is Substrate.* *Substrate pin should be connected to Source EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 5 eGaN® FET DATASHEET EPC2023 RECOMMENDED LAND PATTERN (units in µm) Land pattern is solder mask defined Solder mask opening is 180 µm It is recommended to have on-Cu trace PCB vias 6050 180 Pad 1 is Gate; Pads 2, 5, 6, 9,10,13,14, 17, 18, 21, 22, 25, 26, 29 are Source; Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28 are Drain; X30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2300 2030 700 X30 Pad 30 is Substrate.* *Substrate pin should be connected to Source 400 X28 RECOMMENDED STENCIL DRAWING Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. (units in µm) 6050 5 7 2 4 6 8 R60 9 11 13 15 17 19 21 23 25 27 29 10 12 14 16 18 20 22 24 26 28 30 400 X34 2300 3 1330 1 2050 720 Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. Additional assembly resources available at https://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx 200 X35 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Information subject to change without notice. Revised June, 2020 | 6