EPC2031

eGaN® FET DATASHEET EPC2031 EPC2031 – Enhancement Mode Power Transistor VDS , 60 V RDS(on) , 2.6 mΩ ID , 48 A D EFFICIENT POWER CONVERSION G HAL S Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VDS ID VALUE Drain-to-Source Voltage (Continuous) 60 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 72 Continuous (TA = 25°C, RθJA = 11°C/W) 48 Pulsed (25°C, TPULSE = 300 µs) 450 V Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 VGS UNIT A V EPC2031 eGaN® FETs are supplied only in passivated die form with solder bumps. Die Size: 4.6 mm x 2.6 mm • High Frequency DC-DC Conversion • Motor Drive • Industrial Automation • Synchronous Rectification • Class-D Audio °C Thermal Characteristics PARAMETER TYP UNIT RθJC Thermal Resistance, Junction-to-Case 0.45 RθJB Thermal Resistance, Junction-to-Board 3.9 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 45 °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN 60 TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 1 mA IDSS Drain-Source Leakage VGS = 0 V, VDS = 48 V 0.1 0.8 mA Gate-to-Source Forward Leakage VGS = 5 V 1 9 mA Gate-to-Source Reverse Leakage VGS = -4 V 0.1 0.8 mA IGSS V VGS(TH) Gate Threshold Voltage 1.4 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 30 A 2 2.6 mΩ VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 VDS = VGS, ID = 15 mA 0.8 V All measurements were done with substrate connected to source. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1 eGaN® FET DATASHEET EPC2031 Dynamic Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) RG Gate Resistance QG Total Gate Charge MIN VDS = 30 V, VGS = 0 V TYP MAX UNIT 1640 2000 35 980 pF 1500 1340 VDS = 0 to 30 V, VGS = 0 V 1580 0.4 QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge VDS = 30 V, VGS = 5 V, ID = 30 A 16 VDS = 30 V, ID = 30 A 3.2 Ω 21 5 nC 3.6 VDS = 30 V, VGS = 0 V 48 72 0 All measurements were done with substrate connected to source. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics 400 300 ID – Drain Current (A) ID – Drain Current (A) 400 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 200 100 0 200 100 0 0.5 1.0 1.5 2.0 2.5 VDS – Drain-to-Source Voltage (V) 0 3.0 Figure 3: RDS(on) vs. VGS for Various Drain Currents 8 ID = 15 A ID = 30 A ID = 45 A ID = 60 A 6 4 2 0 VDS = 3 V RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 8 25˚C 125˚C 300 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 Figure 4: RDS(on) vs. VGS for Various Temperatures 25˚C 125˚C 6 IVDDS==303 AV 4 2 0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2031 Figure 5a: Capacitance (Linear Scale) Figure 5b: Capacitance (Log Scale) COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1000 Capacitance (pF) Capacitance (pF) 3000 2000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 100 1000 0 0 10 20 30 40 50 10 60 0 10 20 VDS – Drain-to-Source Voltage (V) 2.0 1.5 40 1.0 20 0.5 0 10 20 30 50 60 40 50 60 5 VGS – Gate-to-Source Voltage (V) 60 0 40 Figure 7: Gate Charge Figure 6: 6a:Output OutputCharge Chargeand andCOSS COSSStored StoredEnergy Energy EOSS – COSS Stored Energy (μJ) QOSS – Output Charge (nC) 80 30 VDS – Drain-to-Source Voltage (V) 3 2 1 0 0 ID = 30 A VDS = 30 V 4 0 10 5 15 20 QG – Gate Charge (nC) VDS – Drain-to-Source Voltage (V) Figure 9: Normalized On-State Resistance vs. Temperature Figure 8: Reverse Drain-Source Characteristics 2.0 Normalized On-State Resistance RDS(on) ISD – Source-to-Drain Current (A) 400 25˚C 125˚C 300 VGS = 0 V 200 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 4.5 5.0 1.8 ID = 30 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 All measurements were done with substrate shortened to source. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 3 eGaN® FET DATASHEET EPC2031 Figure 11: Safe Operating Area Figure 10: Normalized Threshold Voltage vs. Temperature 1000 1.40 I D – Drain Current (A) Normalized Threshold Voltage 1.30 ID = 15 11 mA 1.20 1.10 1.00 0.90 100 Limited by RDS(on) 10 0.80 Pulse Width 1 ms 100 µs 1 10 µs 0.70 0.60 0 25 50 75 100 TJ – Junction Temperature (°C) 125 0.1 150 0.1 1 10 VDS - Drain-Source Voltage (V) 100 Figure 12: Transient Thermal Response Curves ZθJB, Normalized Thermal Impedance Junction-to-Board 1 Duty Cycle: 0.5 0.1 0.1 0.05 0.02 0.01 0.01 PDM t1 0.001 Single Pulse 0.0001 10-5 10-4 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-3 10-2 10-1 1 10+1 tp, Rectangular Pulse Duration, seconds ZθJC, Normalized Thermal Impedance Junction-to-Case 1 Duty Cycle: 0.5 0.2 0.1 0.1 PDM 0.05 t1 0.02 0.01 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.001 -6 10 t2 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 4 eGaN® FET DATASHEET EPC2031 TAPE AND REEL CONFIGURATION e 8 mm pitch, 12 mm wide tape on 7” reel d f Die orientation dot 2031 YYYY ZZZZ 7” inch reel Loaded Tape Feed Direction g a b c DIM EPC2031 (Note 1) a b c (Note 2) d e f (Note 2) g Dimension (mm) Target MIN MAX 12.00 11.90 12.30 1.75 1.65 1.85 5.50 5.45 5.55 4.00 3.90 4.10 8.00 7.90 8.10 2.00 1.95 2.05 1.50 1.50 1.60 Gate solder bump is under this corner Die is placed into pocket solder bump side down (face side down) Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2031 YYYY Die orientation dot Part Number ZZZZ Gate Pad bump is under this corner EPC2031 Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 2031 YYYY ZZZZ A DIE OUTLINE Solder Bump View DIM 14 19 24 3 8 13 18 23 7 12 17 22 2 6 11 16 21 1 5 10 15 20 A B c d e f e c X4 B MIN Nominal MAX 4570 2570 1000 500 285 332 4600 2600 1000 500 300 369 4630 2630 1000 500 315 406 Pads 1 and 2 are Gate; e d 9 X4 4 Micrometers Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain; f Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are Side View 790 typ 510 typ Source; Pad 12 is Substrate* Seating plane EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 280+/−28 *Substrate pin should be connected to Source | 5 eGaN® FET DATASHEET EPC2031 RECOMMENDED LAND PATTERN 1 5 10 15 20 Land pattern is solder mask defined Solder mask opening is 330 µm It is recommended to have on-Cu trace PCB vias 2 6 11 16 21 Pads 1 and 2 are Gate; 7 12 17 22 3 8 13 18 23 4 9 14 19 24 300 300 RECOMMENDED STENCIL DRAWING 1000 X4 2600 500 (units in µm) X4 4600 *Substrate pin should be connected to Source 330 Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. 4600 (units in µm) 5 10 15 20 2 6 11 16 21 7 12 17 22 3 8 13 18 23 4 9 14 19 24 1000 X4 Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 2600 X4 1 500 300 RECOMMENDED STENCIL DRAWING 330 Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. Option 2 : Intended for use with SAC305 Type 3 solder. 4600 5 10 15 20 2 6 11 16 21 7 12 17 22 3 8 13 18 23 4 9 14 19 24 300 1000 300 500 1 Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 2600 (units in µm) 300 Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are Source; Pad 12 is Substrate* Option 1 : Intended for use with SAC305 Type 4 solder. 300 Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain; 350 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Information subject to change without notice. Revised June, 2020 | 6