EPC2034C

eGaN® FET DATASHEET EPC2034C EPC2034C – Enhancement Mode Power Transistor VDS , 200 V RDS(on) , 8 mΩ ID , 48 A D EFFICIENT POWER CONVERSION G HAL S Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VDS ID VALUE UNIT Drain-to-Source Voltage (Continuous) 200 V Continuous (TA = 25°C) 48 Pulsed (25°C, TPULSE = 300 µs) 213 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 VGS A V °C EPC2034C eGaN® FETs are supplied only in passivated die form with solder bumps. Die Size: 4.6 mm x 2.6 mm • High Frequency DC/DC Conversion • Multi-level AC/DC Power Supplies • Wireless Power • Solar Micro Inverters • Robotics • Class-D Audio • Low Inductance Motor Drives Thermal Characteristics PARAMETER TYP RθJC Thermal Resistance, Junction-to-Case 0.3 RθJB Thermal Resistance, Junction-to-Board 4 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 45 UNIT °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details PARAMETER TYP MAX UNIT VDS = 160 V, VGS = 0 V, TJ = 25°C 0.03 0.4 mA Gate-to-Source Forward Leakage VGS = 5 V, TJ = 25°C 0.002 4 mA Gate-to-Source Forward Leakage# VGS = 5 V, TJ = 125°C 0.03 9 mA 0.03 0.4 mA 1.1 2.5 V 8 mΩ BVDSS Drain-to-Source Voltage IDSS Drain-Source Leakage IGSS Static Characteristics (TJ= 25°C unless otherwise stated) TEST CONDITIONS VGS = 0 V, ID = 0.6 mA MIN 200 V Gate-to-Source Reverse Leakage VGS = -4 V, TJ = 25°C VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 7 mA RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 20 A 6 VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.7 0.8 V # Defined by design. Not subject to production test. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1 eGaN® FET DATASHEET EPC2034C Dynamic Characteristics (TJ= 25˚C unless otherwise stated) PARAMETER TEST CONDITIONS MIN Capacitance# CISS Input CRSS Reverse Transfer Capacitance COSS Output Capacitance# COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) RG Gate Resistance QG Total Gate Charge# QGS Gate to Source Charge QGD Gate to Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge# QRR Source-Drain Recovery Charge TYP MAX 1155 1386 VDS = 100 V, VGS = 0 V UNIT 3.1 641 962 pF 755 VDS = 0 to 100 V, VGS = 0 V 969 0.5 VDS = 100 V, VGS = 5 V, ID = 20 A Ω 11.1 13.8 3.8 VDS = 100 V, ID = 20 A 2.0 nC 2.1 VDS = 100 V, VGS = 0 V 96 144 0 # Defined by design. Not subject to production test. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 2: Transfer Characteristics Figure 1: Typical Output Characteristics at 25°C 200 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 150 ID – Drain Current (A) ID – Drain Current (A) 200 100 50 0 25°C 25˚C 125˚C 125°C 150 = 36 VV VDS DS = 100 50 0 1 2 3 4 5 0 6 0.5 1.0 1.5 VDS – Drain-to-Source Voltage (V) 20 ID = 10 A ID = 20 A ID = 30 A ID = 40 A 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 2.5 3.0 3.5 4.0 4.5 5.0 Figure 4: RDS(on) vs. VGS for Various Temperatures RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) Figure 3: RDS(on) vs. VGS for Various Drain Currents 2.0 VGS – Gate-to-Source Voltage (V) 5.0 VGS – Gate-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 20 25°C 25˚C 125˚C 125°C IVDDS==203 AV 15 10 5 0 2.0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2034C Figure 5a: Capacitance (Linear Scale) Figure 5b: Capacitance (Log Scale) 10000 2500 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1000 Capacitance (pF) Capacitance (pF) 2000 1500 1000 10 500 0 0 50 100 150 1 200 VDS – Drain-to-Source Voltage (V) 128 9.6 4 96 7.2 64 4.8 32 2.4 100 VGS – Gate-to-Source Voltage (V) 5 50 150 200 0.0 200 150 ID = 20 A VDS = 100 V 2 1 0 0 2 4 6 8 10 12 QG – Gate Charge (nC) Figure 9: Normalized On-State Resistance vs. Temperature Figure 8: Reverse Drain-Source Characteristics 2.0 Normalized On-State Resistance RDS(on) 200 ISD – Source-to-Drain Current (A) 100 3 VDS – Drain-to-Source Voltage (V) 25°C 25˚C 125˚C 125°C 150 VDSGS == 30 VV 100 50 0 50 Figure 7: Gate Charge 12.0 EOSS – COSS Stored Energy (μJ) QOSS – Output Charge (nC) Figure 6: 6a:Output OutputCharge Chargeand andCOSS COSSStored StoredEnergy Energy 0 0 VDS – Drain-to-Source Voltage (V) 160 0 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 4.5 5.0 ID = 20 A VGS = 5 V 1.8 1.6 1.4 1.2 1.0 0.8 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 All measurements were done with substrate shortened to source. TJ = 25°C unless otherwise stated. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 3 eGaN® FET DATASHEET EPC2034C Figure 11: Safe Operating Area Figure 10: Normalized Threshold Voltage vs. Temperature 1.4 1000 1.2 100 ID = 11 7 mA mA ID – Drain Current (A) Normalized Threshold Voltage 1.3 1.1 1.0 0.9 0.8 Limited by RDS(on) 10 Pulse Width 1 ms 10 µs 1 100 µs 0.7 0.6 0 25 50 75 100 TJ – Junction Temperature (°C) 125 0.1 0.1 150 1 10 100 1000 VDS – Drain-Source Voltage (V) TJ = Max Rated, TC = +25°C, Single Pulse Figure 12: Transient Thermal Response Curves Junction-to-Board ZθJB, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.01 PDM 0.02 0.01 t1 0.001 Single Pulse 10-5 10-4 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-3 10-2 10-1 1 10+1 tp, Rectangular Pulse Duration, seconds ZθJC, Normalized Thermal Impedance Junction-to-Case 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.01 PDM 0.02 0.01 t1 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.001 10-6 t2 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 4 eGaN® FET DATASHEET EPC2034C TAPE AND REEL CONFIGURATION e 8 mm pitch, 12 mm wide tape on 7” reel d f Die orientation dot 2034 YYYY ZZZZ 7” inch reel Loaded Tape Feed Direction g a b c DIM Dimension (mm) EPC2034C (Note 1) Target MIN MAX 12.00 11.90 12.30 a 1.75 1.65 1.85 b 5.50 5.45 5.55 c (Note 2) 4.00 3.90 4.10 d 8.00 7.90 8.10 e 2.00 1.95 2.05 f (Note 2) g 1.50 1.50 1.60 Gate solder bump is under this corner Die is placed into pocket solder bump side down (face side down) Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2034 YYYY Die orientation dot Part Number ZZZZ Gate Pad bump is under this corner EPC2034C Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 2034 YYYY ZZZZ A DIE OUTLINE Solder Bump View DIM 14 19 24 3 8 13 18 23 7 12 17 22 2 6 11 16 21 1 5 10 15 20 A B c d e f e c X4 B MIN Nominal MAX 4570 2570 1000 500 285 332 4600 2600 1000 500 300 369 4630 2630 1000 500 315 406 Pads 1 and 2 are Gate; e d 9 X4 4 Micrometers Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain; f Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are Source; Seating plane EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 790 typ Side View *Substrate pin should be connected to Source 280+/−28 510 typ Pad 12 is Substrate* | 5 eGaN® FET DATASHEET EPC2034C RECOMMENDED LAND PATTERN 1 5 10 15 20 Land pattern is solder mask defined Solder mask opening is 330 µm It is recommended to have on-Cu trace PCB vias 2 6 11 16 21 Pads 1 and 2 are Gate; 7 12 17 22 3 8 13 18 23 4 9 14 19 24 300 300 RECOMMENDED STENCIL DRAWING 1000 X4 2600 500 (units in µm) X4 4600 Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain; Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are Source; Pad 12 is Substrate* *Substrate pin should be connected to Source 330 Option 1 : Intended for use with SAC305 Type 4 solder. Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. 4600 (units in µm) 2600 X4 300 500 Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 300 RECOMMENDED STENCIL DRAWING 1000 X4 330 Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. Option 2 : Intended for use with SAC305 Type 3 solder. 4600 (units in µm) 2600 300 300 500 Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 300 1000 350 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Information subject to change without notice. Revised June, 2020 | 6