EPC2039

eGaN® FET DATASHEET EPC2039 EPC2039 – Enhancement Mode Power Transistor VDSS , 80 V RDS(on) , 25 m ID , 6.8 A EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. EPC2039 eGaN® FETs are supplied only in passivated die form with solder bumps Die Size: 1.35 mm x 1.35 mm Maximum Ratings VDS ID VGS TJ TSTG Drain-to-Source Voltage (Continuous) 80 Drain-to-Source Voltage (up to 10,000 5ms pulses at 150˚C) 96 Continuous (TA = 25˚C, R θJA= 70˚C/W) 6.8 Pulsed (25˚C, TPULSE = 300 µs) 50 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 Operating Temperature -40 to 150 Storage Temperature -40 to 150 Applications • High Speed DC-DC conversion • Wireless Power Transfer • LiDAR/Pulsed Power Applications V A Benefits • Ultra High Efficiency • Ultra Low RDS(on) • Ultra low QG • Ultra small footprint V ˚C www.epc-co.com/epc/Products/eGaNFETs/EPC2039.aspx Static Characteristics (TJ= 25˚C unless otherwise stated) PARAMETER BVDSS IDSS IGSS TEST CONDITIONS MIN Drain-to-Source Voltage VGS = 0 V, ID = 300 µA 80 TYP MAX UNIT V Drain Source Leakage VDS = 64 V, VGS = 0 V 20 250 µA Gate-to-Source Forward Leakage VGS = 5 V 0.2 2 Gate-to-Source Reverse Leakage VGS = -4 V 20 250 mA µA 1.6 2.5 V 20 2.5 25 mΩ V VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 2 mA RDS(on) VSD Drain-Source On Resistance Source-Drain Forward Voltage VGS = 5 V, ID = 6 A IS = 0.5 A, VGS = 0 V 0.8 All measurements were done with substrate shorted to source. Thermal Characteristics TYP UNIT RθJC Thermal Resistance, Junction to Case 3 ˚C/W RθJB Thermal Resistance, Junction to Board 28 ˚C/W RθJA Thermal Resistance, Junction to Ambient (Note 1) 81 ˚C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 1 eGaN® FET DATASHEET EPC2039 Dynamic Characteristics (TJ= 25˚C unless otherwise stated) PARAMETER TEST CONDITIONS CISS Input Capacitance CRSS COSS Reverse Transfer Capacitance Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) VDS = 40 V, VGS = 0 V RG Gate Resistance QG Total Gate Charge TYP MAX 210 2 260 115 175 UNIT pF 155 VDS = 0 to 100 V, VGS = 0 V Effective Output Capacitance, Time Related (Note 3) COSS(TR) MIN 190 Ω 0.5 1910 VDS = 40 V, VGS = 5 V, ID = 6 A QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge 2370 760 VDS = 40 V, ID = 6 A 420 pC 560 7640 VDS = 40 V, VGS = 0 V 11500 0 Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 50% BVDSS. Figure 2: Transfer Characteristics 50 50 40 40 ID – Drain Current (A) ID – Drain Current (A) Figure 1: Typical Output Characteristics at 25°C 30 VGS = 5 V VGS = 4 V 20 VGS = 3 V VGS = 2 V 10 0 30 25˚C 125˚C VDS = 3 V 20 10 0 0.5 1.0 1.5 2.0 VDS – Drain-to-Source Voltage (A) 2.5 0 3.0 0.5 Figure 3: RDS(on) vs. VGS for Various Drain Currents 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 80 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 1.5 Figure 4: RDS(on) vs. VGS for Various Temperatures 80 ID = 3 A ID = 6 A ID = 12 A ID = 18 A 60 40 20 0 1.0 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 25˚C 125˚C 60 ID = 6 A 40 20 0 3.0 EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2039 Figure 5b: Capacitance (Log Scale) Figure 5a: Capacitance (Linear Scale) 1000 350 300 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD Capacitance (pF) Capacitance (pF) 250 200 150 100 100 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 50 0 0 20 40 60 1 80 0 20 VDS – Drain-to-Source Voltage (V) ID = 6 A VDS = 40 V 4 3 2 1 0 0.5 1.0 QG – Gate Charge (nC) 1.5 30 20 10 0 2.0 25˚C 125˚C 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VSD – Source-to-Drain Voltage (V) 4.5 5.0 Figure 9: Normalized Threshold Voltage vs. Temperature Figure 8: Normalized On Resistance vs. Temperature 1.40 2.0 1.30 ID = 6 A VGS = 5 V 1.8 Normalized Threshold Voltage Normalized On-State Resistance RDS(on) 80 50 ISD – Source-to-Drain Current (A) VGS – Gate-to-Source Voltage (V) 5 1.6 1.4 1.2 1.0 0.8 60 Figure 7: Reverse Drain-Source Characteristics Figure 6: Gate Charge 0 40 VDS – Drain-to-Source Voltage (V) 1.20 ID = 2 mA 1.10 1.00 0.90 0.80 0.70 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 0.60 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 All measurements were done with substrate shortened to source. EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 3 eGaN® FET DATASHEET EPC2039 Figure 10: Transient Thermal Response Curves Junction-to-Board ZθJB, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.1 0.05 0.02 0.01 0.01 0.1 PDM t1 0.001 Single Pulse 0.0001 10-5 10-4 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-3 10-2 10-1 1 10+1 tp, Rectangular Pulse Duration, seconds ZθJC, Normalized Thermal Impedance Junction-to-Case 1 Duty Cycle: 0.5 0.1 0.2 0.1 0.05 0.01 0.02 0.01 PDM t1 0.001 Single Pulse 0.0001 10-6 10-5 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | | 4 eGaN® FET DATASHEET EPC2039 Figure 11: Safe Operating Area I D – Drain Current (A) 100 10 Limited by RDS(on) 1 Pulse Width 100 ms 100 ms 10 ms10 ms 1 ms 100 µs1 ms 0.1 100 µs 0.01 0.1 1 10 100 VDS – Drain-Source Voltage (V) TJ = Max Rated, TC = +25°C, Single Pulse TAPE AND REEL CONFIGURATION b 4mm pitch, 8mm wide tape on 7” reel e d g f Loaded Tape Feed Direction 7” reel 2039 YYYY ZZZZ c a a b c (see note) d e f (see note) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 max 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Gate solder bump is under this corner Die is placed into pocket solder bump side down (face side down) EPC2039 (note 1) Dimension (mm) target min Die orientation dot Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2039 YYYY Die orientation dot Gate Pad bump is under this corner ZZZZ Part Number EPC2039 Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 AA YYYY EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | Lot_Date Code Marking Line 3 ZZZZ | 5 eGaN® FET DATASHEET EPC2039 A DIE OUTLINE Solder Bump View 6 9 2 5 8 1 4 7 Pad 1 is Gate; Pads 4, 5, 6, 7 are Drain; Pads 2, 3, 8, 9 are Source c c c SEATING PLANE 190 X9 Pad 1 is Gate; 4 7 Pads 4, 5, 6, 7 are Drain; 450 1 2 5 8 3 6 9 Pads 2, 3, 8, 9 are Source 225 450 RECOMMENDED STENCIL DRAWING 450 225 450 1350 1380 1380 450 240 229 The land pattern is solder mask defined Solder mask is 10μm smaller per side than bump 1350 (measurements in µm) MAX 1350 1350 450 225 208 165 +/- 17 (625) Side View RECOMMENDED LAND PATTERN Nominal 1320 1320 450 210 187 d d MIN A B c d e 815 Max B c 3 DIM Recommended stencil should be 4mil (100µm) thick, must be laser cut, openings per drawing. 1350 (measurements in µm) 225 450 450 Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. Additional assembly resources available at http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 225 450 1350 450 200 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2017 | Information subject to change without notice. Revised April, 2017 | 6