EPC2052

eGaN® FET DATASHEET EPC2052 EPC2052 – Enhancement Mode Power Transistor VDS , 100 V RDS(on) , 13.5 mΩ ID , 8.2 A D EFFICIENT POWER CONVERSION G S HAL Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VALUE Drain-to-Source Voltage (Continuous) 100 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120 Continuous (TA = 25°C) 8.2 Pulsed (25°C, TPULSE = 300 µs) 74 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 VDS ID VGS UNIT V A V °C Thermal Characteristics PARAMETER TYP RθJC Thermal Resistance, Junction-to-Case 2 RθJB Thermal Resistance, Junction-to-Board 15 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 74 UNIT °C/W EPC2052 eGaN® FETs are supplied in passivated die form with solder bumps. Die size: 1.5 mm x 1.5 mm Applications • 48 V Servers • Lidar/Pulsed Power • Isolated Power Supplies • Point of Load Converters • Class D Audio • LED Lighting • Low Inductance Motor Drive Benefits • Higher Switching Frequency – Lower switching losses and lower drive power • Higher Efficiency – Lower conduction and switching losses, zero reverse recovery losses • Ultra Small Footprint - Higher power density Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25°C unless otherwise stated) PARAMETER BVDSS Drain-to-Source Voltage IDSS Drain-Source Leakage IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage# TEST CONDITIONS MIN VGS = 0 V, ID = 0.2 mA 100 TYP MAX UNIT V VDS = 80 V, VGS = 0 V, TJ = 25°C 0.02 0.15 mA VGS = 5 V, TJ = 25°C 0.01 1.8 mA VGS = 5 V, TJ = 125°C 0.2 4 mA 0.01 0.18 mA 1.4 2.5 V 13.5 mΩ VGS = -4 V, TJ = 25°C VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 3 mA RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 11 A 10 VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 2.0 0.8 V # Defined by design. Not subject to production test. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1 eGaN® FET DATASHEET EPC2052 Dynamic Characteristics (TJ = 25°C unless otherwise stated) PARAMETER CISS Input Capacitance# CRSS Reverse Transfer Capacitance COSS Capacitance# Output TEST CONDITIONS VDS = 50 V , VGS = 0 V TYP MAX 441 584 COSS(ER) Effective Output Capacitance, Energy Related (Note 2) UNIT 3.2 195 pF 293 227 VDS = 0 to 50 V, VGS = 0 V COSS(TR) Effective Output Capacitance, Time Related (Note 3) RG MIN 274 Gate Resistance 0.7 Charge# QG Total Gate QGS Gate to Source Charge QGD Gate to Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge# QRR Source-Drain Recovery Charge VDS = 50 V, VGS = 5 V, ID = 11 A Ω 3.5 4.5 1.5 VDS = 50 V, ID = 11 A 0.5 nC 1.0 VGS = 0 V, VDS = 50 V 13 20 0 # Defined by design. Not subject to production test. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 2: Transfer Characteristics 70 70 60 60 50 50 ID – Drain Current (A) ID – Drain Current (A) Figure 1: Typical Output Characteristics at 25°C 40 30 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 20 10 0 0 0.5 1.0 1.5 2.0 2.5 30 20 10 0 3.0 Figure 3: RDS(on) vs. VGS for Various Currents 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Drain-to-Source Voltage (V) 4.0 4.5 5.0 Figure 4: RDS(on) vs. VGS for Various Temperatures 40 40 ID = 5 A ID = 11 A ID = 16 A ID = 22 A 35 30 25 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) VDS = 3 V 40 VDS – Drain-to-Source Voltage (V) 20 15 10 5 0 25ºC 125ºC 2.0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 25ºC 125ºC 35 ID = 11 A 30 25 20 15 10 5 0 2.0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2052 Figure 5a: Capacitance (Linear Scale) 500 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 300 Capacitance (pF) Capacitance (pF) 400 1000 200 Figure 5b: Capacitance (Log Scale) 100 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 100 0 0 25 50 75 1 100 0 25 VDS – Drain-to-Source Voltage (V) Figure 6: Output Charge and COSS Stored Energy 15 0.6 10 0.4 5 0.2 25 50 75 100 VDS – Drain-to-Source Voltage (V) 0.0 VGS = 0 V 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 2 1 0 0.5 1.0 1.5 2.0 2.5 QG – Gate Charge (nC) 3.0 3.5 4.0 Figure 9: Normalized On-State Resistance vs. Temperature Normalized On-State Resistance – RDS(on) ISD – Source-to-Drain Current (A) 50 3 2.0 25ºC 125ºC 60 ID = 11 A VDS = 50 V 4 0 Figure 8: Reverse Drain-Source Characteristics 70 100 5 VGS – Gate-to-Source Voltage (V) 0.8 EOSS – COSS Stored Energy (µJ) QOSS – Output Charge (nC) 20 0 75 Figure 7: Gate Charge 1.0 25 0 50 VDS – Drain-to-Source Voltage (V) 4.5 5.0 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 1.8 ID = 11 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 0 25 50 75 100 125 TJ – Junction Temperature (°C) 150 | 3 eGaN® FET DATASHEET EPC2052 Figure 10: Normalized Threshold Voltage vs. Temperature 1.4 Normalized Threshold Voltage 1.3 ID = 3 mA 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0 25 50 75 100 125 150 TJ – Junction Temperature (°C) Figure 11: Transient Thermal Response Curves Junction-to-Board ZθJB, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.2 0.1 0.1 0.05 T 0.02 PDM tp 0.01 0.01 Notes: Duty Factor = tp/T Peak TJ = PDM x ZθJB x RθJB + TB Single Pulse 0.001 10-5 10-4 10-3 10-2 tp - Rectangular Pulse Duration (s) 10-1 1 10 Junction-to-Case ZθC, Normalized Thermal Impedance 1 Duty Factors: 0.5 0.2 0.1 0.1 0.05 T 0.02 PDM tp 0.01 0.01 Notes: Duty Factor = tp/T Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.001 10-5 10-4 10-3 10-2 tp - Rectangular Pulse Duration [s] EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 10-1 1 10 | 4 eGaN® FET DATASHEET EPC2052 Figure 12: Safe Operating Area 100 I D- Drain Current (A) 10 Limited by RDS(on) 1 Pulse Width 1 ms 100 μs 10 μs 0.1 0.1 1 10 100 1000 VDS - Drain-Source Voltage (V) TJ = Max Rated, TC = +25°C, Single Pulse TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7”reel d e f Loaded Tape Feed Direction g 7” reel Die orientation dot b ZZZZ c Gate solder bar is under this corner YYYY a 2052 Die is placed into pocket solder bar side down (face side down) EPC2052 (note 1) Dimension (mm) target min a b c (see note) d e f (see note) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 max 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2052 Pin 1 indicator YYYY ZZZZ Part Number EPC2052 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 2052 YYYY ZZZZ | 5 eGaN® FET DATASHEET EPC2052 A DIE OUTLINE Solder Bump View DIM 3 6 A B c d e 2 5 1 8 4 B c e 9 MICROMETERS MIN Nominal MAX 1470 1470 1500 1500 450 500 264 1530 1530 238 290 Pad 1 is Gate; Pads 2, 3, 7, 8, 9 are Source; Pads 4, 5, 6 are Drain. 7 200 +/- 20 Side View 885 685 +/- 25 d Seating Plane A RECOMMENDED LAND PATTERN (units in µm) 1 4 2 5 8 3 6 9 B c e 7 DIM MICROMETERS A B c d e 1500 1500 450 500 230 Pad 1 is Gate; Pads 2, 3, 7, 8, 9 are Source; Pads 4, 5, 6 are Drain. d A Additional assembly resources available at https://epc-co.com/epc/ DesignSupport/AssemblyBasics.aspx 1 g 4 e 7 c (measurements in µm) 2 5 8 3 6 9 B RECOMMENDED STENCIL DRAWING d Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | DIM MICROMETERS A B c d f g 1500 1500 450 500 300 250 Pad 1 is Gate; Pads 2, 3, 7, 8, 9 are Source; Pads 4, 5, 6 are Drain. Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, opening per drawing. The corner has a radius of R60. Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. Information subject to change without notice. Revised March 19, 2020 | 6