EPC2055

eGaN® FET DATASHEET EPC2055 EPC2055 – Enhancement Mode Power Transistor VDS , 40 V RDS(on) , 3.6 mΩ ID , 29 A D G EFFICIENT POWER CONVERSION HAL S Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VDS ID VALUE Drain-to-Source Voltage (Continuous) 40 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C) 48 Continuous (TA = 25°C) 29 Pulsed (25°C, TPULSE = 300 µs) 161 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 VGS UNIT V A V °C Applications • DC-DC Converters • Isolated DC-DC Converters • Sync rectification • High frequency (2 MHz) Ultra-thin Point of Load Converters with Input 12 V – 24 V • Lidar • USB-C Battery Chargers • LED Lighting • 12 V – 24 V Input Motor Drivers Benefits Thermal Characteristics PARAMETER EPC2055 eGaN® FETs are supplied only in passivated die form with solder bars. Die Size: 2.5 mm x 1.5 mm TYP RθJC Thermal Resistance, Junction-to-Case 1 RθJB Thermal Resistance, Junction-to-Board 2.5 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 64 UNIT °C/W • Ultra High Efficiency • No Reverse Recovery • Ultra Low QG • Small Footprint Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25°C unless otherwise stated) TEST CONDITIONS MIN BVDSS Drain-to-Source Voltage PARAMETER VGS = 0 V, ID = 0.5 mA 40 IDSS Drain-Source Leakage VGS = 0 V, VDS = 32 V 0.01 0.4 Gate-to-Source Forward Leakage VGS = 5 V 0.01 0.8 Gate-to-Source Forward Leakage# VGS = 5 V, TJ = 125°C 0.1 5 Gate-to-Source Reverse Leakage VGS = -4 V 0.01 0.4 1.1 2.5 V 3.6 mΩ IGSS VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 7 mA 0.7 TYP MAX UNIT V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 15 A 3 VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 mA V # Defined by design. Not subject to production test. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1 eGaN® FET DATASHEET EPC2055 Dynamic Characteristics (TJ = 25°C unless otherwise stated) PARAMETER CISS Input Capacitance# CRSS Reverse Transfer Capacitance COSS Output Capacitance# TEST CONDITIONS MIN VDS = 20 V, VGS = 0 V TYP MAX 841 1111 8.8 408 COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) RG Gate Resistance QG Total Gate Charge# UNIT pF 612 574 VDS = 0 to 20 V, VGS = 0 V 668 0.4 VDS = 20 V, VGS = 5 V, ID = 15 A QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge# QRR Source-Drain Recovery Charge Ω 6.6 8.5 2.3 VDS = 20 V, ID = 15 A 0.7 nC 1.6 VDS = 20 V, VGS = 0 V 13 20 0 # Defined by design. Not subject to production test. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 1: Typical Output Characteristics at 25°C 160 140 140 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 100 80 60 80 60 40 20 20 0 0.5 1.0 1.5 2.0 2.5 0 3.0 = 33 VV VDS DS = 100 40 0 25˚C 125˚C 120 ID – Drain Current (A) 120 ID – Drain Current (A) Figure 2: Transfer Characteristics 160 0.5 1.0 1.5 VDS – Drain-to-Source Voltage (V) Figure 3: RDS(on) vs. VGS for Various Drain Currents 3.0 3.5 4.0 4.5 5.0 Figure 4: RDS(on) vs. VGS for Various Temperatures ID = 7 A ID = 15 A ID = 22 A ID = 30 A 10 8 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 2.5 12 12 6 4 2 0 2.0 VGS – Gate-to-Source Voltage (V) 2.0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 10 25˚C 125˚C IVDDS==153 VA 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2055 Figure 5b: Capacitance (Log Scale) Figure 5a: Capacitance (Linear Scale) 1000 1000 COSS = CGD + CSD Capacitance (pF) Capacitance (pF) 800 CISS = CGD + CGS CRSS = CGD 600 400 100 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 200 0 0 10 20 30 1 40 VDS – Drain-to-Source Voltage (V) 20 0.28 4 15 0.21 10 0.14 5 0.07 10 15 20 25 30 35 VGS – Gate-to-Source Voltage (V) 5 EOSS – COSS Stored Energy (µJ) QOSS – Output Charge (nC) 0.35 5 0.00 40 40 ID = 15 A VDS = 20 V 2 1 0 0 1 2 3 4 5 6 7 QG – Gate Charge (nC) Figure 8: Reverse Drain-Source Characteristics Figure 9: Normalized On-State Resistance vs. Temperature 160 2.0 120 Normalized On-State Resistance RDS(on) 25˚C 125˚C 140 ISD – Source-to-Drain Current (A) 30 3 VDS – Drain-to-Source Voltage (V) VGS = 0 V 100 80 60 40 20 0 20 Figure 7: Gate Charge Figure 6: Output Charge and COSS Stored Energy 0 10 VDS – Drain-to-Source Voltage (V) 25 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 4.5 5.0 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 1.8 ID = 15 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 0 25 50 75 100 125 150 TJ – Junction Temperature (°C) | 3 eGaN® FET DATASHEET EPC2055 Figure 11: Safe Operating Area Figure 10: Normalized Threshold Voltage vs. Temperature 1000 1.4 ID = 7 mA I D – Drain Current (A) Normalized Threshold Voltage 1.3 1.2 1.1 1.0 0.9 100 Limited by RDS(on) 10 Pulse Width 1 ms 100 µs 1 0.8 0.7 0.6 10 µs 0 25 50 75 100 TJ – Junction Temperature (°C) 125 0.1 0.1 150 1 10 VDS - Drain-Source Voltage (V) 100 TJ = Max Rated, TC = +25°C, Single Pulse Figure 12: Transient Thermal Response Curves ZθJB, Normalized Thermal Impedance Junction-to-Board 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM t1 0.01 Single Pulse 0.001 -5 10 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-4 10-3 10-2 10-1 1 10+1 tp, Rectangular Pulse Duration, seconds ZθJC, Normalized Thermal Impedance Junction-to-Case 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 PDM t1 Single Pulse 0.001 0.0001 10-6 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 4 eGaN® FET DATASHEET EPC2055 TAPE AND REEL CONFIGURATION 4 mm pitch, 8 mm wide tape on 7” reel e f Loaded Tape Feed Direction g d 7” inch reel Die orientation dot b YYYY ZZZZ c a Gate solder bar is under this corner 2055 Die is placed into pocket solder bump side down (face side down) h DIM EPC2204 (Note 1) a b c (Note 2) d e f (Note 2) g h Dimension (mm) Target MIN MAX 8.00 7.90 8.30 1.75 1.65 1.85 3.50 3.45 3.55 4.00 3.90 4.10 4.00 3.90 4.10 2.00 1.95 2.05 1.50 1.50 1.60 0.50 0.45 0.55 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2055 YYYY Die orientation dot Laser Markings Part Number ZZZZ Gate Pad bump is under this corner EPC2055 DIE OUTLINE Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 2055 YYYY ZZZZ A Solder Bump View 6 B 5 c 4 MIN Nominal MAX A B 2470 1470 2500 1500 2530 1530 c 1175 d 1350 e 500 k 1 g j 3 d 2 h Micrometers DIM f Seating plane EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 250 300 h 825 j 787.5 k 225 Pad 1 is Gate; Pads 2 ,4, 6 are Source; Pads 3, 5 are Drain 120 ± 12 518 ± -25 638 Side View e f g | 5 eGaN® FET DATASHEET EPC2055 RECOMMENDED LAND PATTERN 2 6 B 5 c1 4 Pad 1 is Gate; Pads 2 ,4, 6 are Source; Pads 3, 5 are Drain h1 3 d1 j 1 g1 k (units in µm) Land pattern is solder mask defined Solder mask opening is 180 µm It is recommended to have on-Cu trace PCB vias A f1 e RECOMMENDED STENCIL DRAWING DIM Nominal A B c1 d1 e f1 g1 h1 j k 2500 1500 1155 1330 500 230 280 805 787.5 225 A B c1 h1 d1 j g1 k (units in µm) R60 f1 DIM Nominal A B c1 d1 e f1 g1 h1 j k 2500 1500 1155 1330 500 230 280 805 787.5 225 e Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. The corner has a radius of R60. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. Split stencil design can be provided upon request, but EPC has tested this stencil design and not found any scooping issues. Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Information subject to change without notice. Revised December, 2020 | 6