eGaN® FET DATASHEET
EPC2100
EPC2100 – Enhancement-Mode GaN Power
Transistor Half-Bridge
VDS , 30 V
RDS(on) , 8.2 mΩ (Q1), 2.1 mΩ (Q2)
ID , 10 A (Q1), 40 A (Q2)
EFFICIENT POWER CONVERSION
HAL
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
Maximum Ratings
DEVICE
PARAMETER
VDS
ID
Q1
VALUE
Drain-to-Source Voltage (Continuous)
30
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
36
Continuous (TA = 25°C, RθJA = 92°C/W)
10
Pulsed (25°C, TPULSE = 300 µs)
100
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
TJ
Operating Temperature
–40 to 150
TSTG
Storage Temperature
–40 to 150
VGS
VDS
ID
Q2
Drain-to-Source Voltage (Continuous)
30
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
36
Continuous (TA = 25°C, RθJA = 22°C/W)
40
Pulsed (25°C, TPULSE = 300 µs)
400
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
TJ
Operating Temperature
–40 to 150
TSTG
Storage Temperature
–40 to 150
VGS
V
EPC2100 eGaN® ICs are supplied only in
passivated die form with solder bumps
Die Size: 6.05 mm x 2.3 mm
A
Applications
UNIT
• High Frequency DC-DC
V
°C
V
• Point-of-Load (POL) Converters
Benefits
• High Frequency Operation
• Ultra High Efficiency
• High Density Footprint
A
V
°C
Thermal Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
TYP
RθJC
Thermal Resistance, Junction-to-Case
0.4
RθJB
Thermal Resistance, Junction-to-Board
2.5
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
42
UNIT
°C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 |
| 1
eGaN® FET DATASHEET
EPC2100
Static Characteristics (TJ = 25°C unless otherwise stated)
DEVICE
PARAMETER
30
TYP
MAX
UNIT
Drain-to-Source Voltage
VGS = 0 V, ID = 0.3 mA
IDSS
Drain-Source Leakage
VDS = 24 V, VGS = 0 V
0.004
0.2
mA
Gate-to-Source Forward Leakage
VGS = 5 V
0.007
3
mA
Gate-to-Source Reverse Leakage
VGS = -4 V
0.004
0.2
mA
V
VGS(TH)
Gate Threshold Voltage
VDS = VGS, ID = 4 mA
1.3
2.5
V
RDS(on)
Drain-Source On Resistance
VGS = 5 V, ID = 25 A
6
8.2
mΩ
VSD
Source-Drain Forward Voltage
IS = 0.5 A, VGS = 0 V
1.8
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 1 mA
IDSS
Drain-Source Leakage
IGSS
Q2
MIN
BVDSS
IGSS
Q1
TEST CONDITIONS
0.8
V
30
V
VDS = 24 V, VGS = 0 V
0.015
0.8
mA
Gate-to-Source Forward Leakage
VGS = 5 V
0.03
9
mA
Gate-to-Source Reverse Leakage
VGS = -4 V
0.015
0.8
mA
VGS(TH)
Gate Threshold Voltage
1.3
2.5
V
RDS(on)
Drain-Source On Resistance
VGS = 5 V, ID = 25 A
1.5
2.1
mΩ
VSD
Source-Drain Forward Voltage
IS = 0.5 A, VGS = 0 V
1.7
VDS = VGS, ID = 16 mA
0.8
V
Dynamic Characteristics
DEVICE
Q1
Q2
PARAMETER
CISS
Input Capacitance
CRSS
Reverse Transfer Capacitance
COSS
Output Capacitance
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
QG
Total Gate Charge
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
CISS
Input Capacitance
CRSS
Reverse Transfer Capacitance
COSS
Output Capacitance
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
QG
Total Gate Charge
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
TEST CONDITIONS
VDS = 15 V, VGS = 0 V
MIN
TYP
MAX
395
475
15
290
VDS = 0 to 15 V, VGS = 0 V
VDS = 15 V, VGS = 5 V, ID = 25 A
UNIT
435
pF
371
404
3.6
4.9
1.3
VDS = 15 V, ID = 25 A
0.6
nC
0.9
VDS = 15 V, VGS = 0 V
6.1
9.2
0
1630
VDS = 15 V, VGS = 0 V
64
1370
VDS = 0 to 15 V, VGS = 0 V
VDS = 15 V, VGS = 5 V, ID = 25 A
1960
2060
pF
1740
1900
15
19
4.8
VDS = 15 V, ID = 25 A
2.7
nC
3.4
VDS = 15 V, VGS = 0 V
29
44
0
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
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| 2
eGaN® FET DATASHEET
EPC2100
Figure 1a (Q1): Typical Output Characteristics at 25°C
Figure 1b (Q2): Typical Output Characteristics at 25°C
100
400
VGS = 5 V
VGS = 5 V
VGS = 4 V
VGS = 4 V
VGS = 3 V
ID – Drain Current (A)
ID – Drain Current (A)
80
VGS = 2 V
60
40
300
VGS = 3 V
VGS = 2 V
200
100
20
0
0
0.5
1.0
1.5
2.0
2.5
VDS – Drain-to-Source Voltage (V)
0
3.0
Figure 2a (Q1): Transfer Characteristics
0.5
1.0
1.5
2.0
2.5
VDS – Drain-to-Source Voltage (V)
3.0
Figure 2b (Q2): Transfer Characteristics
100
400
25˚C
125˚C
80
25˚C
125˚C
300
VDS = 3 V
ID – Drain Current (A)
ID – Drain Current (A)
0
60
40
VDS = 3 V
200
100
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
4.0
4.5
0
0.5
5.0
1.0
1.5
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
4.0
4.5
5.0
Figure 3b (Q2): RDS(on) vs. VGS for Various Drain Currents
Figure 3a (Q1): RDS(on) vs. VGS for Various Drain Currents
20
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
6
ID = 15 A
ID = 25 A
ID = 35 A
ID = 50 A
15
10
5
0
2.5
3.0
3.5
4.0
4.5
5.0
ID = 15 A
ID = 25 A
ID = 35 A
ID = 50 A
5
4
3
2
1
0
VGS – Gate-to-Source Voltage (V)
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2.5
3.0
3.5
4.0
4.5
5.0
VGS – Gate-to-Source Voltage (V)
| 3
eGaN® FET DATASHEET
EPC2100
Figure 4a (Q1): RDS(on) vs. VGS for Various Temperatures
Figure 4b (Q2): RDS(on) vs. VGS for Various Temperatures
20
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
6
25˚C
125˚C
ID = 25 A
15
10
5
0
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5
ID = 25 A
4
3
2
1
0
5.0
Figure 5a (Q1): Capacitance (Linear Scale)
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
Figure 5b (Q1): Capacitance (Log Scale)
1000
800
100
Capacitance (pF)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
600
Capacitance (pF)
25˚C
125˚C
400
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
10
200
0
0
5
10
15
20
25
1
30
VDS – Drain-to-Source Voltage (V)
0
5
10
15
20
VDS – Drain-to-Source Voltage (V)
25
30
Figure 5d (Q2): Capacitance (Log Scale)
Figure 5c (Q2): Capacitance (Linear Scale)
3000
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
2000
1000
Capacitance (pF)
Capacitance (pF)
2500
1500
1000
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
100
500
0
0
5
10
15
20
VDS – Drain-to-Source Voltage (V)
25
30
10
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0
5
10
15
20
25
30
VDS – Drain-to-Source Voltage (V)
| 4
eGaN® FET DATASHEET
Figure
Output
Charge
COSS Stored Energy
Figure 6b
6a:(Q2):
Output
Charge
and Cand
OSS Stored Energy
0.10
50
0.5
8
0.08
40
0.4
6
0.06
30
0.3
4
0.04
20
0.2
2
0.02
10
0.1
0.00
0
0
0
5
10
15
20
25
30
QOSS – Output Charge (nC)
10
EOSS – COSS Stored Energy (μJ)
60
0
5
10
ID = 25 A
VDS = 15 V
4
VGS – Gate-to-Source Voltage (V)
VGS – Gate-to-Source Voltage (V)
30
0.0
5
5
3
2
1
0
1
2
3
QG – Gate Charge (nC)
3
2
1
0
4
ID = 25 A
VDS = 15 V
4
Figure 8a (Q1): Reverse Drain-Source Characteristics
0
5
QG – Gate Charge (nC)
10
15
Figure 8b (Q2): Reverse Drain-Source Characteristics
100
400
25˚C
125˚C
80
ISD – Source-to-Drain Current (A)
ISD – Source-to-Drain Current (A)
25
Figure 7b (Q2): Gate Charge
Figure 7a (Q1): Gate Charge
VGSDS = 03 V
60
40
20
0
20
VDS – Drain-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V)
0
15
0.6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VSD – Source-to-Drain Voltage (V)
4.0
4.5
5.0
25˚C
125˚C
300
VGSDS = 03 V
200
100
0
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0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VSD – Source-to-Drain Voltage (V)
4.0
4.5
5.0
| 5
EOSS – COSS Stored Energy (μJ)
Figure
Output
Charge
COSS Stored Energy
Figure 6a
6a:(Q1):
Output
Charge
and Cand
OSS Stored Energy
0.12
12
QOSS – Output Charge (nC)
EPC2100
eGaN® FET DATASHEET
EPC2100
Figure 9a (Q1):
Normalized On-State Resistance vs. Temperature
Figure 9b (Q2):
Normalized On-State Resistance vs. Temperature
2.0
Normalized On-State Resistance RDS(on)
Normalized On-State Resistance RDS(on)
2.0
1.8
ID = 25 A
VGS = 5 V
1.6
1.4
1.2
1.0
0.8
0
25
50
75
100
TJ – Junction Temperature (°C)
125
1.8
1.4
1.2
1.0
0.8
150
1.4
1.4
1.3
1.3
Normalized Threshold Voltage
Normalized Threshold Voltage
0
ID = 4 mA
1.1
1.0
0.9
0.8
50
75
100
TJ – Junction Temperature (°C)
125
150
1.2
ID = 16 mA
1.1
1.0
0.9
0.8
0.7
0.7
0.6
0
25
50
75
100
TJ – Junction Temperature (°C)
125
0.6
150
Figure 11a (Q1): Safe Operating Area
100
100
I D – Drain Current (A)
1000
10
Limited by RDS(on)
ms
Pulse100
Width
10 ms
1
ms
1 ms
250 µs
1
0
25
50
1
100
125
150
Limited by RDS(on)
10
Pulse Width
100 ms1 ms
10 ms 250 µs
1 ms
100 µs 100 µs
10 µs
1
100 µs
0.1
0.1
75
TJ – Junction Temperature (°C)
Figure 11b (Q2): Safe Operating Area
1000
I D – Drain Current (A)
25
Figure 10b (Q2):
Normalized Threshold Voltage vs. Temperature
Figure 10a (Q1):
Normalized Threshold Voltage vs. Temperature
1.2
ID = 25 A
VGS = 5 V
1.6
10
100
0.1
0.1
VDS – Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
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1
10
100
VDS – Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
| 6
eGaN® FET DATASHEET
Junction-to-Board
1
ZθJB, Normalized Thermal Impedance
Figure 12a
Transient Thermal
Response Curves
EPC2100
Duty Cycle:
0.5
0.2
0.1
0.1
0.05
PDM
0.02
t1
0.01 0.01
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
Single Pulse
0.001
10-5
10-4
10-3
10-2
10-1
1
101
tp, Rectangular Pulse Duration, seconds
Junction-to-Case
ZθJC, Normalized Thermal Impedance
Figure 12b
Transient Thermal
Response Curves
1 Duty Cycle:
0.5
0.2
0.1
0.1
0.05
PDM
0.02
t1
0.01 0.01
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
0.001
10-6
10-5
10-4
10-3
10-2
10-1
1
tp, Rectangular Pulse Duration, seconds
Figure 13
Typical Application Circuit
eGaNIC
Gate driver/
controller
VB
HO
VS
VCC
GND
VIN
+
LO
VIN
Gate 1
GR1
Gate 2
_
Q1
VSW
Q2
VOUT
+
RLoad
PGND
_
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| 7
eGaN® FET DATASHEET
EPC2100
TAPE AND REEL CONFIGURATION
Loaded Tape Feed Direction
4mm pitch, 12mm wide tape on 7” reel
d
e
f
g
Gate bumps are along this edge of the die
7” reel
b
ZZZZ
a
c
Die
orientation
dot
YYYY
2100
Die is placed into pocket
solder ball side down
(face side down)
EPC2100 (note 1)
Dimension (mm) target
a
b
c (see note)
d
e
f (see note)
g
12.00
1.75
5.50
4.00
4.00
2.00
1.50
min
11.70
1.65
5.45
3.90
3.90
1.95
1.50
max
12.30
1.85
5.55
4.10
4.10
2.05
1.60
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
2100
YYYY
ZZZZ
Part
Number
EPC2100
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
2100
YYYY
Lot_Date Code
Marking Line 3
ZZZZ
Die orientation dot
Gate bumps are along this edge of the die
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| 8
eGaN® FET DATASHEET
EPC2100
DIE OUTLINE
Solder Bump View
A
10
15
20
25
30
35
40
45
50
55
60
65
70
75
4
9
14
19
24
29
34
39
44
49
54
59
64
69
74
3
8
13
18
23
28
33
38
43
48
53
58
63
68
73
2
7
12
17
22
27
32
37
42
47
52
57
62
67
72
1
6
11
16
21
26
31
36
41
46
51
56
61
66
71
e
e
Nominal
MAX
A
B
c
d
e
f
6020
2270
400
450
210
187
6050
2300
400
450
225
208
6080
2330
400
450
240
240
Pad 2 is Gate1 (high side); Pad 4 is Gate2 (low side);
Pad 3 is HS Gate Return;
Pads 5, 12, 13, 14, 15, 22, 23, 24, 25, 32, 33, 34, 35,
42, 43, 44, 45, 52, 53, 54, 55, 62, 63, 64, 65, 72, 73,
74, 75 are Ground;
f
c
MIN
B
d
5
DIM
Side View
(785)
160+/−16
(625)
Pads 1, 11, 21, 31, 41, 51, 61, 71 are VIN ;
Seating plane
Pads 6, 7, 8, 9, 10, 16, 17, 18, 19, 20, 26, 27, 28, 29,
30, 36, 37, 38, 39, 40, 46, 47, 48, 49, 50, 56, 57, 58,
59, 60, 66, 67, 68, 69, 70 are Switch Node
RECOMMENDED LAND PATTERN
(measurements in µm)
6050
6
11
16
21
26
31
36
41
46
51
56
61
66
71
2
7
12
17
22
27
32
37
42
47
52
57
62
67
72
3
8
13
18
23
28
33
38
43
48
53
58
63
68
73
4
9
14
19
24
29
34
39
44
49
54
59
64
69
74
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
The land pattern is solder mask defined.
Suggest SMD Pads at 200 +20/–10 µm.
190 µm minimum.
2300
450
1
400
RECOMMENDED STENCIL DRAWING
(measurements in µm)
6050
Recommended stencil should be 4 mil (100 µm)
thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 4 solder,
reference 88.5% metals content.
2300
275
450
225
Additional assembly resources available at:
https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
400
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 |
Information subject to
change without notice.
Revised August 2019
| 9