EPC2103

eGaN® FET DATASHEET EPC2103 EPC2103 – Enhancement-Mode GaN Power Transistor Half-Bridge VDS , 80 V RDS(on) , 5.5 mΩ ID , 30 A EFFICIENT POWER CONVERSION HAL Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings DEVICE PARAMETER VDS Q1 & Q2 ID VALUE Drain-to-Source Voltage (Continuous) 80 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 96 Continuous (TA = 25˚C, RθJA = 13°C/W) 30 Pulsed (25°C, TPULSE = 300 µs) 195 UNIT V A Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 VGS V Applications • High Frequency DC-DC • Motor Drive °C Benefits • Ultra High Efficiency Thermal Characteristics PARAMETER EPC2103 eGaN® ICs are supplied only in passivated die form with solder bumps Die Size: 6.05 mm x 2.3 mm TYP RθJC Thermal Resistance, Junction-to-Case 0.3 RθJB Thermal Resistance, Junction-to-Board 2.2 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 42 UNIT °C/W • High Frequency Operation • High Density Footprint Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details Static Characteristics (TJ = 25°C unless otherwise stated) DEVICE Q1 & Q2 PARAMETER TEST CONDITIONS MIN 80 BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.5 mA IDSS Drain-Source Leakage IGSS TYP MAX UNIT V VDS = 64 V, VGS = 0 V 0.007 0.4 mA Gate-to-Source Forward Leakage VGS = 5 V 0.013 6.5 mA Gate-to-Source Reverse Leakage VGS = -4 V 0.007 0.4 mA 1.3 2.5 V 5.5 mΩ VGS(TH) Gate Threshold Voltage RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 20 A 4 VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | VDS = VGS, ID = 7 mA 0.8 V | 1 eGaN® FET DATASHEET EPC2103 Dynamic Characteristics (TJ = 25°C unless otherwise stated) DEVICE Q1 Q2 PARAMETER CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge TEST CONDITIONS VDS = 40 V, VGS = 0 V MIN TYP MAX 730 880 7 445 VDS = 0 to 40 V, VGS = 0 V VDS = 40 V, VGS = 5 V, ID = 20 A UNIT 670 pF 573 733 6.5 8 2.2 VDS = 40 V, ID = 20 A 1.1 nC 1.5 VDS = 40 V, VGS = 0 V 30 45 0 730 VDS = 40 V, VGS = 0 V 7 525 VDS = 0 to 40 V, VGS = 0 V VDS = 40 V, VGS = 5 V, ID = 20 A 880 790 pF 668 855 6.5 8 2.2 VDS = 40 V, ID = 20 A 1.1 nC 1.5 VDS = 40 V, VGS = 0 V 34 51 0 Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 2 eGaN® FET DATASHEET EPC2103 Figure 1 (Q1 & Q2): Typical Output Characteristics at 25°C Figure 2 (Q1 & Q2): Transfer Characteristics VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 100 50 0 VDS = 3 V 100 50 0 0.5 1.0 1.5 2.0 VDS – Drain-to-Source Voltage (V) 2.5 0 0.5 3.0 Figure 3 (Q1 & Q2): RDS(on) vs. VGS for Various Drain Currents 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 16 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 1.0 Figure 4 (Q1 & Q2): RDS(on) vs. VGS for Various Temperatures 16 ID = 10 A ID = 20 A ID = 30 A ID = 40 A 12 8 4 0 25˚C 125˚C 150 ID – Drain Current (A) ID – Drain Current (A) 150 2.5 3.0 3.5 4.0 4.5 25˚C 125˚C 12 ID = 20 A 8 4 0 5.0 VGS – Gate-to-Source Voltage (V) 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 Figure 5b (Q1): Capacitance (Log Scale) Figure 5a (Q1): Capacitance (Linear Scale) 2000 1000 Capacitance (pF) Capacitance (pF) COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1500 1000 100 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 500 0 0 20 40 60 80 VDS – Drain-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 1 0 20 40 60 80 VDS – Drain-to-Source Voltage (V) | 3 eGaN® FET DATASHEET EPC2103 Figure 5c (Q2): Capacitance (Linear Scale) Figure 5d (Q2): Capacitance (Log Scale) 2000 1000 Capacitance (pF) Capacitance (pF) COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1500 1000 100 10 500 0 20 40 60 1 80 0 20 40 VDS – Drain-to-Source Voltage (V) 80 Figure Output Charge COSS Stored Energy Figure 6a 6a:(Q1): Output Charge and Cand OSS Stored Energy Figure Output Charge COSS Stored Energy Figure 6b 6a:(Q2): Output Charge and Cand OSS Stored Energy 40 1.6 50 2.0 40 1.6 30 1.2 30 1.2 20 0.8 10 0.4 20 0.8 10 0 QOSS – Output Charge (nC) 60 EOSS – COSS Stored Energy (μJ) 2.0 50 QOSS – Output Charge (nC) 60 VDS – Drain-to-Source Voltage (V) 0.4 0 20 40 60 80 0 0.0 0 20 40 60 2.4 80 0.0 VDS – Drain-to-Source Voltage (V) VDS – Drain-to-Source Voltage (V) Figure 8 (Q1 & Q2): Reverse Drain-Source Characteristics Figure 7 (Q1 & Q2): Gate Charge ID = 20 A VDS = 40 V 4 ISD – Source-to-Drain Current (A) VGS – Gate-to-Source Voltage (V) 5 3 2 1 0 0 2 4 QG – Gate Charge (nC) 6 8 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 25˚C 125˚C 150 VGSDS = 03 V 100 50 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 4.5 5.0 | 4 EOSS – COSS Stored Energy (μJ) 0 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD eGaN® FET DATASHEET EPC2103 Figure 9 (Q1 & Q2): Normalized On-State Resistance vs. Temperature Figure 10 (Q1 & Q2): Normalized Threshold Voltage vs. Temperature 1.400 1.300 Normalized Threshold Voltage 1.8 ID = 20 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 1.200 ID = 7 mA 1.100 1.000 0.900 0.800 0.700 0 25 50 75 100 TJ – Junction Temperature (°C) Figure 11a Transient Thermal Response Curves 125 0.600 150 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 (Q1 & Q2) Junction-to-Board ZθJB, Normalized Thermal Impedance Normalized On-State Resistance RDS(on) 2.0 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 PDM 0.02 t1 0.01 0.01 Notes: Single Pulse Duty Factor: D= t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB Single Pulse 0.001 10-5 t2 10-4 10-3 10-2 10-1 1 101 tp, Rectangular Pulse Duration, seconds (Q1 & Q2) Junction-to-Case ZθJC, Normalized Thermal Impedance Figure 11b Transient Thermal Response Curves 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 PDM 0.02 t1 0.01 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.001 10-6 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 5 eGaN® FET DATASHEET EPC2103 Figure 12 (Q1 & Q2): Safe Operating Area Figure 13: Typical Application Circuit 1000 I D – Drain Current (A) eGaNIC Gate driver/ controller 100 VIN VB 10 0.1 0.1 1 GR1 VS Pulse Width 1 ms 250 µs 100 µs 1 Gate 1 HO Limited by RDS(on) VCC GND VIN + Q1 VSW Gate 2 LO _ VOUT + RLoad Q2 PGND _ 10 100 VDS – Drain-Source Voltage (V) TJ = Max Rated, TC = +25°C, Single Pulse TAPE AND REEL CONFIGURATION e 8 mm pitch, 12 mm wide tape on 7” reel d 7” inch reel g f Loaded Tape Feed Direction Gate solder bump is under this corner a b c Die orientation dot YYYY ZZZZ 2103 h DIM EPC2103 (Note 1) a b c (Note 2) d e f (Note 2) g h Dimension (mm) Target MIN MAX 12.00 11.90 12.30 1.75 1.65 1.85 5.50 5.45 5.55 4.00 3.90 4.10 8.00 7.90 8.10 2.00 1.95 2.05 1.50 1.50 1.60 1.50 1.50 1.75 Die is placed into pocket solder bump side down (face side down) Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2103 YYYY ZZZZ Die orientation dot Part Number EPC2103 Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 2103 YYYY ZZZZ Gate bumps are along this edge of the die EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 6 eGaN® FET DATASHEET EPC2103 DIE OUTLINE Solder Bump View A 10 15 20 25 30 35 40 45 50 55 60 65 70 75 4 9 14 19 24 29 34 39 44 49 54 59 64 69 74 3 8 13 18 23 28 33 38 43 48 53 58 63 68 73 2 7 12 17 22 27 32 37 42 47 52 57 62 67 72 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 e e Nominal MAX A B c d e f 6020 2270 400 450 210 187 6050 2300 400 450 225 208 6080 2330 400 450 240 229 Pad 2 is Gate 1 (high side); Pad 3 is HS Gate Return; Pad 4 is G2; Pads 1, 11, 12, 13, 21, 22, 23, 31, 32, 33, 41, 42, 51, 52, 61, 62, 71, 72 are VIN ; f c MIN B d 5 DIM Side View (785) 160+/−16 (625) Pads 5, 14, 15, 24, 25, 34, 35, 43, 44, 45, 53, 54, 55, 63, 64, 65, 73, 74, 75 Ground; Seating plane Pads 6, 7, 8, 9, 10, 16, 17, 18, 19, 20, 26, 27, 28, 29, 30, 36, 37, 38, 39, 40, 46, 47, 48, 49, 50, 56, 57, 58, 59, 60, 66, 67, 68, 69, 70 are Switch Node RECOMMENDED LAND PATTERN (measurements in µm) 6050 6 11 16 21 26 31 36 41 46 51 56 61 66 71 2 7 12 17 22 27 32 37 42 47 52 57 62 67 72 3 8 13 18 23 28 33 38 43 48 53 58 63 68 73 4 9 14 19 24 29 34 39 44 49 54 59 64 69 74 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 The land pattern is solder mask defined. Suggest SMD Pads at 200 +20/–10 µm. 190 µm minimum. 2300 450 1 400 RECOMMENDED STENCIL DRAWING (measurements in µm) 6050 Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. 2300 275 450 225 Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx 400 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Information subject to change without notice. Revised June, 2020 | 7