EPC2104

eGaN® FET DATASHEET EPC2104 EPC2104 – Enhancement-Mode GaN Power Transistor Half-Bridge VDS , 100 V RDS(on) , 6.8 mΩ ID , 30 A EFFICIENT POWER CONVERSION HAL Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings DEVICE PARAMETER VDS Q1 & Q2 ID VGS VALUE Drain-to-Source Voltage (Continuous) 100 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120 Continuous (TA = 25°C, RθJA = 10°C/W) 30 Pulsed (25°C, TPULSE = 300 µs) 180 Gate-to-Source Voltage UNIT V A 6 V Gate-to-Source Voltage -4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 EPC2104 eGaN® ICs are supplied only in passivated die form with solder bumps Die Size: 6.05 mm x 2.3 mm Applications • High Frequency DC-DC • Motor Drive °C Benefits • Ultra High Efficiency Thermal Characteristics PARAMETER Q1 & Q2 • High Frequency Operation TYP RθJC Thermal Resistance, Junction-to-Case 0.3 RθJB Thermal Resistance, Junction-to-Board 2.2 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 42 UNIT • High Density Footprint °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details Static Characteristics (TJ = 25°C unless otherwise stated) DEVICE Q1 & Q2 TEST CONDITIONS MIN BVDSS Drain-to-Source Voltage PARAMETER VGS = 0 V, ID = 0.5 mA 100 IDSS Drain-Source Leakage VDS = 80 V, VGS = 0 V 0.006 0.4 mA Gate-to-Source Forward Leakage VGS = 5 V 0.012 5.5 mA Gate-to-Source Reverse Leakage VGS = -4 V 0.006 0.4 mA 1.3 2.5 V 6.8 mΩ IGSS TYP Gate Threshold Voltage VDS = VGS, ID = 6 mA RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 20 A 5 VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | UNIT V VGS(TH) 0.8 MAX V | 1 eGaN® FET DATASHEET EPC2104 Dynamic Characteristics (TJ = 25°C unless otherwise stated) DEVICE PARAMETER Q1 Q2 TEST CONDITIONS CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge MIN VDS = 50 V, VGS = 0 V TYP MAX 730 880 UNIT 5 430 pF 645 545 VDS = 0 to 50 V, VGS = 0 V 699 VDS = 50 V, VGS = 5 V, ID = 20 A 6.8 8.7 2.3 VDS = 50 V, ID = 20 A 1.4 nC 1.6 VDS = 50 V, VGS = 0 V 35 53 0 730 VDS = 50 V, VGS = 0 V 880 5 500 pF 750 631 VDS = 0 to 50 V, VGS = 0 V 812 VDS = 50 V, VGS = 5 V, ID = 20 A 6.8 8.7 2.3 VDS = 50 V, ID = 20 A 1.4 nC 1.6 VDS = 50 V, VGS = 0 V 41 62 0 Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 1 (Q1 & Q2): Typical Output Characteristics at 25°C VGS = 5 V 150 25˚C 125˚C VGS = 4 V ID – Drain Current (A) ID – Drain Current (A) 150 Figure 2 (Q1 & Q2): Transfer Characteristics VGS = 3 V VGS = 2 V 100 50 0 0 0.5 1.0 1.5 2.0 VDS – Drain-to-Source Voltage (V) 2.5 3.0 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | VDS = 3 V 100 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 | 2 eGaN® FET DATASHEET EPC2104 Figure 4 (Q1 & Q2): RDS(on) vs. VGS for Various Temperatures Figure 3 (Q1 & Q2): RDS(on) vs. VGS for Various Drain Currents 20 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 20 ID = 10 A ID = 20 A ID = 30 A ID = 40 A 15 10 5 0 2.5 3.0 3.5 4.0 4.5 ID = 20 A 10 5 0 5.0 25˚C 125˚C 15 2.5 3.0 3.5 Figure 5a (Q1): Capacitance (Linear Scale) 4.0 4.5 VGS – Gate-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V) 5.0 Figure 5b (Q1): Capacitance (Log Scale) 2000 1000 Capacitance (pF) 1500 Capacitance (pF) COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 500 0 100 0 25 50 75 1 100 VDS – Drain-to-Source Voltage (V) 0 25 50 75 100 VDS – Drain-to-Source Voltage (V) Figure 5c (Q2): Capacitance (Linear Scale) Figure 5d (Q2): Capacitance (Log Scale) 2000 1000 Capacitance (pF) Capacitance (pF) COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1500 1000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 500 0 100 0 25 50 75 100 VDS – Drain-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 1 0 25 50 75 100 VDS – Drain-to-Source Voltage (V) | 3 eGaN® FET DATASHEET EPC2104 Figure 6b (Q2): Output Charge and COSS Stored Energy 2.8 50 2.5 60 2.4 40 2.0 50 2.0 40 1.6 30 1.5 30 1.2 20 0.8 10 0.4 1.0 20 0.5 10 0 0 25 50 75 100 0 0 VDS – Drain-to-Source Voltage (V) EOSS – COSS Stored Energy (μJ) 70 QOSS – Output Charge (nC) 3.0 EOSS – COSS Stored Energy (μJ) QOSS – Output Charge (nC) Figure 6a (Q1): Output Charge and COSS Stored Energy 60 0 25 50 75 0 100 VDS – Drain-to-Source Voltage (V) Figure 7 (Q1 & Q2): Gate Charge Figure 8 (Q1 & Q2): Reverse Drain-Source Characteristics ID = 20 A VDS = 50 V 4 ISD – Source-to-Drain Current (A) VGS – Gate-to-Source Voltage (V) 5 3 2 1 0 0 2 4 QG – Gate Charge (nC) 6 150 25˚C 125˚C 50 0 8 Figure 9 (Q1 & Q2): Normalized On-State Resistance vs. Temperature 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VSD – Source-to-Drain Voltage (V) 4.5 5.0 1.4 1.3 1.8 Normalized Threshold Voltage Normalized On-State Resistance RDS(on) 0 Figure 10 (Q1 & Q2): Normalized Threshold Voltage vs. Temperature 2.0 ID = 20 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 VGSDS = 03 V 100 1.2 ID = 6 mA 1.1 1.0 0.9 0.8 0.7 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 0.6 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 | 4 eGaN® FET DATASHEET Transient Thermal Response Curves (Junction-to-Board) 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 ZθJB, Normalized Thermal Impedance Figure 11a Transient Thermal Response Curves EPC2104 PDM 0.02 t1 0.01 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB Single Pulse 0.001 10-5 t2 10-4 10-3 10-2 10-1 1 101 tp, Rectangular Pulse Duration, seconds Transient Thermal Response Curves (Junction-to-Case) 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 ZθJC, Normalized Thermal Impedance Figure 11b Transient Thermal Response Curves PDM 0.02 t1 0.01 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.001 10-6 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds Figure 12 (Q1 & Q2): Safe Operating Area Figure 13: Typical Application Circuit 1000 I D – Drain Current (A) 10 VB Limited by RDS(on) HO VS Pulse Width 1 ms 100 µs 10 µs 1 0.1 0.1 eGaNIC Gate driver/ controller 100 1 VCC GND 10 100 1000 VIN + LO VIN Gate 1 GR1 Gate 2 _ Q1 VSW Q2 VOUT + RLoad PGND _ VDS – Drain-Source Voltage (V) TJ = Max Rated, TC = +25°C, Single Pulse EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 5 eGaN® FET DATASHEET EPC2104 TAPE AND REEL CONFIGURATION e 8 mm pitch, 12 mm wide tape on 7” reel d 7” inch reel g f Loaded Tape Feed Direction Gate solder bump is under this corner a b c Die orientation dot YYYY ZZZZ 2104 h DIM EPC2104 (Note 1) a b c (Note 2) d e f (Note 2) g h Dimension (mm) Target MIN MAX 12.00 11.90 12.30 1.75 1.65 1.85 5.50 5.45 5.55 4.00 3.90 4.10 8.00 7.90 8.10 2.00 1.95 2.05 1.50 1.50 1.60 1.50 1.50 1.75 Die is placed into pocket solder bump side down (face side down) Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2104 YYYY ZZZZ Die orientation dot Part Number EPC2104 Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 2104 YYYY ZZZZ Gate bumps are along this edge of the die EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 6 eGaN® FET DATASHEET EPC2104 DIE OUTLINE Solder Bump View A 10 15 20 25 30 35 40 45 50 55 60 65 70 75 4 9 14 19 24 29 34 39 44 49 54 59 64 69 74 3 8 13 18 23 28 33 38 43 48 53 58 63 68 73 2 7 12 17 22 27 32 37 42 47 52 57 62 67 72 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 e A B c d e f 6020 2270 400 450 210 187 6050 2300 400 450 225 208 6080 2330 400 450 240 229 B MAX (625) Pads 5, 14, 15, 24, 25, 34, 35, 43, 44, 45, 53, 54, 55, 63, 64, 65, 73, 74, 75 Ground; Pads 6, 7, 8, 9, 10, 16, 17, 18, 19, 20, 26, 27, 28, 29, 30, 36, 37, 38, 39, 40, 46, 47, 48, 49, 50, 56, 57, 58, 59, 60, 66, 67, 68, 69, 70 are Switch Node 160+/−16 Side View Nominal Pads 1, 11, 12, 13, 21, 22, 23, 31, 32, 33, 41, 42, 51, 52, 61, 62, 71, 72 are VIN; f c MIN Pad 2 is G1; Pad 3 is Q1 Gate Return; Pad 4 is G2; (785) e d 5 DIM Seating plane RECOMMENDED LAND PATTERN (measurements in µm) 6050 6 11 16 21 26 31 36 41 46 51 56 61 66 71 2 7 12 17 22 27 32 37 42 47 52 57 62 67 72 3 8 13 18 23 28 33 38 43 48 53 58 63 68 73 4 9 14 19 24 29 34 39 44 49 54 59 64 69 74 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 The land pattern is solder mask defined. Suggest SMD Pads at 200 +20/–10 µm. 190 µm minimum. 2300 450 1 400 RECOMMENDED STENCIL DRAWING (measurements in µm) 6050 Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. 2300 275 450 225 Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx 400 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Information subject to change without notice. Revised June, 2020 | 7