EPC2105ENGRT

eGaN® FET DATASHEET EPC2105 EPC2105 – Enhancement-Mode GaN Power Transistor Half-Bridge VDS , 80 V RDS(on) , 14.5 mΩ (Q1), 3.6 mΩ (Q2) ID , 10 A (Q1), 40 A (Q2) EFFICIENT POWER CONVERSION HAL Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings DEVICE PARAMETER VDS ID Q1 VGS VALUE Drain-to-Source Voltage (Continuous) 80 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 96 Continuous (TA = 25°C, RθJA = 45°C/W) 10 Pulsed (25°C, TPULSE = 300 µs) 70 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 VDS ID Q2 Drain-to-Source Voltage (Continuous) 80 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 96 Continuous (TA = 25°C, RθJA = 11°C/W) 40 Pulsed (25°C, TPULSE = 300 µs) 300 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 VGS UNIT V A V °C V A EPC2105 eGaN® ICs are supplied only in passivated die form with solder bumps Die Size: 6.05 mm x 2.3 mm Applications • High Frequency DC-DC Benefits • High Frequency Operation • Ultra High Efficiency • High Density Footprint V °C Thermal Characteristics PARAMETER Q1 TYP RθJC Thermal Resistance, Junction-to-Case 0.4 RθJB Thermal Resistance, Junction-to-Board 2.5 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 42 UNIT °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1 eGaN® FET DATASHEET EPC2105 Static Characteristics (TJ = 25°C unless otherwise stated) DEVICE PARAMETER 80 TYP MAX UNIT Drain-to-Source Voltage VGS = 0 V, ID = 0.3 mA IDSS Drain-Source Leakage VDS = 64 V, VGS = 0 V 0.003 0.2 mA Gate-to-Source Forward Leakage VGS = 5 V 0.005 2.5 mA Gate-to-Source Reverse Leakage VGS = -4 V 0.003 0.2 mA V VGS(TH) Gate Threshold Voltage 1.3 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 20 A 10 14.5 mΩ VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.7 BVDSS Drain-to-Source Voltage IDSS Drain-Source Leakage IGSS Q2 MIN BVDSS IGSS Q1 TEST CONDITIONS VDS = VGS, ID = 2.5 mA VGS = 0 V, ID = 0.75 mA 0.8 V 80 V VDS = 64 V, VGS = 0 V 0.01 0.55 mA Gate-to-Source Forward Leakage VGS = 5 V 0.02 9 mA Gate-to-Source Reverse Leakage VGS = -4 V 0.01 0.55 mA VGS(TH) Gate Threshold Voltage 1.3 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 20 A 2.4 3.6 mΩ VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.5 VDS = VGS, ID = 10 mA 0.8 V Dynamic Characteristics (TJ = 25°C unless otherwise stated) DEVICE Q1 Q2 PARAMETER CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge TEST CONDITIONS VDS = 40 V, VGS = 0 V MIN TYP MAX 300 360 3 170 VDS = 0 to 40 V, VGS = 0 V VDS = 40 V, VGS = 5 V, ID = 20 A UNIT 255 pF 215 269 2.7 3.5 0.9 VDS = 40 V, ID = 20 A 0.5 nC 0.6 VDS = 40 V, VGS = 0 V 11 17 0 1170 VDS = 40 V, VGS = 0 V 12 780 VDS = 0 to 40 V, VGS = 0 V VDS = 40 V, VGS = 5 V, ID = 20 A 1410 1170 pF 1000 1270 11 15 3 VDS = 40 V, ID = 20 A 2.1 nC 2 VDS = 40 V, VGS = 0 V 51 77 0 Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 2 eGaN® FET DATASHEET EPC2105 Figure 1a (Q1): Typical Output Characteristics at 25°C Figure 1b (Q2): Typical Output Characteristics at 25°C 300 ID – Drain Current (A) ID – Drain Current (A) 60 40 VGS = 5 V VGS = 4 V VGS = 3 V 20 200 VGS = 5 V 100 VGS = 4 V VGS = 2 V VGS = 3 V VGS = 2 V 0 0 0.5 1.0 1.5 2.0 2.5 VDS – Drain-to-Source Voltage (V) 0 3.0 Figure 2a (Q1): Transfer Characteristics 0 0.5 1.0 1.5 2.0 2.5 VDS – Drain-to-Source Voltage (V) 3.0 Figure 2b (Q2): Transfer Characteristics 300 25˚C 125˚C 25˚C 125˚C VDS = 3 V ID – Drain Current (A) ID – Drain Current (A) 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 VDS = 3 V 200 100 0 0.5 5.0 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 Figure 3b (Q2): RDS(on) vs. VGS for Various Drain Currents Figure 3a (Q1): RDS(on) vs. VGS for Various Drain Currents RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 40 ID = 10 A ID = 20 A ID = 30 A ID = 40 A 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 VGS – Gate-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 8 ID = 10 A ID = 20 A ID = 30 A ID = 40 A 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VGS – Gate-to-Source Voltage (V) | 3 eGaN® FET DATASHEET EPC2105 Figure 4a (Q1): RDS(on) vs. VGS for Various Temperatures Figure 4b (Q2): RDS(on) vs. VGS for Various Temperatures RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 40 25˚C 125˚C 30 ID = 20 A 20 10 0 2.5 3.0 3.5 4.0 4.5 VGS – Gate-to-Source Voltage (V) 8 25˚C 125˚C ID = 20 A 6 4 2 0 5.0 2.0 Figure 5a (Q1): Capacitance (Linear Scale) 3.0 3.5 4.0 4.5 VGS – Gate-to-Source Voltage (V) 5.0 Figure 5b (Q1): Capacitance (Log Scale) 500 1000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 100 Capacitance (pF) 400 Capacitance (pF) 2.5 300 200 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 10 100 0 0 20 40 60 1 80 VDS – Drain-to-Source Voltage (V) 0 20 40 VDS – Drain-to-Source Voltage (V) 60 80 Figure 5d (Q2): Capacitance (Log Scale) Figure 5c (Q2): Capacitance (Linear Scale) 2500 Capacitance (pF) Capacitance (pF) 1000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 2000 1500 1000 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 100 10 500 0 0 20 40 60 80 VDS – Drain-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 10 20 40 60 80 VDS – Drain-to-Source Voltage (V) | 4 eGaN® FET DATASHEET EPC2105 15 0.6 0.4 10 0.2 5 0 0 20 40 QOSS – Output Charge (nC) 0.8 EOSS – COSS Stored Energy (μJ) QOSS – Output Charge (nC) 20 0.0 80 60 100 3.0 80 2.4 60 1.8 40 1.4 20 0.6 0 VDS – Drain-to-Source Voltage (V) 40 0.0 80 60 Figure 7b (Q2): Gate Charge Figure 7a (Q1): Gate Charge 5 ID = 20 A VDS = 40 V 4 VGS – Gate-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V) 20 VDS – Drain-to-Source Voltage (V) 5 3 2 1 0 0 0 0.5 1.0 1.5 2.0 QG – Gate Charge (nC) 2.5 3 2 1 0 3.0 ID = 20 A VDS = 30 V 4 Figure 8a (Q1): Reverse Drain-Source Characteristics 0 2 4 6 QG – Gate Charge (nC) 8 10 12 Figure 8b (Q2): Reverse Drain-Source Characteristics 300 25˚C 125˚C ISD – Source-to-Drain Current (A) ISD – Source-to-Drain Current (A) 60 VGSDS = 03 V 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 4.5 5.0 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 25˚C 125˚C VGSDS = 03 V 200 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD – Source-to-Drain Voltage (V) 4.0 4.5 5.0 | 5 EOSS – COSS Stored Energy (μJ) Figure 6b (Q2): Output Charge and COSS Stored Energy Figure 6a (Q1): Output Charge and COSS Stored Energy eGaN® FET DATASHEET EPC2105 Figure 9a (Q1): Normalized On-State Resistance vs. Temperature Figure 9b (Q2): Normalized On-State Resistance vs. Temperature 2.0 Normalized On-State Resistance RDS(on) Normalized On-State Resistance RDS(on) 2.0 1.8 ID = 20 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 0 25 50 75 100 TJ – Junction Temperature (°C) 125 1.8 1.4 1.2 1.0 0.8 150 1.4 1.4 1.3 1.3 Normalized Threshold Voltage Normalized Threshold Voltage 0 ID = 2.5 mA 1.1 1.0 0.9 0.8 50 75 100 TJ – Junction Temperature (°C) 125 150 1.2 ID = 10 mA 1.1 1.0 0.9 0.8 0.7 0.7 0.6 0 25 50 75 100 TJ – Junction Temperature (°C) 125 0.6 150 Figure 11a (Q1): Safe Operating Area 100 100 Limited by RDS(on) Pulse Width 1 ms 250 µs 100 µs 1 0.1 0.1 I D – Drain Current (A) 1000 10 1 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 Figure 11b (Q2): Safe Operating Area 1000 I D – Drain Current (A) 25 Figure 10b (Q2): Normalized Threshold Voltage vs. Temperature Figure 10a (Q1): Normalized Threshold Voltage vs. Temperature 1.2 ID = 20 A VGS = 5 V 1.6 10 100 VDS – Drain-Source Voltage (V) TJ = Max Rated, TC = +25°C, Single Pulse EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Limited by RDS(on) 10 ms Pulse100 Width 10 ms 1 ms 1 ms 250 µs 100 µs 1 0.1 0.1 1 10 100 VDS – Drain-Source Voltage (V) TJ = Max Rated, TC = +25°C, Single Pulse | 6 eGaN® FET DATASHEET (Q1 & Q2) Junction-to-Board ZθJB, Normalized Thermal Impedance Figure 12a Transient Thermal Response Curves EPC2105 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 PDM 0.02 t1 0.01 0.01 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB Single Pulse 0.001 10-5 10-4 10-3 10-2 10-1 1 101 tp, Rectangular Pulse Duration, seconds (Q1 & Q2) Junction-to-Case ZθJC, Normalized Thermal Impedance Figure 12b Transient Thermal Response Curves 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.01 PDM 0.02 0.01 0.001 10-6 t1 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds Figure 13 Typical Application Circuit eGaNIC Gate driver/ controller VB HO VS VCC GND VIN + LO VIN Gate 1 GR1 Gate 2 _ Q1 VSW Q2 VOUT + RLoad PGND _ EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 7 eGaN® FET DATASHEET EPC2105 TAPE AND REEL CONFIGURATION e 8 mm pitch, 12 mm wide tape on 7” reel d 7” inch reel g f Loaded Tape Feed Direction Gate solder bump is under this corner a b c Die orientation dot YYYY ZZZZ 2105 h DIM EPC2105 (Note 1) a b c (Note 2) d e f (Note 2) g h Dimension (mm) Target MIN MAX 12.00 11.90 12.30 1.75 1.65 1.85 5.50 5.45 5.55 4.00 3.90 4.10 8.00 7.90 8.10 2.00 1.95 2.05 1.50 1.50 1.60 1.50 1.50 1.75 Die is placed into pocket solder bump side down (face side down) Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2105 YYYY ZZZZ Die orientation dot Part Number EPC2105 Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 2105 YYYY ZZZZ Gate bumps are along this edge of the die EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 8 eGaN® FET DATASHEET EPC2105 DIE OUTLINE Solder Bump View A 10 15 20 25 30 35 40 45 50 55 60 65 70 75 4 9 14 19 24 29 34 39 44 49 54 59 64 69 74 3 8 13 18 23 28 33 38 43 48 53 58 63 68 73 2 7 12 17 22 27 32 37 42 47 52 57 62 67 72 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 e e Nominal MAX A B c d e f 6020 2270 400 450 210 187 6050 2300 400 450 225 208 6080 2330 400 450 240 240 Pad 2 is Gate1 (high side); Pad 4 is Gate2 (low side); Pad 3 is HS Gate Return; Pads 5, 12, 13, 14, 15, 22, 23, 24, 25, 32, 33, 34, 35, 42, 43, 44, 45, 52, 53, 54, 55, 62, 63, 64, 65, 72, 73, 74, 75 are Ground; f c MIN B d 5 DIM Side View (785) 160+/−16 (625) Pads 1, 11, 21, 31, 41, 51, 61, 71 are VIN ; Seating plane Pads 6, 7, 8, 9, 10, 16, 17, 18, 19, 20, 26, 27, 28, 29, 30, 36, 37, 38, 39, 40, 46, 47, 48, 49, 50, 56, 57, 58, 59, 60, 66, 67, 68, 69, 70 are Switch Node RECOMMENDED LAND PATTERN (measurements in µm) 6050 6 11 16 21 26 31 36 41 46 51 56 61 66 71 2 7 12 17 22 27 32 37 42 47 52 57 62 67 72 3 8 13 18 23 28 33 38 43 48 53 58 63 68 73 4 9 14 19 24 29 34 39 44 49 54 59 64 69 74 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 The land pattern is solder mask defined. Suggest SMD Pads at 200 +20/–10 µm. 190 µm minimum. 2300 450 1 400 RECOMMENDED STENCIL DRAWING (measurements in µm) 6050 Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. 2300 275 450 225 Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx 400 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Information subject to change without notice. Revised June, 2020 | 9