EPC2108

eGaN® FET DATASHEET EPC2108 EPC2108 – Enhancement-Mode GaN Power Transistor Half-Bridge with Integrated Synchronous Bootstrap VDS , 60 V RDS(on) , 240 mΩ ID , 1.7 A EFFICIENT POWER CONVERSION HAL Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings DEVICE PARAMETER VDS Q1 & Q2 ID VALUE Drain-to-Source Voltage (Continuous) 60 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 72 Continuous (TA = 25˚C, RθJA = 60°C/W) 1.7 Pulsed (25°C, TPULSE = 300 µs) 5.5 Gate-to-Source Voltage 6 Gate-to-Source Voltage –4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 VGS VDS ID Q3 Drain-to-Source Voltage (Continuous) 100 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120 Continuous (TA = 25°C, RθJA= 100°C/W) 0.5 Pulsed (25°C, TPULSE = 300 µs) 0.5 Gate-to-Source Voltage 6 Operating Temperature –40 to 150 TJ Storage Temperature –40 to 150 TSTG Storage Temperature –40 to 150 VGS UNIT EPC2108 eGaN® ICs are supplied only in passivated die form with solder bumps Die Size: 1.35 mm x 1.35 mm V A Applications • High Frequency DC-DC Conversion • Class-D Audio • Wireless Power (Highly Resonant and Inductive) V °C V Benefits • Ultra High Efficiency • Ultra Low RDS(on) • Ultra Low QG • Ultra Small Footprint A V °C DBTST Thermal Characteristics PARAMETER TYP RθJC Thermal Resistance, Junction-to-Case 6 RθJB Thermal Resistance, Junction-to-Board 33 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 81 6 UNIT Gupper °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details SBTST Positive 7 1 Q1 9 Q3 4 Out1 5 Out2 DGrev Q2 3 GBTST 2 Glower 8 Ground EPC2108 – Detailed Schematic EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1 eGaN® FET DATASHEET DEVICE PARAMETER BVDSS IDSS Q1 & Q2 Q3 IGSS VGS(TH) RDS(on) VSD BVDSS IDSS IGSS VF VGS(TH) RDS(on) VSD Q2 Q3 Static Characteristics (TJ= 25˚C unless otherwise stated) TEST CONDITIONS Drain-to-Source Voltage Drain-Source Leakage Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Threshold Voltage Drain-Source On Resistance Source-Drain Forward Voltage Drain-to-Source Voltage Drain-Source Leakage Gate-to-Source Forward Leakage Source-Gate Forward Voltage Gate Threshold Voltage Drain-Source On Resistance Source-Drain Forward Voltage VGS = 0 V, ID = 0.3 mA VDS = 48 V, VGS = 0 V VGS = 5 V VGS = -4 V VDS = VGS, ID = 0.2 mA VGS = 5 V, ID = 2.5 A IS = 0.5 A, VGS = 0 V VGS = 0 V, ID = 0.125 mA VDS = 80 V, VGS = 0 V VGS = 5 V IF = 0.2 mA, VDS = 0 V VDS = VGS, ID = 0.1 mA VGS = 5 V, ID = 0.05 A IS = 0.1 A, VGS = 0 V MIN CISS CRSS COSS COSS(ER) COSS(TR) Input Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance, Energy Related (Note 2) Effective Output Capacitance, Time Related (Note 3) RG QG QGS QGD QG(TH) QOSS QRR CISS CRSS COSS COSS(ER) COSS(TR) Total Gate Charge Gate to Source Charge Gate to Drain Charge Gate Charge at Threshold Output Charge Source-Drain Recovery Charge Input Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance, Energy Related (Note 2) Effective Output Capacitance, Time Related (Note 3) RG QG QGS QGD QG(TH) QOSS QRR CISS CRSS COSS COSS(ER) COSS(TR) Total Gate Charge Gate to Source Charge Gate to Drain Charge Gate Charge at Threshold Output Charge Source-Drain Recovery Charge Input Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance, Energy Related (Note 2) Effective Output Capacitance, Time Related (Note 3) RG QG QGS QGD QG(TH) QOSS QRR Total Gate Charge Gate to Source Charge Gate to Drain Charge Gate Charge at Threshold Output Charge Source-Drain Recovery Charge 0.8 0.8 VDS = 0 to 30 V, VGS = 0 V Gate Resistance VDS = 30 V, VGS = 5 V, ID = 2.5 A VDS = 50 V, ID = 2.5 A VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 0 V VDS = 0 to 30 V, VGS = 0 V Gate Resistance VDS = 30 V, VGS = 5 V, ID = 2.5 A VDS = 30 V, ID = 2.5 A VDS = 30 V, VGS = 0 V VDS = 50 V, VGS = 0 V VDS = 0 to 50 V, VGS = 0 V Gate Resistance VDS = 50 V, VGS = 5 V, ID = 0.05 A VDS = 50 V, VGS = 0 V MAX UNIT 0.05 0.1 0.05 1.6 150 2.6 0.25 1 0.25 2.5 240 0.02 0.1 0.1 1 2.7 2.5 3300 V mA mA mA V mΩ V V mA mA V V mΩ V 100 VDS = 30 V, VGS = 0 V VDS = 50 V, ID = 0.05 A TYP 60 Dynamic Characteristics (TJ= 25˚C unless otherwise stated) PARAMETER TEST CONDITIONS DEVICE Q1 EPC2108 1.7 2100 2.9 MIN TYP MAX 26 0.4 12 20 24 0.6 240 106 47 71 710 0 26 0.4 16 25 31 0.6 240 106 47 71 930 0 7 0.02 1.6 2.2 2.7 4.8 44 20 4 18 134 0 31 18 UNIT pF Ω 310 pC 1070 31 24 pF Ω 310 pC 1400 8.4 2.4 pF Ω 55 pC 200 Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(ER) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 2 eGaN® FET DATASHEET EPC2108 Figure 1b (Q3): Typical Output Characteristics at 25°C Figure 1a (Q1 & Q2): Typical Output Characteristics at 25°C 0.5 5 VGS = 5 V ID – Drain Current (A) ID – Drain Current (A) 0.4 4 VGS = 4 V 3 VGS = 3 V VGS = 2 V 2 1 0 VGS = 5 V VGS = 4 V 0.3 VGS = 3 V VGS = 2 V 0.2 0.1 0 0.5 1.0 1.5 2.0 2.5 VDS – Drain-to-Source Voltage (V) 00 3.0 Figure 2a (Q1 & Q2): Transfer Characteristics 0.5 1.0 1.5 2.0 2.5 VDS – Drain-to-Source Voltage (V) 3.0 Figure 2b (Q3): Transfer Characteristics 0.5 25˚C 125˚C 4 VDS = 3 V 3 2 VDS = 3 V 0.3 0.2 0.1 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 0 5.0 1.0 1.5 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 RDS(on) – Drain-to-Source Resistance (mΩ) 8000 ID = 1.0 A ID = 1.5 A ID = 2.0 A ID = 2.5 A 500 400 300 200 100 0 0.5 Figure 3b (Q3): RDS(on) vs. VGS for Various Drain Currents Figure 3a (Q1 & Q2): RDS(on) vs. VGS for Various Drain Currents 600 RDS(on) – Drain-to-Source Resistance (mΩ) 25˚C 125˚C 0.4 ID – Drain Current (A) ID – Drain Current (A) 5 3.0 3.5 4.0 4.5 5.0 ID = 0.05 A ID = 0.10 A ID = 0.15 A ID = 0.20 A 6000 4000 2000 0 VGS – Gate-to-Source Voltage (V) EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | 2.5 3.0 3.5 4.0 4.5 5.0 VGS – Gate-to-Source Voltage (V) | 3 eGaN® FET DATASHEET EPC2108 Figure 4a (Q1 & Q2): RDS(on) vs. VGS for Various Temperatures Figure 4b (Q3): RDS(on) vs. VGS for Various Temperatures 8000 500 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 600 25˚C 125˚C ID = 2.5 A 400 300 200 100 0 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 6000 ID = 0.05 A 4000 2000 0 5.0 Figure 5a (Q1): Capacitance (Linear Scale) 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 Figure 5b (Q1): Capacitance (Log Scale) 100 50 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD Capacitance (pF) 40 Capacitance (pF) 25˚C 125˚C 30 20 10 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1 10 0 0 10 20 30 40 50 0.1 60 VDS – Drain-to-Source Voltage (V) 10 20 30 40 VDS – Drain-to-Source Voltage (V) 50 60 Figure 5d (Q2): Capacitance (Log Scale) Figure 5c (Q2): Capacitance (Linear Scale) 100 60 50 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 40 Capacitance (pF) Capacitance (pF) 0 30 20 10 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1 10 0 0 10 20 30 40 50 60 0.1 0 VDS – Drain-to-Source Voltage (V) EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | 10 20 30 40 50 60 VDS – Drain-to-Source Voltage (V) | 4 eGaN® FET DATASHEET EPC2108 Figure 5e (Q3): Capacitance (Linear Scale) Figure 5f (Q3): Capacitance (Log Scale) 100 8 7 10 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 5 Capacitance (pF) Capacitance (pF) 6 4 3 2 1 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 0.1 0.01 1 0 20 40 60 80 0.001 100 0 20 VDS – Drain-to-Source Voltage (V) Figure 6a 6a:(Q1): Output Output Charge Charge and Cand COSS Stored Energy Energy OSS Stored 25 20 0.6 15 0.4 10 0.2 5 0.0 0 10 20 30 40 50 60 QOSS – Output Charge (nC) 0.8 1.6 EOSS – COSS Stored Energy (μJ) QOSS – Output Charge (nC) 1.0 35 1.2 30 1.0 25 0.8 20 0.6 15 0.4 10 0.2 5 0 6 0.10 4 0.05 2 60 10 20 30 40 50 60 0 80 EOSS – COSS Stored Energy (μJ) QOSS – Output Charge (nC) 0.15 40 40 10 8 20 100 VDS – Drain-to-Source Voltage (V) Figure 6c 6a:(Q3): Output Output Charge Charge and and COSS Stored COSS Stored Energy Energy 0 80 1.4 0 0 0.20 0.00 60 Figure 6b 6a:(Q2): Output Output Charge Charge and Cand COSS Stored Energy Energy OSS Stored VDS – Drain-to-Source Voltage (V) 0.25 40 VDS – Drain-to-Source Voltage (V) EOSS – COSS Stored Energy (μJ) 0 0 100 VDS – Drain-to-Source Voltage (V) EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 5 eGaN® FET DATASHEET EPC2108 Figure 7a (Q1 & Q2): Gate Charge Figure 7b (Q3): Gate Charge 5 ID = 2.5 A VDS = 30 V 4 VGS – Gate-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V) 5 3 2 1 0 0 50 100 150 200 QG – Gate Charge (pC) 3 2 1 0 250 ID = 0.05 A VDS = 50 V 4 Figure 8a (Q1 & Q2): Reverse Drain-Source Characteristics 0 10 20 30 40 QG – Gate Charge (pC) 50 Figure 8b (Q3): Reverse Drain-Source Characteristics 0.5 25˚C 125˚C 4 ISD – Source-to-Drain Current (A) ISD – Source-to-Drain Current (A) 5 VGSDS = 03 V 3 2 1 Normalized On-State Resistance RDS(on) 2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VSD – Source-to-Drain Voltage (V) 4.5 Figure 9a (Q1 & Q2): Normalized On-State Resistance vs. Temperature 1.6 1.4 1.2 1.0 0.8 0.3 0.2 0.1 2.2 ID = 2.5 A VGS = 5 V 1.8 VGSDS = 03 V 0 5.0 Normalized On-State Resistance RDS(on) 0 25˚C 125˚C 0.4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VSD – Source-to-Drain Voltage (V) 4.5 5.0 Figure 9b (Q3): Normalized On-State Resistance vs. Temperature 2.0 ID = 0.05 A VGS = 5 V 1.8 1.6 1.4 1.2 1.0 0.8 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 0.6 EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | 0 25 50 75 100 125 150 TJ – Junction Temperature (°C) | 6 eGaN® FET DATASHEET EPC2108 Figure 10b (Q3): Normalized Threshold Voltage vs. Temperature 1.40 1.40 1.30 1.30 1.20 Normalized Threshold Voltage Normalized Threshold Voltage Figure 10a (Q1 & Q2): Normalized Threshold Voltage vs. Temperature ID = 0.2 mA 1.10 1.00 0.90 0.80 0.70 1.10 1.00 0.90 0.80 0.70 0 25 50 75 100 TJ – Junction Temperature (°C) Figure 11a Transient Thermal Response Curves 125 0.60 150 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 (Q1/Q2/Q3) Junction-to-Board ZθJB, Normalized Thermal Impedance 0.60 ID = 0.1 mA 1.20 1 Duty Cycle: 0.5 0.1 0.01 0.1 0.05 0.02 0.01 PDM t1 Single Pulse 0.001 10-5 t2 Notes: Single Pulse Duty Factor: D= t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-4 10-3 10-2 10-1 1 101 tp, Rectangular Pulse Duration, seconds (Q1/Q2/Q3) Junction-to-Case ZθJC, Normalized Thermal Impedance Figure 11b Transient Thermal Response Curves 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 PDM 0.02 0.01 t1 0.01 Single Pulse 0.001 10-6 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC 10-5 10-4 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 7 eGaN® FET DATASHEET EPC2108 Figure 13 (Q3): Gate-Source Characteristics Figure 12 (Q1 & Q2): Safe Operating Area 0.08 10 1 Pulse Width 100 ms 10 ms 100 µs 1 ms 50 µs 100 µs 25 µs 0.1 0.1 1 25˚C 125˚C 0.04 Limited by RDS(on) IG – Gate Current (mA) I D – Drain Current (A) 0.06 0.02 0.00 -0.5 -1.0 10 100 VDS – Drain-Source Voltage (V) TJ = Max Rated, TC = +25°C, Single Pulse -1.5 -2.0 -2 -1 0 1 2 3 VGS – Gate-to-Source Voltage (V) 4 5 6 Figure 14: Typical Application Circuit Q3 Q1 Level Shift 5V Output C Bus Q2 Gate Driver EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 8 eGaN® FET DATASHEET EPC2108 TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7”reel d e f Loaded Tape Feed Direction g 7” reel b 2108 YYYY ZZZZ a c 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Pin 1 is under this corner Die is placed into pocket solder bump side down (face side down) EPC2108 (note 1) Dimension (mm) target min max a b c (see note) d e f (see note) g Die orientation dot Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS Die orientation dot Pin 1 is under this corner 2108 YYYY ZZZZ Part Number EPC2108 EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 2108 YYYY Lot_Date Code Marking Line 3 ZZZZ | 9 eGaN® FET DATASHEET EPC2108 A DIE OUTLINE Solder Bump View Micrometers 9 5 8 c B 2 1 4 7 c (625) c d d Pad 1 is Gate1 (Q1) Pad 2 is Gate2 (Q2) Pad 3 is Gate 3 (Q3) Pad 7 is Drain1 (Q1) Pad 5 is Drain2 (Q2) Pad 6 is Drain3 (Q3) Pad 4 is Source1 (Q1) Pad 8 is Source2 (Q2) Pad 9 is Source3 (Q3) Seating Plane RECOMMENDED LAND PATTERN Nominal MAX A B c d e 1320 1320 450 210 187 1350 1350 450 225 208 1380 1380 450 240 229 165 +/- 17 Side View MIN 815 Max 6 c 3 DIM 1350 The land pattern is solder mask defined Solder mask is 10 μm smaller per side than bump 200 +20 / - 10 (*) (measurements in µm) X9 4 7 2 5 8 3 6 9 225 450 225 450 1350 450 1 450 * minimum 190 1350 RECOMMENDED STENCIL DRAWING Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. 250 225 450 450 Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 225 450 1350 450 R6 0 (measurements in µm) Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | Information subject to change without notice. Revised August, 2019 | 10