EPC2110

eGaN® FET DATASHEET EPC2110 EPC2110 – Dual Common-Source Enhancement-Mode GaN Power Transistor VDS , 120 V RDS(on) , 110 mΩ ID , 3.4 A EFFICIENT POWER CONVERSION HAL Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings of Q1 & Q2 VDS ID PARAMETER VALUE UNIT Drain-to-Source Voltage (Continuous) 120 V Continuous (TA = 25°C, RθJA = 52°C/W) 3.4 Pulsed (25°C, TPULSE = 300 µs) 20 Gate-to-Source Voltage 6 Gate-to-Source Voltage –4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 VGS EPC2110 eGaN® FETs are supplied only in passivated die form with solder bumps Die Size: 1.35 mm x 1.35 mm A V Applications • Ultra High Frequency DC-DC Conversion • Wireless Power Transfer • Synchronous Rectification °C Benefits • Ultra High Efficiency • Ultra Low RDS(on) • Ultra Low QG • Ultra Small Footprint Thermal Characteristics of Q1 & Q2 PARAMETER TYP RθJC Thermal Resistance, Junction-to-Case 3 RθJB Thermal Resistance, Junction-to-Board 25 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 81 UNIT °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details PARAMETER BVDSS IDSS IGSS www.epc-co.com/epc/Products/eGaNFETsandICs/EPC2110.aspx Static Characteristics of Q1 & Q2 (TJ= 25˚C unless otherwise stated) TEST CONDITIONS MIN TYP MAX VGS = 0 V, ID = 0.3 mA Drain-Source Leakage VDS = 96 V, VGS = 0 V 0.01 0.25 mA VGS = 5 V 0.05 1 mA 0.01 0.25 mA 1.4 2.5 V VGS = 5 V, ID = 4 A 80 110 mΩ IS = 0.5 A, VGS = 0 V 1.9 Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage VGS(TH) Gate Threshold Voltage RDS(on) Drain-Source On Resistance VSD Source-Drain Forward Voltage EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 120 UNIT Drain-to-Source Voltage VGS = -4 V VDS = VGS, ID = 0.7 mA 0.8 V V | 1 eGaN® FET DATASHEET EPC2110 3 2 9 8 D1 D2 Q1 1 Q2 G1 G2 7 S 4 5 6 EPC2110 – Detailed Schematic Note: The EPC2110 can be connected in parallel or used as independent FETs with common source. Dynamic Characteristics of Q1 & Q2 (TJ= 25˚C unless otherwise stated) PARAMETER TEST CONDITIONS CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) RG Gate Resistance QG Total Gate Charge QGS Gate to Source Charge QGD Gate to Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge VDS = 60 V, VGS = 0 V MIN TYP MAX 85 100 1 45 VDS = 0 to 60 V, VGS = 0 V UNIT 70 pF 54 67 0.6 VDS = 60 V, VGS = 5 V, ID = 4 A 0.8 VDS = 60 V, ID = 4 A 0.18 Ω 1.1 0.25 nC 0.16 VDS = 60 V, VGS = 0 V 4 6 0 Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 2 eGaN® FET DATASHEET EPC2110 Figure 2 (Q1 & Q2): Transfer Characteristics 20 20 15 15 ID – Drain Current (A) ID – Drain Current (A) Figure 1 (Q1 & Q2): Typical Output Characteristics at 25°C 10 VGS = 5 V VGS = 4 V VGS = 3 V 5 25˚C 125˚C VDS = 3 V 10 5 VGS = 2 V 0 0 0.5 1.0 1.5 2.0 VDS – Drain-to-Source Voltage (V) 2.5 0 3.0 0.5 Figure 3 (Q1 & Q2): RDS(on) vs. VGS for Various Drain Currents 2.0 2.5 3.0 3.5 VGS – Gate-to-Source Voltage (V) 4.0 4.5 5.0 300 RDS(on) – Drain-to-Source Resistance (mΩ) RDS(on) – Drain-to-Source Resistance (mΩ) 1.5 Figure 4 (Q1 & Q2): RDS(on) vs. VGS for Various Temperatures 300 ID = 1 A ID = 2A ID = 4 A ID = 8 A 200 100 0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 25˚C 125˚C ID = 4 A 200 100 0 5.0 VGS – Gate-to-Source Voltage (V) 2.0 2.5 3.0 3.5 4.0 VGS – Gate-to-Source Voltage (V) 4.5 5.0 Figure 5b (Q1 & Q2): Capacitance (Log Scale) Figure 5a (Q1 & Q2): Capacitance (Linear Scale) 150 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 100 Capacitance (pF) Capacitance (pF) 100 50 0 10 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 1 0 20 40 60 80 100 120 VDS – Drain-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 0.1 0 20 40 60 80 100 120 VDS – Drain-to-Source Voltage (V) | 3 eGaN® FET DATASHEET Figure 7 (Q1 & Q2): Gate Charge Figure 66a:(Q1 Output & Q2):Charge Outputand Charge COSS Stored and COSSEnergy Stored Energy 0.35 QOSS – Output Charge (nC) 5 0.25 4 0.20 3 0.15 2 0.10 1 0.05 0 20 40 60 80 VGS – Gate-to-Source Voltage (V) 0.30 6 0 5 EOSS – COSS Stored Energy (μJ) 7 EPC2110 0.00 120 100 ID = 4 A VDS = 60 V 4 3 2 1 0 VDS – Drain-to-Source Voltage (V) 0 Figure 8: Reverse Drain-Source Characteristics 2.0 Normalized On-State Resistance RDS(on) ISD – Source-to-Drain Current (A) 20 25˚C 125˚C 15 VGSDS = 03 V 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VSD – Source-to-Drain Voltage (V) 4.5 0.2 0.6 0.8 1 Figure 9 (Q1 & Q2): Normalized On-State Resistance vs. Temperature 1.8 ID = 4 A VGS = 5 V 1.6 1.4 1.2 1.0 0.8 5.0 0.4 QG – Gate Charge (pC) 0 25 50 75 100 TJ – Junction Temperature (°C) 125 150 Figure 10 (Q1 & Q2): Normalized Threshold Voltage vs. Temperature 1.40 Normalized Threshold Voltage 1.30 1.20 ID = 0.7 mA 1.10 1.00 0.90 0.80 0.70 0.60 0 25 50 75 100 TJ – Junction Temperature (°C) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | 125 150 | 4 eGaN® FET DATASHEET EPC2110 ZθJB, Normalized Thermal Impedance Figure 11a (Q1 & Q2): Transient Thermal Response Curves (Junction-to-Board) 1 Duty Cycle: 0.5 0.1 0.1 0.05 PDM t1 0.02 0.01 0.01 t2 Notes: Single Duty Factor: D Pulse = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB Single Pulse 0.001 10-5 10-4 10-3 10-2 10-1 1 101 tp, Rectangular Pulse Duration, seconds ZθJC, Normalized Thermal Impedance Figure 11b (Q1 & Q2): Transient Thermal Response Curves (Junction-to-Case) 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 PDM t1 0.02 0.01 0.01 Notes: Single Duty Factor: D =Pulse t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.001 10-6 t2 10-4 10-5 10-3 10-2 10-1 1 tp, Rectangular Pulse Duration, seconds Figure 12 (Q1 & Q2): Safe Operating Area I D – Drain Current (A) 100 10 Limited by RDS(on) 1 0.1 0.1 Pulse Width 1100 ms µs 100 µs 10 µs 1 10 100 1000 VDS – Drain-Source Voltage (V) TJ = Max rated, TC = +25°C, Single pulse EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 5 eGaN® FET DATASHEET EPC2110 TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7”reel d e f Loaded Tape Feed Direction g 7” reel b 2110 YYYY ZZZZ a c 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 P1 is under this corner Die is placed into pocket solder bump side down (face side down) EPC2110 (note 1) Dimension (mm) target min a b c (see note) d e f (see note) g Die orientation dot max 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS Die orientation dot Pin 1 is under this corner 2110 YYYY ZZZZ EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Part Number EPC2110 Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 2110 YYYY Lot_Date Code Marking Line 3 ZZZZ | 6 eGaN® FET DATASHEET EPC2110 A DIE OUTLINE Solder Bump View e 6 9 2 5 8 1 4 7 c B c 3 Pad 1 is Gate 1; Pad 7 is Gate 2; Pads 2, 3 are Drain 1; Pads 8, 9 are Drain 2; Pads 4, 6 are Source; Pad 5 is Substrate* c MAX A B c d e 1320 1320 450 210 187 1350 1350 450 225 208 1380 1380 450 240 229 165 +/- 17 Side View Seating Plane RECOMMENDED LAND PATTERN Nominal 815 Max (625) c MIN d d *Substrate pin should be connected to Source Micrometers DIM 1350 The land pattern is solder mask defined Solder mask is 10 μm smaller per side than bump 200 +20 / - 10 (*) (measurements in µm) X9 4 7 2 5 8 3 6 9 225 450 225 450 1350 450 1 450 * minimum 190 RECOMMENDED STENCIL DRAWING 1350 Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. 250 225 450 450 Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx 225 450 1350 450 R6 0 (measurements in µm) Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | Information subject to change without notice. Revised May, 2020 | 7