EPC2152ENGRT

EPC2152x – 70 V, 12.5 A ePower™ Stage PRELIMINARY Key Parameters Rated Output Current (1 MHz) (1) Operating PWM Frequency Range (2) Operating Input Voltage Range Bias Supply Voltage Typical Application 12.5 A 3 MHz 60 V 12 V Synchronous Buck Converter Output Current and PWM Frequency Ratings are functions of Operating Conditions. See Notes 1 & 2. Features • • • • • • • • • • • Separate and independent high side and low side control inputs Input signal compatible with 3.3 V or 5 V CMOS logic levels 20 ns minimum input pulse width 20 ns delay time input to output 1 ns switching time at output node Robust level shifter operating from negative transient conditions False trigger immunity greater than 100 V/ns at output node Synchronous charging for high side bootstrap supply Regulated gate drive buffer output to drive output FETs at safe operating level Undervoltage lockout for high side and low side power supplies LGA Chip Scale Package RBOOT is used to adjust di/dt of HS FET turn-on transition. SW node peak over-voltage spike should be kept below Abs Max Ratings of VSW(continuous) and VSW(pulse). Performance Curves Buck Converter Topology, VIN = 48 V, VOUT = 12 V, Deadtime = 10ns, L = 2.2 µH, DCR = 3 mΩ, RBOOT = 2.2 Ω, EPC90120 PCB, Airflow = 800 LFM. Die Photo Applications • • • • Buck and Boost Converters Half-Bridge, Full Bridge or LLC Isolated Converters Class D Switching Audio Amplifier Single Phase and Three Phase Motor Drive Inverter* *Optimized device for motor drive is EPC21521 Subject to Change without Notice www.epc-co.com 3.85 mm x 2.59 mm x 0.63 mm COPYRIGHT 2020 Rev 1.3 Page 1 EPC2152x – 70 V, 12.5 A ePower™ Stage PRELIMINARY Functional Block Diagram General Description The EPC2152 is a single chip driver plus eGaN® FET half-bridge power stage product family. Integration is implemented using EPC’s proprietary GaN IC technology. Input logic interface, level shifting, bootstrap charging and gate drive buffer circuits along with eGaN output FETs configured as a halfbridge are integrated within a monolithic chip. This results in a chip-scale LGA form factor device that measures only 3.85 mm x 2.59 mm x 0.63 mm. The two eGaN output FETs in half-bridge topology are designed to have same RDS(on). Integration of eGaN FETs with on-chip gate drive buffers practically eliminate effects of common source inductance and gate drive loop inductance. Monolithic integration combined with a pinout that uses low inductance LGA solder bumps, result in a high-current output node that can switch Subject to Change without Notice www.epc-co.com within 1 ns under full load with PWM frequency up to 3 MHz. The charging path for the floating bootstrap supply is integrated using GaN FET driven by a synchronous circuit. This eliminates the need for an external bootstrap diode with associated reverse recovery charge that may result in significant power loss at high frequency switching. This synchronous bootstrap charging circuit also minimizes the voltage drop in the bootstrap charging path to ensure adequate voltage for the bootstrap power supply. Robust level shifters from low side to high side channels are designed to operate correctly even at large negative clamped voltage and to avoid false trigger from fast dv/dt transients exceeding 100 V/ns. Internal regulation of the gate drive voltage based on feedback from the driven output FETs ensures a safe gate voltage level while still turning on the output FETs to a low RDS(on) state. Additional protection is provided by separate high side and low side undervoltage lockout (UVLO) circuits with lockout levels referenced to the gate drive buffer circuit to avoid operating the output FETs in a high RDS(on) state. The EPC2152 device is capable of interfacing to digital controllers that use standard 3.3 V or 5V CMOS logic levels. Separate and independent high side and low side logic control inputs allow external controllers to set deadtimes for optimal operating efficiency. COPYRIGHT 2020 Rev 1.3 Page 2 EPC2152x – 70 V, 12.5 A ePower™ Stage PRELIMINARY Pinout Description, Pad View Pin# Pin Name Pin Type Description 1 VBOOT S Floating bootstrap power supply referenced to SW, connect an external bypass capacitor from VBOOT to SW 2 VDD S Operating power supply referenced to GND, connect an external bypass capacitor from VDD to GND 3 HSin S High side PWM logic input, level referenced to GND 4 LSin S Low side PWM logic input, level referenced to GND 5, 9 VIN P Input bus voltage. Connected to high side eGaN FET drain terminal. 6, 7, 10, 11 SW P Output switching node. Connected to output of eGaN halfbridge power stage. The floating bootstrap power supply, VBOOT, is also referenced to SW. 8, 12 GND P Power ground. Connected to low side eGaN FET source terminal. The operating power supply, VDD, is also referenced to GND. Pin Type : P=Power, S=Signal and Supply Subject to Change without Notice www.epc-co.com COPYRIGHT 2020 Rev 1.3 Page 3 EPC2152x – 70 V, 12.5 A ePower™ Stage PRELIMINARY Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur and device reliability may be affected. All voltage parameters are absolute voltages referenced to GND unless indicated otherwise. Symbol VIN VSW(continuous) VSW(pulse50ns) VSW(pulse2ns) VDD VBOOT - VSW HSin LSin TJ TSTG Parameter Input Voltage (VIN to GND) Output Switching Node (SW to GND), Continuous Output Switching Node (SW to GND), PW