EPC21601ENGRT

eGaN® IC DATASHEET EPC21601 EPC21601 – eToF Laser Driver IC TM D VDD 40 V 15 A Peak EFFICIENT POWER CONVERSION IN VSS HAL The EPC21601 is a laser driver that is controlled using 3.3 V logic at high frequencies of up to 100 MHz to modulate laser driving currents of up to 15 Amps. Full driver integration is achieved using EPC’s proprietary GaN IC technology. Wafer-level chip-scale packaging is used resulting in a BGA package that measures only 1.5 x 1 mm. The BGA package has low inductance and lays out very well with the laser system. The EPC21601 uses a 5 V logic supply and is capable of interfacing to digital controllers. It can switch at frequencies exceeding 100 MHz. Figure 1: Typical Connection Diagrams VIN LStray VDD VDD D IN VLaser PWM VOUT D VSS Laser Driver Boost Converter Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS unless indicated otherwise. Symbol VD VDD IN ID TJ TSTG Definition MIN Drain Voltage Logic Supply Voltage Logic Input Average Drain Current Operating Junction Temperature Storage Temperature -0.3 -0.3 -40 -40 MAX 40 5.5 5 3.4 125 150 UNIT V A °C ESD Ratings Symbol Definition HBW Human-body model CDM Charged-device model6 MIN +/-250 N/A Definition MIN RθJC Thermal Resistance, Junction-to-Case 5.7 RθJB Thermal Resistance, Junction-to-Board 23 RRθJA_JEDEC Thermal Resistance, Junction-to-Ambient (using JEDEC 51-2 PCB) 130 RθJA _EVB Thermal Resistance, Junction-to-Ambient (using EPC9154 EVB) 120 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | Applications • Time of flight measurement – Gesture recognition – Gaming – Driver monitoring – Robotic vision – Industrial safety • ToF module using VCEL laser for camera modules, laptops and smart phones • Boost control switch • Flyback control switch • Forward control switch • Class-E Amplifier UNIT V Thermal Characteristics Symbol EPC21601 eGaN® FETs are supplied in passivated die form with solder bumps. Features • VLaser operating range up to 30 V • 15 Amp peak current • Switching frequency greater than 100 MHz • Typical voltage switching time 750 ps • 5 V nominal logic power supply • 3.3 V logic compatible input control • 1.5 ns minimum output pulse width • 3.5 ns delay time from input to output IN VSS Die size: 1.5 x 1 mm Scan QR code or click link below for more information including reliability reports, device models, demo boards! UNIT °C/W https://l.ead.me/EPC21601 | 1 eGaN® IC DATASHEET EPC21601 Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to VSS unless indicated otherwise. Symbol Definition MIN VLaser VDD Driver Voltage5 5 Laser Logic Supply Voltage5 TYP MAX 30 5 Truth Table UNIT IN Laser V 0 1 Off On Electrical Characteristics All ratings at TJ = 25 ˚C. VLaser = 20 V, ID = 10 A, VIL = 0 V, VIH = 3.3 V, VDD = 5 V, unless indicated otherwise. Symbol Definition MIN Operating Power Supply, VDD IDD (Off) VDD Quiescent current with laser driver off IDD (30 MHz) Operating current off VDD at 30 MHz Input Pins VIH High-level input voltage VIL Low-level input voltage VIHyst Hysteresis between rising and falling threshold RIN Input pulldown resistance Power Stage RDS(on)1 Drain to Source Resistance ID(peak) 1 Peak Laser Drive Current Capability, f = 50 MHz COSS 1 VDS = 20 V, VIN = 0 V 1 QOSS VDS = 20 V, VIN = 0 V EOSS 1 VDS = 20 V, VIN = 0 V COSS(ER) 1,2 VDS = 0 to 20 V, VIN = 0 V COSS(TR) 1,3 VDS = 0 to 20 V, VIN = 0 V Dynamic Characteristics tD(on) 1 Turn on delay time 1 tF Drain fall time tD(off) 1 Turn off delay time 1,4 tR Drain rise time tdPW 1 Pulse width distortion tin(min(on)) 1 Minimum input pulse width tD(min(on)) 1 Minimum drain pulse width tOn(Max) 1 Maximum on time fMax 1 Maximum frequency, 0 °C to 100 °C TYP MAX 11 50 20 70 1.9 0.5 53 40 Pin VDD mA V IN D VSS Description Input Voltage Supply (Decouple to VSS with small, low inductance capacitor) Logic input Power Drain Power and Signal Return mΩ A pF nC nJ 15 49 1.5 13 63 73 -2 UNIT mV kΩ 1.25 3.5 0.75 3.2 0.32 -0.24 2.5 1.5 500 100 Pinout Description pF 6.75 1.5 5.5 1.6 ns MHz Notes: 1. Guaranteed by design, but not tested 2. COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS 3. COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS 4. Drain rise time is determined by ZVS charging of the output capacitance 5. See Power Sequencing section in Applications Information for considerations on laser drive voltage 6. Paragraph 2.7 of AEC Q100-011 Rev. D, Jan. 29, 2019 states that CDM specification is not necessary on such a small device. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 2 eGaN® IC DATASHEET EPC21601 Performance Curves Figure 3: Typical Quiescent Current vs. Temperature 100 16 80 14 Current (mA) 60 Temperature (°C) -40 25 100 125 40 20 0 0 20 40 60 12 10 8 80 0 100 50 Frequency (MHz) Figure 4: Turn On Propagation Delay vs. Temperature 5.00 4.75 4.75 VDD = 5 V 4.25 4.25 4.00 4.00 3.75 3.50 3.75 3.50 3.25 3.25 3.00 3.00 2.75 2.75 2.5 2.50 2.25 VDD = 5 V 4.50 Delay (ns) Delay (ns) Figure 5: Turn Off Propagation Delay vs. Temperature 5.00 4.50 0 50 2.25 100 0 50 Temperature (°C) 100 Figure 6: Typical COSS 2.5 QOSS – Output charge (nC) Capacitance (pF) 60 40 20 0 5 10 15 20 25 100 Temperature (°C) 80 0 100 Temperature (°C) 30 35 40 VDS – Drain-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | Figure 7: Typical Output Charge and COSS Stored Energy 40 2.0 32 1.5 24 1.0 16 0.5 8 0 0 5 10 15 20 25 30 35 EOSS — COSS Stored Energy (nJ) Current (mA) Figure 2: Typical Quiescent Current vs. Frequency 0 40 VDS – Drain-to-Source Voltage (V) | 3 eGaN® IC DATASHEET EPC21601 Figure 8: Transient Thermal Impedance Junction-to-Board ZθJB, Normalized Thermal Impedance 1 0.1 Duty Cycle: 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 Single Pulse 0.001 10-5 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJB x RθJB + TB 10-4 10-3 10-2 10-1 1 10+1 t1, Rectangular Pulse Duration, seconds ZθJC, Normalized Thermal Impedance Junction-to-Case 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM Single Pulse t1 0.01 0.001 10-6 t2 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZθJC x RθJC + TC 10-5 10-4 10-3 10-2 10-1 1 t1, Rectangular Pulse Duration, seconds Application Information Safety Warning This device is capable of driving laser diodes to generate high power optical pulses. Such pulses are capable of causing PERMANENT VISION DAMAGE AND BLINDNESS as well as additional injury or property damage. Laser diodes may emit infrared (IR) light that is invisible to the user, but which can still cause PERMANENT VISION DAMAGE AND BLINDNESS as well as additional injury or property damage. User is fully responsible for following proper laser safety procedures to prevent injury or damage. Power Sequencing IN must be held low during power up sequence. For power up, VDD must be applied before applying voltage to the drain to prevent possible unwanted turn on of the output. For power down, the order must be reversed. Power Up IN VDD Drain 1 Low 0V 0V 2 Low 5V 0V 3 Low 5V VLaser Drive 4 Active 5V VLaser Drive Power Down IN VDD Drain 1 Low 5V VLaser Drive 2 Low 5V 0V 3 Low 0V 0V EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 4 eGaN® IC DATASHEET Application Information (continued) EPC21601 Figure 9: Power and Gate Drive Turn On Loops LStray Layout and decoupling Minimizing inductance in both power and gate drive loops is critical. The power loop is primary, and gate drive loop secondary. Short, wide traces are required, and returning in the second layer, using a thin dielectric will cancel much of the inductance. Using multiple ceramic capacitors in parallel will reduce stray inductance and impedance in the power loop. Use high quality NPO or COG capacitors for both power and gate drive. This will increase effective capacitance as capacitors with lower quality materials will lose much more capacitance with voltage. Recommended layout is shown below. Component recommendations for power and gate drive decoupling capacitors are shown in the EPC9154 demonstration board quick start guide. Turn off current is limited by the energy of the power loop stray inductance transferring to the COSS of the power FET of the laser driver. EOSS vs. VDS curve is in the datasheet. LStray VDD D IN VLaser VSS Gate drive Power loop Figure 10: Recommended Layout Start up VDD should be applied before the laser voltage. For applications where the laser voltage is below 10 V and at elevated temperatures, it may take a few pulses before the pulse width stabilizes. Output Capacitance Output capacitance (COSS) is the capacitance between drain and ground. Output charge (QOSS) is the integral of output capacitance over voltage. Just like discrete power FETs, output capacitance is charged and discharged with each cycle. This takes time and dissipates power. Please refer to FET application notes to determine impact. Cathode to drain connection on second conductor layer Figure 11: Parameter Measurement Test Circuits 2Ω 5V VDD 20 V D IN VSS Figure 12: Parameter Measurement Definitions IN 90% 10% 90% VD 10% tD(off) tD(on) tF EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | tR | 5 eGaN® IC DATASHEET EPC21601 TAPE AND REEL CONFIGURATION • 4 mm pitch, 8 mm wide tape on 7” reel • Standard reel packages 2,500 units e f 7” inch reel Loaded Tape Feed Direction g d Die orientation dot b c Die is placed into pocket solder bump side down (face side down) h DIM Dimension (mm) EPC21601 (Note 1) Target MIN MAX 8.00 7.90 8.30 a 1.75 1.65 1.85 b 3.50 3.45 3.55 c (Note 2) 4.00 3.90 4.10 d 4.00 3.90 4.10 e 2.00 1.95 2.05 f (Note 2) g 1.50 1.50 1.60 0.50 0.45 0.55 h Pin 1 is under this corner AAB YYY a Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS AAB YYY Die orientation dot Part Number Pin 1 is under this corner Laser Markings Lot_Date Code Marking Line 1 Lot_Date Code Marking Line 2 AAB YYY EPC21601 A DIE OUTLINE Solder Bump View DIM e 5 6 A B c d e k m e 4 B e c 1 2 3 k 518 ±25 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | MAX 1450 950 500 500 264 225 225 1480 980 238 290 200 ±20 Seating plane Nominal Pad 1 is IN; Pads 2 & 3 are Drain; Pad 4 is VDD; Pads 5 & 6 are VSS d Side View MIN 1420 920 718 m MICROMETERS | 6 eGaN® IC DATASHEET EPC21601 RECOMMENDED LAND PATTERN A (units in µm) e 2 3 e 1 B e c 4 5 6 d RECOMMENDED STENCIL DRAWING A (measurements in µm) e 1 g 2 3 B f c 4 5 6 k m MICROMETERS A B c d e k m 1450 950 500 500 230 225 225 Pad 1 is IN; Pads 2 & 3 are Drain; Pad 4 is VDD; Pads 5 & 6 are VSS k m DIM d DIM MICROMETERS A B c d f g k m 1450 950 500 500 300 250 225 225 Recommended stencil should be 4mil (100 µm) thick, must be laser cut, opening per drawing. The corner has a radius of R60 Intended for use with SAC305 Type 4 solder, reference 88.5% metals content. Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | Information subject to change without notice. Revised December, 2022 | 7