eGaN® FET DATASHEET
EPC2203
EPC2203 – Automotive 80 V (D-S)
Enhancement Mode Power Transistor
VDS , 80 V
RDS(on) , 80 mΩ
ID , 1.7 A
AEC-Q101
D
EFFICIENT POWER CONVERSION
G
HAL
S
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
Maximum Ratings
PARAMETER
VDS
ID
VALUE
UNIT
Drain-to-Source Voltage (Continuous)
80
V
Continuous (TA = 25°C, RθJA = 314°C/W)
1.7
Pulsed (25°C, TPULSE = 300 µs)
17
A
Gate-to-Source Voltage
5.75
Gate-to-Source Voltage
-4
TJ
Operating Temperature
–40 to 150
TSTG
Storage Temperature
–40 to 150
VGS
V
°C
Thermal Characteristics
PARAMETER
TYP
RθJC
Thermal Resistance, Junction-to-Case
6.5
RθJB
Thermal Resistance, Junction-to-Board
65
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
100
EPC2203 eGaN® FETs are supplied only in
passivated die form with solder bumps.
Die Size: 0.9 mm x 0.9 mm
Applications
• Lidar/Pulsed Power Applications
• High Power Density DC-DC Converters
• Wireless Power
• Class-D Audio
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
UNIT
°C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
80
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 300 μA
IDSS
Drain-Source Leakage
IGSS
TYP
MAX
UNIT
V
VDS = 64 V, VGS = 0 V
5
250
μA
Gate-to-Source Forward Leakage
VGS = 5 V
0.01
0.9
mA
Gate-to-Source Reverse Leakage
VGS = -4 V
2
250
μA
VGS(TH)
Gate Threshold Voltage
RDS(on)
Drain-Source On Resistance
VSD
Source-Drain Forward Voltage
VDS = VGS, ID = 0.6 mA
1.5
2.5
V
VGS = 5 V, ID = 1 A
0.8
53
80
mΩ
IS = 0.35 A, VGS = 0 V
2.2
V
All measurements were done with substrate connected to source.
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| 1
eGaN® FET DATASHEET
EPC2203
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
CISS
Input Capacitance
TEST CONDITIONS
MIN
VDS = 50 V, VGS = 0 V
CRSS
Reverse Transfer Capacitance
COSS
Output Capacitance
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
RG
Gate Resistance
QG
Total Gate Charge
QGS
Gate-to-Source Charge
TYP
MAX
73
88
UNIT
0.5
47
pF
71
57
VDS = 0 to 50 V, VGS = 0 V
72
0.6
VDS = 50 V, VGS = 5 V, ID = 1 A
Ω
670
830
220
VDS = 50 V, ID = 1 A
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
120
pC
154
VDS = 50 V, VGS = 0 V
3600
5400
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
Figure 2: Transfer Characteristics
15
15
12
12
ID – Drain Current (A)
ID – Drain Current (A)
Figure 1: Typical Output Characteristics at 25°C
9
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
6
3
0
VDS = 3 V
9
6
3
0
0.5
1.0
1.5
2.0
2.5
VDS – Drain-to-Source Voltage (V)
0
3.0
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
ID = 0.5 A
ID = 1.0 A
ID = 1.5 A
ID = 2.0 A
200
150
100
50
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
4.0
4.5
5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
Figure 3: RDS(on) vs. VGS for Various Drain Currents
0
25˚C
125˚C
4.5
5.0
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25˚C
125˚C
200
ID = 1 A
150
100
50
0
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
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eGaN® FET DATASHEET
EPC2203
Figure 5b: Capacitance (Log Scale)
Figure 5a: Capacitance (Linear Scale)
140
100
120
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capacitance (pF)
Capacitance (pF)
100
80
60
10
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
1
40
20
0
0
20
40
60
0.1
80
0
20
0.18
5
0.15
4
0.12
3
0.09
2
0.06
1
0.03
0
0
20
40
60
80
60
80
0.6
0.8
Figure 6: Gate Charge
5
VGS – Gate-to-Source Voltage (V)
6
EOSS — COSS Stored Energy (µJ)
QOSS — Output charge (nC)
Figure 5c: Output Charge and COSS Stored Energy
40
VDS – Drain-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V)
3
2
1
0
0.00
ID = 1 A
VDS = 50 V
4
0
0.2
0.4
QG – Gate Charge (nC)
VDS – Drain-to-Source Voltage (V)
Figure 7: Reverse Drain-Source Characteristics
Figure 8: Normalized On-State Resistance vs. Temperature
2.0
Normalized On-State Resistance RDS(on)
ISD – Source-to-Drain Current (A)
15
25˚C
125˚C
12
9
6
3
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VSD – Source-to-Drain Voltage (V)
4.0
4.5
5.0
ID = 1 A
VGS = 5 V
1.8
1.6
1.4
1.2
1.0
0.8
0
25
50
75
100
TJ – Junction Temperature (°C)
125
150
All measurements were done with substrate shortened to source.
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 |
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eGaN® FET DATASHEET
EPC2203
Figure 9: Normalized Threshold Voltage vs. Temperature
Figure 9: Normalized Threshold Voltage vs. Temperature
1.40
Normalized Threshold Voltage
1.30
ID = 0.6 mA
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0
25
50
75
100
TJ – Junction Temperature (°C)
125
150
Figure 10: Transient Thermal Response Curves
Junction-to-Case
Junction-to-Board
1
Duty Cycle:
0.5
ZθJC, Normalized Thermal Impedance
ZθJB, Normalized Thermal Impedance
1
0.1
0.1
0.05
0.02
0.01
0.01
PDM
t1
0.001
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
Single Pulse
0.0001
10-5
t2
10-4
10-3
10-2
10-1
1
10+1
Duty Cycle:
0.5
0.2
0.1
0.05
0.02
0.01
0.01
0.1
PDM
t1
0.001
Single Pulse
0.0001
10-6
tp, Rectangular Pulse Duration, seconds
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
10-5
10-4
10-3
10-2
10-1
1
tp, Rectangular Pulse Duration, seconds
Figure 11: Safe Operating Area
I D – Drain Current (A)
10
Limited by RDS(on)
Pulse Width
1 ms
100 ms
10 ms250 µs
1 ms
100 µs
100 µs
1
0.1
0.1
1
10
100
VDS - Drain-Source Voltage (V)
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| 4
eGaN® FET DATASHEET
EPC2203
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7”reel
7” reel
d
e
f
g
Loaded Tape Feed Direction
b
AE
YYY
a
c
DIM
EPC2203 (Note 1)
a
b
c (Note 2)
d
e
f (Note 2)
g
Dimension (mm)
Target MIN MAX
8.00
7.90 8.30
1.75
1.65 1.85
3.50
3.45 3.55
4.00
3.90 4.10
4.00
3.90 4.10
2.00
1.95 2.05
1.50
1.50 1.60
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
DIE MARKINGS
Die orientation dot
Gate Pad bump is
under this corner
AE
YYY
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 |
Part
Number
EPC2203
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
AE
YYY
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eGaN® FET DATASHEET
EPC2203
A
DIE OUTLINE
Solder Bump View
g
2
d
B
4
1
3
c
MIN
Nominal
MAX
A
B
c
d
e
f
g
870
870
450
450
210
210
187
900
900
450
450
225
225
208
930
930
450
450
240
240
229
f
e
Pads 1 is Gate;
Pad 3 is Drain;
Pads 2, 4 are Source
DIM
165+/- 17
685 +/-25
Side View
Seating Plane
RECOMMENDED
LAND PATTERN
The land pattern is solder mask defined
Solder mask is 10 μm smaller per side than bump
900
(measurements in µm)
Pads 1 is Gate;
3
Pad 3 is Drain;
Pads 2, 4 are Source
X4
2
225
450
200 +20 / - 10 (*)
242
4
225
900
1
450
* minimum 190
RECOMMENDED
STENCIL DRAWING
900
Recommended stencil should be 4mil (100 µm) thick, must be
laser cut, openings per drawing.
250
0
(measurements in µm)
225
450
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
225
450
900
R6
Intended for use with SAC305 Type 4 solder, reference 88.5%
metals content.
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 |
Information subject to
change without notice.
Revised January, 2021
| 6
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