eGaN® FET DATASHEET
EPC2204
EPC2204 – Enhancement Mode Power Transistor
VDS , 100 V
RDS(on) , 6 mΩ
ID , 29 A
D
G
EFFICIENT POWER CONVERSION
HAL
S
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows
very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally
low QG and zero QRR. The end result is a device that can handle tasks where very high switching
frequency, and low on-time are beneficial as well as those where on-state losses dominate.
Maximum Ratings
PARAMETER
VALUE
VDS
Drain-to-Source Voltage (Continuous)
100
VDS
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C)
120
Continuous (TA = 25°C)
29
Pulsed (25°C, TPULSE = 300 µs)
125
ID
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
TJ
Operating Temperature
-40 to 150
TSTG
Storage Temperature
-40 to 150
VGS
UNIT
V
A
V
°C
EPC2204 eGaN® FETs are supplied only in
passivated die form with solder bars.
Die Size: 2.5 x 1.5 mm
Applications
• DC-DC Converters
• Isolated DC-DC
Converters
• Lidar
• Sync rectification for
AC-DC and DC-DC
• Point of Load Converters
• USB-C
• Class-D Audio
• LED Lighting
• E-Mobility
Benefits
Thermal Characteristics
PARAMETER
TYP
RθJC
Thermal Resistance, Junction-to-Case
1
RθJB
Thermal Resistance, Junction-to-Board
2.5
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
64
UNIT
°C/W
• Ultra High Efficiency
• No Reverse Recovery
• Ultra Low QG
• Small Footprint
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
BVDSS
Drain-to-Source Voltage
IDSS
Drain-Source Leakage
IGSS
TEST CONDITIONS
MIN
VGS = 0 V, ID = 0.25 mA
100
TYP
MAX
UNIT
V
VGS = 0 V, VDS = 80 V
0.04
Gate-to-Source Forward Leakage
VGS = 5 V
0.01
1.3
Gate-to-Source Forward Leakage#
VGS = 5 V, TJ = 125°C
0.3
6.7
Gate-to-Source Reverse Leakage
VGS = -4 V
0.03
0.2
1.1
2.5
V
6
mΩ
VGS(TH) Gate Threshold Voltage
VDS = VGS, ID = 4 mA
0.8
RDS(on)
Drain-Source On Resistance
VGS = 5 V, ID = 16 A
4.4
VSD
Source-Drain Forward Voltage#
IS = 0.5 A, VGS = 0 V
1.6
0.2
mA
V
# Defined by design. Not subject to production test.
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| 1
eGaN® FET DATASHEET
EPC2204
Dynamic Characteristics# (TJ = 25°C unless otherwise stated)
PARAMETER
CISS
Input Capacitance
CRSS
Reverse Transfer Capacitance
COSS
Output Capacitance
TEST CONDITIONS
MIN
VDS = 50 V, VGS = 0 V
TYP
MAX
644
851
2.3
304
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
RG
Gate Resistance
QG
Total Gate Charge
UNIT
pF
456
401
VDS = 0 to 50 V, VGS = 0 V
501
0.4
VDS = 50 V, VGS = 5 V, ID = 16 A
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
Ω
5.7
7.4
1.8
VDS = 50 V, ID = 16 A
0.8
nC
1
VDS = 50 V, VGS = 0 V
25
38
0
# Defined by design. Not subject to production test.
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
Figure 2: Typical Transfer Characteristics
120
120
100
100
ID – Drain Current (A)
ID – Drain Current (A)
Figure 1: Typical Output Characteristics at 25°C
80
60
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
40
= 33 VV
VDS
DS =
80
60
40
20
20
0
0
0.5
1.0
1.5
2.0
VDS – Drain-to-Source Voltage (V)
2.5
0
3.0
16
ID = 8 A
ID = 16 A
ID = 24 A
ID = 32 A
14
12
10
8
6
4
2
2.0
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
4.0
4.5
5.0
Figure 4: Typical RDS(on) vs. VGS for Various Temperatures
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
0
25˚C
125˚C
5.0
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16
25˚C
125˚C
14
12
IVDDS==163 VA
10
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
| 2
eGaN® FET DATASHEET
EPC2204
Figure 5b: Typical Capacitance (Log Scale)
Figure 5a: Typical Capacitance (Linear Scale)
1000
900
800
600
500
COSS = CGD + CSD
CISS = CGD + CGS
400
CRSS = CGD
Capacitance (pF)
Capacitance (pF)
700
300
100
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
10
200
100
0
0
25
50
75
1
100
VDS – Drain-to-Source Voltage (V)
32
1.28
4
24
0.96
16
0.64
8
0.32
40
60
VGS – Gate-to-Source Voltage (V)
5
EOSS – COSS Stored Energy (µJ)
QOSS – Output Charge (nC)
1.60
20
100
0.00
100
80
ID = 16 A
VDS = 50 V
2
1
0
0
1
2
3
4
5
6
QG – Gate Charge (nC)
Figure 8: Reverse Drain-Source Characteristics
Figure 9: Normalized On-State Resistance vs. Temperature
2.0
Normalized On-State Resistance RDS(on)
120
ISD – Source-to-Drain Current (A)
75
3
VDS – Drain-to-Source Voltage (V)
25˚C
125˚C
100
VGS = 0 V
80
60
40
20
0
50
Figure 7: Typical Gate Charge
Figure 6: Typical Output Charge and COSS Stored Energy
0
25
VDS – Drain-to-Source Voltage (V)
40
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VSD – Source-to-Drain Voltage (V)
4.0
4.5
5.0
1.8
ID = 16 A
VGS = 5 V
1.6
1.4
1.2
1.0
0.8
0
25
50
75
100
125
150
TJ – Junction Temperature (°C)
Note: Negative gate drive voltage increases the reverse drain-source voltage.
EPC recommends 0 V for OFF.
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| 3
eGaN® FET DATASHEET
EPC2204
Figure 11: Safe Operating Area
Figure 10: Normalized Threshold Voltage vs. Temperature
1000
1.4
ID = 4 mA
I D – Drain Current (A)
Normalized Threshold Voltage
1.3
1.2
1.1
1.
0.9
0.8
100
Limited by RDS(on)
10
Pulse Width
1 ms
100 µs
1
0.7
0.6
10 µs
0
25
50
75
100
TJ – Junction Temperature (°C)
125
0.1
0.1
150
1
10
VDS - Drain-Source Voltage (V)
100
1000
TJ = Max Rated, TC = +25°C, Single Pulse
Figure 12: Transient Thermal Response Curves
ZθJB, Normalized Thermal Impedance
Junction-to-Board
1 Duty Cycle:
0.5
0.2
0.1
0.1
0.05
0.02
0.01
PDM
t1
0.01 Single Pulse
0.001 -5
10
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
10-4
10-3
10-2
10-1
1
10+1
t1, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
Junction-to-Case
1 Duty Cycle:
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
PDM
t1
Single Pulse
0.001
0.0001
10-6
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
10-5
10-4
10-3
10-2
10-1
1
t1, Rectangular Pulse Duration, seconds
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
| 4
eGaN® FET DATASHEET
EPC2204
TAPE AND REEL CONFIGURATION
4 mm pitch, 8 mm wide tape on 7” reel
e
f
Loaded Tape Feed Direction
g
d
7” inch reel
Die
orientation
dot
b
YYYY
ZZZZ
c
a
Gate solder bar
is under this
corner
2204
Die is placed into pocket
solder bar side down
(face side down)
h
DIM
EPC2204 (Note 1)
a
b
c (Note 2)
d
e
f (Note 2)
g
h
Dimension (mm)
Target MIN MAX
8.00
7.90 8.30
1.75
1.65 1.85
3.50
3.45 3.55
4.00
3.90 4.10
4.00
3.90 4.10
2.00
1.95 2.05
1.50
1.50 1.60
0.50
0.45 0.55
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
DIE MARKINGS
2204
YYYY
Die orientation dot
ZZZZ
Gate Pad bar is
under this corner
DIE OUTLINE
Laser Markings
Part
Number
EPC2204
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
2204
YYYY
ZZZZ
A
m
Solder Bump View
6
B
5
c
4
k
1
g
j
3
d
2
h
Micrometers
f
e
Seating plane
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120 ± 12
518 ± 25
638
Side View
DIM
MIN
Nominal
MAX
A
B
2470
1470
2500
1500
2530
1530
c
1175
d
1350
e
500
f
250
g
300
h
825
j
787.5
k
225
m
250
Pad 1 is Gate;
Pads 2 ,4, 6 are Source;
Pads 3, 5 are Drain
| 5
eGaN® FET DATASHEET
RECOMMENDED
LAND PATTERN
A
m
2
f1
RECOMMENDED
STENCIL DRAWING
6
B
5
c1
4
h1
3
d1
j
1
g1
k
(units in µm)
EPC2204
DIM
Nominal
A
B
c1
d1
e
f1
g1
h1
j
k
m
2500
1500
1155
1330
500
230
280
805
787.5
225
250
Land pattern is solder
mask defined
Pad 1 is Gate;
Pads 2 ,4, 6 are Source;
Pads 3, 5 are Drain
e
A
m
f2
f2
g1
k
(units in µm)
B
c1
h1
d1
j
f1
R60
f2
e
DIM
Nominal
A
B
c1
d1
e
f1
f2
g1
h1
j
k
m
2500
1500
1155
1330
500
230
210
280
805
787.5
225
250
Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 4 solder, reference 88.5% metals content.
Split stencil design can be provided upon request, but EPC has tested this stencil design and not found any scooping issues.
Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
Information subject to
change without notice.
Revised November, 2022
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