eGaN® FET DATASHEET
EPC2206
EPC2206 – Automotive 80 V (D-S) Enhancement
Mode Power Transistor
VDS , 80 V
RDS(on) , 2.2 mΩ
ID , 90 A
AEC-Q101
D
EFFICIENT POWER CONVERSION
G
HAL
S
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
EPC2206 eGaN® FETs are supplied only in passivated
die form with solder bars.
Die Size: 6.05 x 2.3 mm
Maximum Ratings
PARAMETER
VDS
ID
Drain-to-Source Voltage (Continuous)
VALUE
UNIT
80
V
Continuous (TA = 25°C)
90
Pulsed (25°C, TPULSE = 300 µs)
390
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
TJ
Operating Temperature
-40 to 150
TSTG
Storage Temperature
-40 to 150
VGS
Applications
• 48 V Automotive Power
• Open Rack Server Architectures
• High Power Density DC-DC Converters
• Isolated Power Supplies
• Class D Audio
• Low Inductance Motor Drive
A
V
°C
Benefits
• Ultra High Efficiency
• No Reverse Recovery
• Ultra Low QG
• Small Footprint
Thermal Characteristics
PARAMETER
TYP
RθJC
Thermal Resistance, Junction-to-Case
0.4
RθJB
Thermal Resistance, Junction-to-Board
1.1
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
42
UNIT
°C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
80
TYP
MAX
UNIT
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 500 μA
IDSS
Drain-Source Leakage
VGS = 0 V, VDS = 80 V
20
200
µA
VGS = 6 V, TJ = 25°C
0.02
4
mA
VGS = 6 V, TJ = 125°C
0.1
9
mA
VGS = -4 V
20
200
µA
1.2
2.5
V
VGS = 5 V, ID = 29 A
1.8
2.2
mΩ
IS = 0.5 A, VGS = 0 V
1.5
Gate-to-Source Forward Leakage
IGSS
Gate-to-Source Forward
Leakage#
Gate-to-Source Reverse Leakage
VGS(TH) Gate Threshold Voltage
RDS(on)
VSD
Drain-Source On Resistance
Source-Drain
Forward Voltage#
VDS = VGS, ID = 13 mA
0.7
V
V
All measurements were done with substrate connected to source.
# Defined by design. Not subject to production test.
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| 1
eGaN® FET DATASHEET
EPC2206
Dynamic Characteristics# (TJ = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
CISS
Input Capacitance
CRSS
Reverse Transfer Capacitance
COSS
Output Capacitance
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
RG
Gate Resistance
QG
Total Gate Charge
MIN
TYP
MAX
1610
1940
VDS = 40 V, VGS = 0 V
UNIT
15
1100
pF
1650
1450
VDS = 0 to 40 V, VGS = 0 V
1790
0.3
VDS = 40 V, VGS = 5 V, ID = 29 A
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
Ω
15
19
4.1
VDS = 40 V, ID = 29 A
3
nC
2.7
VDS = 40 V, VGS = 0 V
72
108
0
All measurements were done with substrate connected to source.
# Defined by design. Not subject to production test.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
Figure 1: Typical Output Characteristics at 25°C
Figure 2: Typical Transfer Characteristics
320
ID – Drain Current (A)
ID – Drain Current (A)
320
240
160
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
80
0
0
0.5
1.0
1.5
2.0
VDS – Drain-to-Source Voltage (V)
2.5
160
80
0
3.0
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
ID = 15 A
ID = 30 A
ID = 45 A
ID = 60 A
2
2.0
2.5
3.0
3.5
4.0
4.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
4.0
4.5
5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
4
0
VDS = 3 V
240
Figure 3: RDS(on) vs. VGS for Various Drain Currents
6
25˚C
125˚C
5.0
VGS – Gate-to-Source Voltage (V)
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6
25˚C
125˚C
IVDDS==293 AV
4
2
0
2.0
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
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eGaN® FET DATASHEET
EPC2206
Figure 5b: Typical Capacitance (Log Scale)
Figure 5a: Typical Capacitance (Linear Scale)
10000
3000
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
2000
1000
Capacitance (pF)
Capacitance (pF)
2500
1500
1000
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
100
10
500
0
0
20
40
60
1
80
0
20
100
5.00
4
80
4.00
60
3.00
40
2.00
20
1.00
20
40
VGS – Gate-to-Source Voltage (V)
5
EOSS – COSS Stored Energy (µJ)
QOSS – Output Charge (nC)
6.00
0
0.00
80
60
60
80
Figure 7: Typical Gate Charge
Figure 6: Typical Output Charge and COSS Stored Energy
120
0
40
VDS – Drain-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V)
ID = 29 A
VDS = 40 V
3
2
1
0
0
5
10
15
QG – Gate Charge (nC)
VDS – Drain-to-Source Voltage (V)
Figure 8: Reverse Drain-Source Characteristics
Figure 9: Normalized On-State Resistance vs. Temperature
Normalized On-State Resistance RDS(on)
ISD – Source-to-Drain Current (A)
2.2
25˚C
125˚C
320
240
160
80
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VSD – Source-to-Drain Voltage (V)
4.0
4.5
5.0
2.0
ID = 29 A
VGS = 5 V
1.8
1.6
1.4
1.2
1.0
0.8
0
25
50
75
100
125
150
TJ – Junction Temperature (°C)
Note: Negative gate drive voltage increases the reverse drain-source voltage.
EPC recommends 0 V for OFF.
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
| 3
eGaN® FET DATASHEET
EPC2206
Figure 11: Safe Operating Area
Figure 10: Normalized Threshold Voltage vs. Temperature
1000
1.40
ID = 13 mA
I D – Drain Current (A)
Normalized Threshold Voltage
1.30
1.20
1.10
1.00
0.90
0.80
100
Limited by RDS(on)
10
Pulse Width
1 ms
250 µs
1
100 µs
0.70
0.60
0
25
50
75
100
TJ – Junction Temperature (°C)
125
0.1
0.1
150
1
10
VDS - Drain-Source Voltage (V)
100
TJ = Max Rated, TC = +25°C, Single Pulse
Figure 12: Transient Thermal Response Curves
ZθJB, Normalized Thermal Impedance
Junction-to-Board
1 Duty Cycle:
0.5
0.2
0.1
0.1
0.05
0.01
PDM
0.02
0.01
t1
Single Pulse
0.001 -5
10
10-4
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
10-3
10-2
10-1
1
10+1
t1, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
Junction-to-Case
1 Duty Cycle:
0.5
0.2
0.1
0.1
0.05
0.02
0.01 0.01
0.001
PDM
t1
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
0.0001
10-6
t2
10-5
10-4
10-3
10-2
10-1
1
t1, Rectangular Pulse Duration, seconds
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
| 4
eGaN® FET DATASHEET
EPC2206
TAPE AND REEL CONFIGURATION
e
8 mm pitch, 12 mm wide tape on 7” reel
d
7” inch reel
Loaded Tape Feed Direction
g
f
Die
orientation
dot
YYYY
ZZZZ
a b c
Gate solder bar
is under this
corner
2206
h
DIM
EPC2206 (Note 1)
Dimension (mm)
Target MIN MAX
12.00 11.90 12.30
1.75
1.65 1.85
5.50
5.45 5.55
4.00
3.90 4.10
8.00
7.90 8.10
2.00
1.95 2.05
1.50
1.50 1.60
1.50
1.50 1.75
a
b
c (Note 2)
d
e
f (Note 2)
g
h
Die is placed into pocket
solder bump side down
(face side down)
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
DIE MARKINGS
2206
YYYY
Die orientation dot
Laser Markings
Part
Number
ZZZZ
Gate Pad bump is
under this corner
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
2206
YYYY
ZZZZ
EPC2206
DIE OUTLINE
A
Solder Bump View
Micrometers
f
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
B
g
x28
(695)
Side View
Seating plane
(795)
e
x4
100 ± 20
d
2
c
x30
x30
DIM
MIN
Nominal
MAX
A
B
c
d
e
f
g
6020
2270
2047
717
210
195
400
6050
2300
2050
720
225
200
400
6080
2330
2053
723
240
205
400
Pad 1 is Gate;
Pads 2 ,5, 6, 9, 10, 13, 14, 17, 18, 21, 22,
25, 26, 29 are Source;
Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23,
24, 27, 28 are Drain;
Pad 30 is Substrate.*
*Substrate pin should be connected to Source
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
| 5
eGaN® FET DATASHEET
EPC2206
RECOMMENDED
LAND PATTERN
(units in µm)
Land pattern is solder mask defined.
6050
180
x30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2300
2030
700
x30
Pad 1 is Gate;
Pads 2, 5, 6, 9,10,13,14, 17, 18, 21, 22,
25, 26, 29 are Source;
Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23,
24, 27, 28 are Drain;
Pad 30 is Substrate.*
*Substrate pin should be connected to Source
400
x28
RECOMMENDED
STENCIL DRAWING
(units in µm)
3
5
7
R60
9
11
13
15
17
19
21
23
25
27
Intended for use with SAC305 Type 4 solder,
reference 88.5% metals content.
29
2300
1
Recommended stencil should be 4 mil (100 µm)
thick, must be laser cut, openings per drawing.
2030
700
6050
2
4
400
x28
6
8
10
12
14
16
18
20
22
24
26
28
30
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
180
x30
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
Information subject to
change without notice.
Revised June 2022
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