eGaN® FET DATASHEET
EPC2216
EPC2216 – Automotive 15 V (D-S) Enhancement
Mode Power Transistor
VDS , 15 V
RDS(on) , 26 mΩ
ID , 3.4 A
AEC-Q101
D
EFFICIENT POWER CONVERSION
G
HAL
S
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
Maximum Ratings
PARAMETER
VALUE
Drain-to-Source Voltage (Continuous)
15
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
18
Continuous (TA = 25°C)
3.4
Pulsed (25°C, TPULSE = 300 µs)
28
Gate-to-Source Voltage
6
Gate-to-Source Voltage
–4
TJ
Operating Temperature
–40 to 150
TSTG
Storage Temperature
–40 to 150
VDS
ID
VGS
UNIT
V
EPC2216 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 0.85 mm x 1.2 mm
A
Applications
V
• High Speed DC-DC conversion
• Lidar/Pulsed Power Applications
• Lidar for Augmented Reality Applications
°C
Benefits
Thermal Characteristics
PARAMETER
TYP
RθJC
Thermal Resistance, Junction-to-Case
5.7
RθJB
Thermal Resistance, Junction-to-Board
39
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
97
UNIT
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
°C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
PARAMETER
BVDSS
Drain-to-Source Voltage
IDSS
Drain-Source Leakage
Static Characteristics (TJ= 25°C unless otherwise stated)
TEST CONDITIONS
TYP
MAX
UNIT
VDS = 15 V, VGS = 0 V, TJ = 25°C
0.01
0.1
mA
VGS = 0 V, ID = 0.1 mA
MIN
15
V
Gate-to-Source Forward Leakage
VGS = 5 V, TJ = 25°C
0.004
0.5
mA
IGSS
Gate-to-Source Forward Leakage#
VGS = 5 V, TJ = 125°C
0.02
1
mA
Gate-to-Source Reverse Leakage
VGS = -4 V, TJ = 25°C
0.01
0.1
mA
VGS(TH)
Gate Threshold Voltage
VDS = VGS, ID = 1 mA
1
2.5
V
RDS(on)
Drain-Source On Resistance
VGS = 5 V, ID = 1.5 A
20
26
mΩ
VSD
Source-Drain Forward Voltage
IS = 0.5 A, VGS = 0 V
1.9
0.7
V
# Defined by design. Not subject to production test.
All measurements were done with substrate connected to source.
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 |
| 1
eGaN® FET DATASHEET
EPC2216
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
Capacitance#
CISS
Input
CRSS
Reverse Transfer Capacitance
COSS
Output Capacitance#
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
RG
Gate Resistance
QG
Total Gate Charge#
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge#
QRR
Source-Drain Recovery Charge
VDS = 7.5 V, VGS = 0 V
TYP
MAX
98
118
UNIT
20
66
99
pF
69
VDS = 0 to 7.5 V, VGS = 0 V
71
0.5
VDS = 7.5 V, VGS = 5 V, ID = 1.5 A
Ω
0.87
1.1
0.21
VDS = 7.5 V, ID = 1.5 A
0.13
nC
0.16
VDS = 7.5 V, VGS = 0 V
0.53
0.8
0
# Defined by design. Not subject to production test.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
Figure 2: Transfer Characteristics
25
25
20
20
ID – Drain Current (A)
ID – Drain Current (A)
Figure 1: Typical Output Characteristics at 25°C
15
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
10
5
0
0
0.5
1.0
1.5
2.0
VDS – Drain-to-Source Voltage (V)
2.5
25°C
25˚C
125˚C
125°C
= 33 VV
VDS
DS =
15
10
5
0
3.0
0.5
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
ID = 0.8 A
ID = 1.5 A
ID = 2.2 A
ID = 3 A
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
70
50
1.5
VGS – Gate-to-Source Voltage (V)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
60
1.0
5.0
VGS – Gate-to-Source Voltage (V)
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 |
70
60
25°C
125°C
50
ID = 1.5 A
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
| 2
eGaN® FET DATASHEET
EPC2216
Figure 5b: Capacitance (Log Scale)
Figure 5a: Capacitance (Linear Scale)
1000
120
Capacitance (pF)
Capacitance (pF)
100
80
60
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
40
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
100
20
0
0
2.5
5.0
7.5
10.0
12.5
10
15.0
0
2.5
5.0
0.0064
4
0.72
0.0048
0.48
0.0032
0.24
0.0016
2.5
0.0
5.0
7.5
10.0
VGS – Gate-to-Source Voltage (V)
0.96
0.00
10.0
12.5
15.0
Figure 7: Gate Charge
5
EOSS – COSS Stored Energy (μJ)
QOSS – Output Charge (nC)
Figure6:6a:Output
OutputCharge
Chargeand
andCOSS
COSSStored
StoredEnergy
Energy
Figure
0.0080
1.20
7.5
VDS – Drain-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V)
0.0000
15.0
12.5
ID = 1.5 A
VDS = 7.5 V
3
2
1
0
VDS – Drain-to-Source Voltage (V)
0
0.2
0.4
0.6
0.8
1.0
QG – Gate Charge (nC)
Figure 8: Reverse Drain-Source Characteristics
Figure 9: Normalized On-State Resistance vs. Temperature
2.0
Normalized On-State Resistance RDS(on)
ISD – Source-to-Drain Current (A)
25
25°C
125°C
20
VGS = 0
15
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VSD – Source-to-Drain Voltage (V)
4.0
4.5
5.0
1.8
ID = 1.5 A
1.6
VGS = 5 V
1.4
1.2
1.0
0.8
0
25
50
75
100
125
150
TJ – Junction Temperature (°C)
All measurements were done with substrate shortened to source.
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 |
| 3
eGaN® FET DATASHEET
EPC2216
Figure 11: Safe Operating Area
Figure 10: Normalized Threshold Voltage vs. Temperature
100
1.4
1.2
ID = 1 mA
ID – Drain Current (A)
Normalized Threshold Voltage
1.3
1.1
1.0
0.9
0.8
10
Limited by RDS(on)
1
Pulse Width
1 ms
100 μs
0.7
0.6
0
25
50
75
100
125
0.1
0.1
150
1
10
100
VDS – Drain-Source Voltage (V)
TJ – Junction Temperature (°C)
Figure 12: Transient Thermal Response Curves
ZθJB, Normalized Thermal Impedance
Junction-to-Board
1 Duty Cycle:
0.5
0.2
0.1
0.1
0.05
0.01
PDM
0.02
0.01
t1
Single Pulse
0.001
10-5
10-4
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
10-3
10-2
10-1
1
101
tp, Rectangular Pulse Duration, seconds
Junction-to-Case
ZθJC, Normalized Thermal Impedance
1
Duty Cycle:
0.5
0.2
0.1
0.1
0.05
0.01
PDM
0.02
0.01
0.001
10-5
t1
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
10-4
t2
10-3
10-2
10-1
1
101
tp, Rectangular Pulse Duration, seconds
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 |
| 4
eGaN® FET DATASHEET
EPC2216
TAPE AND REEL CONFIGURATION
4 mm pitch, 8 mm wide tape on 7” reel
7” reel
d
e
f
g
Loaded Tape Feed Direction
Gate solder bump is
under this corner
Die orientation dot
b
2216
YYYY
ZZZZ
a
c
Die is placed into pocket
solder bump side down
(face side down)
EPC2216 (note 1)
Dimension (mm) target min
a
b
c (note 2)
d
e
f (note 2)
g
8.00
1.75
3.50
4.00
4.00
2.00
1.5
7.90
1.65
3.45
3.90
3.90
1.95
1.5
max
8.30
1.85
3.55
4.10
4.10
2.05
1.6
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
Part
Number
EPC2216
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking line 3
2216
YYYY
ZZZZ
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 |
2216
YYYY
ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
| 5
eGaN® FET DATASHEET
EPC2216
A
DIE OUTLINE
Micrometers
f
e
Solder Bump View
6
2
5
B
c
3
11
4
Seating Plane
850
880
1230
187
185
210
229
215
240
The land pattern is solder mask defined
Solder mask is 10 μm smaller per side than bump
200
225
1
MAX
850
1200
400
208
200
225
165+/- 17
695+/-15
Side View
4
Pad 1 is Gate;
Pads 2 , 5 are Drain;
400
(measurements in µm)
Nominal
820
1170
Pad 1 is Gate;
Pads 2, 5 are Drain;
Pads 3, 4, 6 are Source
c
RECOMMENDED
LAND PATTERN
MIN
A
B
c
d
e
f
860 Typ
c
d
DIM
2
400
5
1200
Pads 3, 4, 6 are Source
200 +20 / - 10 (*)
3
6
400
* minimum 190
RECOMMENDED
STENCIL DRAWING
Stencil opening
250 μm rounded square (60 deg)
4 mil stencil stainless laser cut
type 4 solder
Solder mask opening
200 μm
(measurements in µm)
200 μm
+20 μm / -10 μm
Min 190 μm
Recommended stencil should be 4 mil (100 µm)
thick, must be laser cut, openings per drawing.
250 μm
400 μm
175 μm
400 μm
175 μm
400 μm
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 |
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
200 μm
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
Intended for use with SAC305 Type 4
solder, reference 88.5% metals content.
Information subject to change
without notice.
Revised May, 2020
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