eGaN® FET DATASHEET
EPC23103
EPC23103 – ePower™ Stage IC
VIN , 100 V
ILoad , 25 A
Y
NAR
I
M
I
REL
EFFICIENT POWER CONVERSION
P
10
23
C
EP
The ePowerTM Stage IC Product Family integrates input logic interface, level shifting, bootstrap charging
and gate drive buffer circuits along with eGaN output FETs. Integration is implemented using EPC’s
proprietary GaN IC technology. The end result is a Power Stage IC that translates logic level input to
high voltage and high current power output that is smaller in size, easier to manufacture, simpler to
design and more efficient to operate.
3
HAL
Key Parameters
PARAMETER
VALUE
Power Stage Load Current (1 MHz)
Pulsed current (25°C, Tpulse = 300 μs)
Operating PWM Frequency (Minimum)
Operating PWM Frequency (Maximum)
Absolute Maximum Input Voltage
Operating Input Voltage Range
Nominal Bias Supply Voltage
UNIT
25
109
5
3
100
80
5
A
kHz
MHz
V
Output Current and PWM Frequency Ratings are specified at ambient temperature of 25°C. See Application Information
section for rating methodologies, test conditions, thermal management techniques and thermal derating curves.
Device Information
PART NUMBER
Rated RDS(on) for HS and LS FETs at 25 °C
QFN Package Size (mm)
7.6 mΩ + 7.6 mΩ
3.5 x 5
EPC23103
All exposed pads feature wettable flanks that allow side wall solder inspection. High voltage and low voltage pads
are separated by 0.6mm spacing to meet IPC rules.
98
32
97
28
96
24
95
20
94
16
93
12
500 kHz
1 MHz
2 MHz
92
91
90
0
5
10
15
20
ILOAD (A)
25
30
8
Total Power Loss (W)
Efficiency (%)
Figure 1: Performance Curves
4
35
0
Buck Converter, VIN = 48 V, VOUT = 12 V, Deadtime = 10 ns, L = 2.2 µH, DCR = 700 µΩ, Top Side Heatsink
attached, Airflow = 400 LFM, TA = 25°C, using EPC90151 Evaluation Board.
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
EPC23103 ePowerTM Stage IC
Package size: 3.5 x 5 mm
Applications
• Buck, Boost, Buck-Boost Converters
• Half-Bridge, Full Bridge LLC Converters
• Motor Drive Inverter
• Class D Audio Amplifier
Features
• Integrated high side and low side eGaN® FET with
internal gate driver and level shifter
• 5 V external bias supply
• 3.3 V or 5 V CMOS input logic levels
• Independent high side and low side control inputs
• Logic lockout commands both FETs off when inputs
are both high at same time
• External resistors to tune SW switching times and
over-voltage spikes above rail and below ground
• Robust level shifter operating for hard and soft
switching conditions
• False trigger immunity from fast switching transients
• Synchronous charging for high side bootstrap supply
• Disable input engages low quiescent current mode
from VDRV supply
• Power on reset for low side VDD supply
• Power on reset for high side VBoot supply
• Active gate pull-down for HS FET and LS FET with loss
of VDRV supply
• Thermally enhanced QFN
package with exposed top
for low thermal resistance
from junction to top-side
heatsink
https://l.ead.me/EPC23103
| 1
eGaN® FET DATASHEET
EPC23103
Figure 2: EPC23103 Quad Flat No-Lead (QFN)
Package (Transparent Top View)
8
9
10
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
7
11
6
12
13
1
2
3
Transparent Top View
4
5
Description
HSIN
LSIN
SD
VDD
VDRV
RDRV
AGND
PGND
SW
VIN
VPHASE
RBOOT
VBOOT
EPC23103 Pinout Description
Pin Pin Name Pin Type Description
1
HSIN
L
High side PWM logic input, level referenced to AGND. Internal pull-down
resistor is connected between HSIN and AGND.
2
LSIN
L
Low side PWM logic input, level referenced to AGND. Internal pull-down
resistor is connected between LSIN and AGND.
3
SD
L
VDD disable input, level referenced to AGND. Internal VDD will be disabled
when SD is pulled up to VDRV or external 5 V source. Internal pull-down
resistor is connected between SD and AGND, thereby VDD will follow VDRV
with SD connected to AGND by default.
4
VDD
S
Internal power supply referenced to AGND, connect a bypass capacitor from
VDD to AGND.
5
VDRV
S
External 5 V nominal power supply referenced to AGND, connect a bypass
capacitor from VDRV to AGND.
6
RDRV
G
Insert resistor between RDRV to VDRV to control the turn-on slew rate of the
driven low side FET.
7
AGND
S
Logic ground. Connect bypass capacitors between operating bias supplies,
VDRV and VDD, to AGND. Internal IC connection between AGND and PGND. Use
star ground external connection with PGND to system ground.
8
PGND
P
Input power supply ground return. Connected to source terminal of internal
low side FET. Connect power loop capacitors from VIN to PGND.
9
SW
P
Output switching node. Connected to output of half-bridge power stage.
SW pin connects together the source terminal of high side FET and the drain
terminal of the low side FET.
10
VIN
P
Power bus input. Connected to drain terminal of internal high side FET.
Connect power loop capacitors from VIN to PGND or power source terminals
of low side FET.
11
VPHASE
S
Kelvin connection to SW, the output switching node. The floating bootstrap
power supply, VBOOT , is also referenced to VPHASE.
12
RBOOT
G
Insert resistor between RBOOT to VBOOT to control the turn-on slew rate of the
internal high side FET.
Floating bootstrap power supply referenced to VPHASE (=SW). Connect an
external bypass capacitor from VBOOT to VPHASE.
Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust
13
VBOOT
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
S
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eGaN® FET DATASHEET
EPC23103
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur and device reliability
may be affected. All voltage parameters are absolute voltages referenced to PGND (=AGND) unless indicated otherwise.
Absolute Maximum Ratings
SYMBOL
PARAMETER
VIN
Input Voltage (VIN to PGND)
MIN
MAX
100
SW(continuous)
Output Switching Node (SW to PGND), Continuous
100
VDRV
External Bias Supply (VDRV to AGND)
6
VDD
Internal Low Side Supply Voltage (VDD to AGND)
6
VBOOT – VPHASE
Internal High Side Supply Voltage (VBOOT to VPHASE), VPHASE = SW
HSIN, LSIN
PWM Logic Inputs (HSIN to AGND and LSIN to AGND)
5.5
SD
VDD Disable Input (SD to AGND)
5.5
TJ
Junction Temperature
TSTG
Storage Temperature
UNITS
V
6
150
-55
150
MIN
MAX
°C
ESD Ratings
ESD Ratings
SYMBOL
PARAMETER
HBM
Human-body model (JEDEC JS-001)
+/-1000
CDM
Charged-device model (JEDEC JESD22-C101)
+/-500
UNITS
V
Thermal Characteristics
RθJA_JEDEC is measured using JESD51-2 standard setup with 1 cubic foot enclosure with no forced air cooling, heat dissipated
only through natural convection. The test used JEDEC Standard 4-layers PCB with 2 oz top and bottom surface layers and
1 oz buried layers. RθJA_EVB is measured using EPC90151 EVB with no forced air cooling, this rating is more indicative of
actual application environment.
Thermal Characteristics
SYMBOL
PARAMETER
TYP
RθJC_Top
Thermal Resistance, Junction-to-Case (Top surface of exposed die substrate)
0.45
RθJB_Bottom
Thermal Resistance, Junction-to-Board (At solder joints of VIN, SW and PGND pads)
2.7
RθJA_JEDEC
Thermal Resistance, Junction-to-Ambient (using JEDEC 51-2 PCB)
46
RθJA_EVB
Thermal Resistance, Junction-to-Ambient (using EPC90151 EVB)
26
UNITS
°C/W
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to PGND (= AGND) unless indicated otherwise.
Recommended Operating Conditions
SYMBOL
PARAMETER
MIN
TYP
MAX
VIN
Input Voltage (VIN to PGND)
SW(Q3 Mode)
Output Switch Node, 3rd Quadrant Mode
SW(pulse2ns)
Output Switch Node, Transient PW < 2 ns
-10
VDRV
External Bias Supply (VDRV to AGND)
4.75
5
5.5
VDD
Internal Low Side Supply Voltage (VDD to AGND)
4.75
5
5.5
VBOOT – VPHASE
Internal High Side Supply Voltage (VBOOT to VPHASE), VPHASE = SW
4.75
5
5.5
HSIN, LSIN
PWM Logic Inputs
SD
PW_min
PW_max
Maximum Input On or Off Pulse Duration, 50% to 50% width
TJ
Operating Junction Temperature
10
80
-2.5
VIN + 2.5
VIN +10
0
5
VDD Disable Input
0
5
Minimum Input On or Off Pulse Duration, 50% to 50% width
20
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
-40
UNITS
V
ns
200
µs
125
°C
| 3
eGaN® FET DATASHEET
EPC23103
Electrical Characteristics
Nominal VIN = 48 V, VDRV = VDD = 5 V and (VBOOT – VPHASE) = 5 V. All typical ratings are specified at TA = 25˚C unless otherwise indicated.
All voltage parameters are absolute voltages referenced to PGND (= AGND) unless indicated otherwise.
SYMBOL
PARAMETER
Low Side Power Supply
Electrical Characteristics
TEST CONDITIONS
MIN
TYP
IDRV_Q
Off State Total Quiescent Current
HSIN/LSIN/SD = 0 V, VDRV = VDD = 5 V
10
IDRV_100kHz
Total Operating Current @100 kHz
PWM = 100 kHz, 50% On-Time
14
IDRV_1MHz
Total Operating Current @1 MHz
PWM = 1 MHz, 50% On-Time
22
IVIN_disable
IDRV_disable
VIN Quiescent Current at Disable Mode
VDRV Quiescent Current at Disable Mode
SD = VDRV = 5 V, VIN = 48 V
SD = VDRV = 5 V, VIN = 48 V
MAX
UNITS
mA
600
50
µA
Bootstrap Power Supply
IBOOT_Q
IBOOT_100kHz
IBOOT_1MHz
VSYNC_BOOT
Off State Bootstrap Supply Current
Bootstrap Supply Current @100 kHz
Bootstrap Supply Current @1 MHz
Sync Boot Generated (VBOOT -VPHASE)
HSIN = 0 V, (VBOOT – VPHASE) = 5 V
HS PWM = 100 kHz, 50% On-Time
HS PWM = 1 MHz, 50% On-Time
ISYNC_BOOT = 20 mA
6
7
14
4.75
POR Trip Level VDD Rising
POR VDD Falling Hysteresis
POR Trip Level (VBOOT - VPHASE) Rising
POR (VBOOT - VPHASE) Falling Hysteresis
LSIN = 5 V, VDD Ramps Up
LSIN = 5 V, VDD Ramps Down
HSIN = 5 V, VBOOT Ramps Up
HSIN = 5 V, VBOOT Ramps Down
4
0.5
4
0.5
High-level Logic Threshold
Low-level Logic Threshold
Logic Threshold Hysteresis
HSIN and LSIN Pull-Down Resistance
HSIN , LSIN Rising
HSIN , LSIN Falling
VIH Rising – VIL Falling
HSIN , LSIN = 5 V
2.4
SD Input Threshold
SD Pull-Down Resistance
VDRV = 5 V
SD = 5 V
3.3
mA
V
Power On Reset
VDD_POR+
VDD_POR_HYST
VBOOT_POR+
VBOOT_POR_HYST
V
Logic Input Pins
VIH
VIL
VIHYST
RIN
VDD Disable Input
V TH_EN
REN
0.8
V
0.3
6.5
kΩ
150
V
kΩ
High Side Internal Power FET
RDS(on)_HS
VHS_DS_Clamp
ILEAK_VIN-SW
CWELL
High Side FET RDS(on)
High Side 3rd Quadrant Clamp
Leakage Current (VIN to SW)
HV-Well Capacitance (SW to PGND)
IDS = +/-10 A, HSIN = 5 V, LSIN = 0 V
IDS = - 10 A, HSIN & LSIN = 0 V
HSIN = 0 V, VIN = 100 V, SW = 0 V
HSIN = 0 V, VIN = 48 V, SW = 48 V
6
-1.5
COSS_HSFET
Output Capacitance (VIN to SW)
HSIN = 0 V, VIN = 48 V, SW = 0 V
264
QOSS_HSFET
EQOSS_HSFET
Output Charge (VIN to SW)
Output Capacitance Stored Energy
HSIN = 0 V, VIN = 48 V, SW = 0 V
HSIN = 0 V, VIN = 48 V, SW = 0 V
21
0.38
HS Turn-On, SW = 0 V to 48 V, RBOOT = 0 Ω, ILOAD = 10 A
2.1
HS Turn-On, SW = 0 V to 48 V, RBOOT = 2.2 Ω, ILOAD = 10 A
3.8
HS Turn-Off, SW = 48 V to 0 V, ILOAD = 10 A
0.13
EON_HS_0
EON_HS_1
EOFF_HS
Turn-On Switching Energy (HS_FET)
Turn-Off Switching Energy (HS_FET)
7.6
300
39
mΩ
V
µA
pF
nC
µJ
Low Side Internal Power FET
RDS(on)_HS
VHS_DS_Clamp
ILEAK_SW-PGND
Low Side FET RDS(on)
Low Side 3rd Quadrant Clamp
Leakage Current (SW to PGND)
IDS = +/-10 A, LSIN = 5 V, HSIN = 0 V
IDS = - 10 A, HSIN & LSIN = 0 V, SW = 0 V, SW = 0 V
LSIN = 0 V, VIN = 100 V, SW = 100 V
6
-1.5
COSS_LSFET
Output Capacitance (SW to PGND)
LSIN = 0 V, SW = 48 V, PGND = 0 V
264
pF
QOSS_LSFET
EQOSS_LSFET
Output Charge (SW to PGND)
Output Capacitance Stored Energy
LSIN = 0 V, SW = 48 V, PGND = 0 V
LSIN = 0 V, SW = 48 V, PGND = 0 V
21
0.38
nC
LS Turn-On, SW = 48 V to 0 V, RBOOT = 0 Ω, ILOAD = 10 A
2.1
LS Turn-On, SW = 48 V to 0 V, RBOOT = 2.2 Ω, ILOAD = 10 A
3.8
LS Turn-Off, SW = 0 V to 48 V, ILOAD = 10 A
0.13
EON_LS_0
EON_LS_1
EOFF_LS
Turn-On Switching Energy (LS_FET)
Turn-Off Switching Energy (LS_FET)
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
7.6
100
mΩ
V
µA
µJ
| 4
eGaN® FET DATASHEET
EPC23103
Electrical Characteristics (continued)
Electrical Characteristics (continued)
SYMBOL
PARAMETER
TEST CONDITIONS
Dynamic Characteristics (Logic Input to Output Switching Node) See Figure 3a and 3b for Timing Diagram and Test Circuit)
MIN
TYP
t_delayHS_on
High-Side On Propagation Delay
SW = 0 V and HS FET Turn-On
20
t_delayLS_on
Low-Side On Propagation Delay
SW = 48 V and LS FET Turn-On
20
t_delayHS_off
High-Side Off Propagation Delay
SW = 48 V and HS FET Turn-Off
20
t_delayLS_off
Low-Side Off Propagation Delay
SW = 0 V and LS FET Turn-Off
20
t_matchon
Delay Matching LSoff to HSon
LS Turn-Off to HS Turn-On
0
t_matchoff
Delay Matching HSoff to LSon
HS Turn-Off to LS Turn-On
0
t_riseSW_HS0
SW Rise Time at High Side FET Turn-On
(Buck Mode, Hard Switching)
HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 0 Ω, ILoad = 5 A
t_riseSW_HS1
t_fallSW_LS0
t_fallSW_LS1
UNITS
ns
1.5
HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 2.2 Ω, ILoad = 5 A
3
LS Turn-On Boost Mode, 48 V to 0 V, RDRV = 0 Ω, ILoad = 5 A
SW Fall Time at Low Side FET Turn-On
(Boost Mode, Hard Switching)
MAX
1.5
LS Turn-On Boost Mode, 48 V to 0 V, RDRV= 2.2 Ω , ILoad = 5 A
3
Dynamic Characteristics Parameter Definition
Figure 3a: Test Circuit for Dynamic Characteristics
5V
High side
input
(5 V, 50 Ω)
RDRV
1 µF
37.4 Ω
150 Ω
150 Ω
100 nF
VDRV
VIN
RDRV
VBOOT
VDD
RBOOT
HSIN
SW
LSIN
PGND
SD
Low side
input
(5 V, 50 Ω)
48 V
RBOOT
2.2 mH
47 mF
5A
1 kΩ 5 W
AGND
EPC23103
37.4 Ω
150 Ω
100 nF
SWa
150 Ω
To
oscilloscope
To oscilloscope
50 Ω
To
oscilloscope
Figure 3b: Logic Input to Output Switching Node Timing Diagram
50%
HSIN
LSIN
50%
2.5 V
2.5 V
t_delayHS_off
~1.46 V
30 mV
SWa
~0 V
t_delayLS_off
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
-30 mV
t_delayHS_on
t_delayLS_on
| 5
eGaN® FET DATASHEET
EPC23103
Truth Table
VDD
VBOOT – VPHASE
VDD_POR
>VDD_POR
HSIN
VBOOT_POR
LSIN
HS FET
LS FET
–
–
OFF
OFF
–
0
OFF
OFF
–
1
OFF
ON
0
0
OFF
OFF
0
1
OFF
ON
1
0
ON
OFF
1
1
OFF
Application Information
Figure 4: Functional Block Diagram
The EPC23103 ePowerTM Stage IC integrates
a half-bridge gate driver with internal
high side and low side FETs. Integration
is implemented using EPC’s proprietary
GaN IC technology. The monolithic chip
integrates input logic interface, level
shifting, bootstrap charging and gate drive
buffer circuits controlling high side and
low side eGaN output FETs configured as
a half-bridge power stage. Robust level
shifters from low side to high side channels
are designed to operate correctly with
soft and hard switching conditions even
at large negative clamped voltage and to
avoid false trigger from fast dv/dt transients
including those driven by external sources
or other phases. Internal circuits integrate
the functions of charging and disabling of
the logic and bootstrap power supplies.
Protection features are added to protect the
output FETs from unwanted turn-on at low
or even complete loss of supply voltages.
CDD
4
5
VDRV
CDRV
The single chip is mounted inside a 3.5 x 5 mm Quad
Flat No-lead (QFN) package using a flip chip on leadframe technique. This packaging structure allows very
low parasitic inductance from the power terminals to
the underlying PCB solder pads. The exposed EPC23103
QFN pads are designed to have at least 0.6 mm spacing
between high and low voltage pins to meet IPC voltage
creepage rule for 100 V. Another enhancement exposes
the backside of the Gan IC die on the top side of the
package while completely encapsulating the rest of the
GaN IC die. This allows a very low thermal resistance
path from the die junction to an attached heatsink
which in effect increase the allowable power dissipation
and thus higher current handling capability.
3
Shutdown
logic
VIN
GND
HSIN
2
LSIN
7
AGND
Logic
+
POR
+
Crossover
LO
VBOOT 13
RBOOT 12
VIN 10
POR
Sync
boot
SD
150 k
1
High side
VDD
Level
shift
CBOOT
VIN
Gate
driver
CIN
VPHASE 11
EPC23103
Delay
match
level
shift
SW
9
SW
RDRV 6
VDD
VDRV
Gate
driver
PGND 8
PGND
Figure 5: EPC23103 QFN package outline, pinouts and exposed backside of
the GaN IC die
Bottom
10
9
8
11
12
13
Top
Site/date code
Lot code
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
E
23 PC
C 1
12 YY 03
34 WW
56 E
General Description
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5
4
3
2
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eGaN® FET DATASHEET
EPC23103
Output Current Rating
Power stage output current rating is best thought of as a figure
of merit for specified output current level that accounts for the
maximum amount of power dissipation allowed from the IC. Total
power dissipation from a power stage IC is tied to the application
circuit topologies, output current demand, switching frequencies, PCB
construction, operating temperature range, thermal management
technique and mechanical stress limit of the metallization imposed
by electromigration. The rating is related to the respective maximum
current capability of the two integrated output FETs in the half-bridge
power stage but not measured the same way as individual discrete FET.
For a power stage IC such as EPC23103, total power loss from the IC is
the sum of the two output FETs conduction, switching and deadtime
losses imposed by the application topologies at operating switching
frequencies as well as power losses from the gate drive and logic circuit.
The maximum power dissipation is defined by the following formula:
Max PDiss = (Max TJ - TA)/ RθJA
where Max TJ is specified at 125 °C and the ambient temperature
is specified at 25 °C. The big variable in achieving the theoretical
maximum power dissipation is RθJA, the thermal resistance from
junction to ambient. The EPC23103 package construction allows two
parallel path of heat dissipation where the bottom path goes from
junction to metallization to lead-frame then the exposed pads at the
bottom of the package. The three power bars (VIN, SW and PGND) are
designed to allow maximum contact area to the underlying PCB pads to
achieve a RθJB_bottom of 3 °C/W. The total thermal resistance to ambient
in this path of RθJA_bottom needs to add the heat dissipation from the PCB
pads through the multi-layer PCB construction then radiating to the
ambient which is highly dependent on the airflow and forced cooling
method. (See Figure 6).
Figure 6: Parallel Thermal Resistance Paths of EPC23103 IC
from junction to ambient
= Heat path
Heatsink
To achieve even lower effective thermal resistance, another path is
provided from junction to the relatively lower thermal resistance Si
substrate of the GaN IC structure to the exposed backside of the entire
die at the top of the package to achieve a RθJC_top of 0.4 °C/W. This lower
thermal resistance path facilitates attachment of a topside heatsink
through thermal interface material (TIM) to the exposed backside of
the die. Note that the backside of the die is connected to the PGND
(=AGND) pins which potentially provides added benefits of using
electrically conductive TIM which has >2X higher thermal conductivity
and lower cost than the insulating type. Typical parameters of electrically
conducting vs. insulating TIMs are shown in the table below.
Typical parameters of electrically conducting vs. insulating TIMs
Thermal Conductivity
(W/m-K)
Relative
Cost
Electrically Conducting
40
1
Electrically Insulating
15
1.3
Type of TIM
Another factor in specifying the output current rating is electromigration
from a metallurgical standpoint. For EPC23103 this limit is a function
of the metallization structure underlying the two output FETs plus
their connection to the lead-frame and the three exposed power bars.
A maximum of 39 A is allowed due to electromigration limit.
EPC uses a reference evaluation board, EPC90151 as shown in Figure 7,
configured in a Buck Converter topology with the following test conditions:
VIN = 48 V, VOUT = 12 V, PWM frequency = 0.5, 1, and 1.5 MHz, with and
without top side heatsink, airflow = 500 and 1000 LFM, operating at
ambient temperature starting at 25°C, maximum TC not to exceed 110°C
(derated from 125°C to avoid thermal runaway).
Figure 7: EPC90151 Evaluation Board
(see EPC90151 Quick Start Guide for details)
TIM: Soft Thermal Pad
r-Global P/N: TB-X 500 µm
200-300 µm compressed
thickness
RθJC (top) =
0.4 °C/W
RθJC (bottom) =
3 °C/W
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| 7
eGaN® FET DATASHEET
EPC23103
Thermal derating curves in Figure 8 are derived from measurement
data. At ambient temperature of 25°C using topside heatsink, the
EPC23103 IC is specified with an output current handling capability
greater than 35 A operating at 1 MHz switching frequency with airflow
greater than 500 LFM. But without the benefit of topside heatsink, the
same conditions at 1 MHz and 500 LFM, the current rating is reduced to
16 A at ambient temperature of 25°C showing the dramatic difference
of using the lower RθJC_top of the higher thermal conductive path.
Figure 8: Thermal Derating Curves for Output Current Rating of
EPC23103 IC using EPC90151 Evaluation Board
45
500 kHz
500 kHz
1 MHz
1 MHz
2 MHz
2 MHz
With
Heat
si
35
nk
ILOAD (A)
30
25
20
No Hea
t
sink
10
25
35
45
55
65
75
85
95
105
Ambient Temperature (°C)
Thermal Derating Curves: 400 LFM
500 kHz
500 kHz
1 MHz
1 MHz
2 MHz
2 MHz
40
With
Heat
si
35
nk
30
ILOAD (A)
VIN
LSG
QOFF
25
20
15
No Hea
t
sink
10
5
25
35
45
55
Sync
boot
drive
VDDON
drive
SD
AGND
VDDON
VBOOTON
QSA
QSB
VBOOT
VDD
5
0
Figure 9: Simplified circuit diagram of VIN , VDRV , VDD , and VBOOT
Power Supplies
VDRV
15
45
The EPC23103 IC only requires an external 5 V VDRV power supply.
Internal low side and high side power supplies, VDD and VBOOT, are
generated from the external supply via two series connected switches.
Figure 9 shows the simplified circuit diagram of the different power
supplies inside the IC and their interaction with each other.
Thermal Derating Curves: 1000 LFM
40
0
Power Supplies – VIN , VDRV , VDD , and VBOOT
65
75
Ambient Temperature (°C)
85
95
105
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
The internal supplies can be disabled to save quiescent power by
turning off the series switch, QSA in Figure 9, with 5 V applied to the SD
pin to engage chip shutdown mode. In this mode, minimum current is
drawn from the external VDRV supply while VDD is open circuit. Whatever
charges remain within the VDD bypass capacitor will be discharged by
the chip internal circuits at nominal rate of 10 mA/CDD.
In the chip shutdown circuit, series switch (QSA) between VDRV and VDD is
turned off by internal disable circuit which itself derived its power from
VIN such that the chip draws a maximum up to 600 µA at 48 V from VIN
when shutdown mode is engaged. The minimum input voltage (VINmin)
should be at least 10 V for the IC to be enabled. Below the minimum
VIN the pass-transistor between VDRV and VDD will be off. Same condition
when VDD disable pin, EN, is connected to 5 V.
The series connected high voltage synchronous bootstrap FET, QSB in
Figure 9, between VDD and VBOOT for the high side floating bootstrap
supply is activated only after the LS FET (Q2) is turned on to avoid
overcharging during deadtime. The use of GaN FET in the charging path
eliminates reverse recovery and reduces power dissipation. Another
advantage is the lower dropout voltage of 100 to 200 mV from the
synchronous FET versus typical Si bootstrap diode voltage of 0.6 V.
With synchronous charging VBOOT is maintained closer to the VDD
voltage, allowing the HS FET gate drive circuit to have similar gate drive
current and delay performance as the LS FET gate drive circuit.
| 8
eGaN® FET DATASHEET
EPC23103
Gate Driver
The EPC23103 IC integrates both HS and LS FET gate drivers with very low
impedance (0.4 Ω) and high pulse current (5 A) push-pull NFET output stage.
Figure 10 is the simplified circuit diagram of the gate driver output stage.
Figure 10: Simplified Circuit Diagram of Gate Driver Output
Stage
VDD
Internal
Bootstrap
Gate
Drive
A
The switching rate and transients at the output node, SW, is controlled
by application topologies resulting in hard or soft switching transitions.
The more stressful hard switching transition needs to be controlled by
a combination of tuning gate drive turn-on and turn-off circuits for the
HS FET (Q1) and LS FET (Q2) and minimizing the power loop parasitic
inductances.
The on-chip gate drive buffers practically eliminate effects of common
source inductance and gate drive loop inductance. Switching times are
tuned by external resistors, RDRV and RBOOT , as shown in Figure 12 to
achieve SW switching rate of 10 to 50 V/ns spanning zero to full load
current. The choice of switching rates is dictated by efficiency versus
EMI mitigation.
MPO
Q
CB1
SW Node Switching Transients
Figure 12: Simplified circuit diagram of external tuning resistor,
internal gate drivers and output FETs
MSO
MS1
VIN
VBOOT
The HS and LS gate drive voltage levels are derived from their respective
internal low side (VDD) and high side (VBOOT) power supplies. To ensure
that the gate drive level (Q) is sufficiently close to VDD or VBOOT, an internal
bootstrap circuit is used to turn-on MPO. Here the MPO and MSO pair
works similarly to the half-bridge power stage Q1 and Q2 output FETs
except all the circuits are internal to the IC. CB1 is an internal bootstrap
capacitor. The PWM inputs, HSIN and LSIN, are used as the clocks for their
respective high side and low side internal bootstrap gate drive circuit.
As with any bootstrap circuit, the gate drive output cannot have 100%
duty cycle to allow CB1 to be recharged. For the EPC23103 IC, the PWM
input pulse width must not exceed a maximum of 200 µs on/off duration
and a minimum pulse width on/off duration of 20 ns as specified in the
recommended operating condition table. At initial startup of the HSIN
and LSIN clocking cycle, CB1 needs to be charged from zero. A delay of
nominally 6 switching cycles appears before the gate drive output will
follow the PWM input pulses. Figure 11a and 11b illustrate the gate drive
output switching behavior.
Figure 11a: Maximum and Minimum PWM Input Pulse Width On
or Off duration to refresh internal gate drive bootstrap circuit
Internal
Bootstrap
Gate
Drive
HGoff
RBOOT
MPO
HSG
CB1
Q1
MSO
MS1
SW
VDD
Internal
Bootstrap
Gate
Drive
LGoff
MS1
RDRV
MPO
LSG
CB1
MSO
VDRV
Q2
PGND
Figure 11b: Missing High Side and Low Side Gate pulses at startup
due to initial charging of internal gate drive bootstrap circuit
VBOOT
HSIN or
LSIN
VDD
On duration
Off duration
Maximum On or Off = 200 μs
Minimum On or Off = 20 ns
HSIN
LSIN
HGate
LGate
Missing pulses
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
| 9
eGaN® FET DATASHEET
EPC23103
During HS FET (Q1) or LS FET (Q2) turn-on transitions with hard switching
conditions, the fast di/dt of the HS FET or LS FET coupled with the power
loop inductance (Vpeak = Lpower loop · di/dt) would cause a transient overvoltage spike above VIN or below PGND. The EPC23103 pinouts for
the three power bars (VIN, SW, PGND) are coupled with the design of
optimal layout techniques to achieve minimized power loop inductance.
Together with SW switching rate tuning by RDRV and RBOOT, the overvoltage spikes can be controlled to less than +10 V above rail and -10 V
below ground during hard switching transitions.
The EPC90151 Evaluation Board provides guidelines for PCB layout to
use the EPC23103 in application circuits together with the Gerber files
and Bill of Material. To control SW switching rate and transients, 2.2 Ω
are used for both RDRV and RBOOT for high frequency DC-DC converter
switching around 1 MHz and 4.7 Ω used for 100 kHz motor drive inverter
applications.
Protection Circuits
EPC integrated eGaN FETs are very robust devices when operating within
the recommended operating conditions, output current rating and thermal management techniques as described. Still there are inevitable power
supplies sequencing at startup and brownout conditions where the power
supplies would go out of the recommended range or even a complete loss
of supply. A particular damaging condition could occur when VIN supply
is already fully charged but VDRV is at the startup phase or discharged due
to fault events. In these conditions the output FETs could be commanded
on into high RDS(on) state with low gate drive voltage level. Or worse when
VDRV is completely lost, either the HS FET or LS FET or both can turn-on
due to the output FET leakage current, especially at higher temperature.
This could cause a short circuit across the CIN capacitor.
The EPC23103 integrates protection circuits as shown in Figure 13 (below)
and the Truth Table (page 6).
Figure 13: Simplified circuit diagram of the protection circuits
against low voltage levels or complete loss of supplies
VIN
HSG
HSOFF
VBOOT
VBOOT_POR
Q
A
VOK
Active
turn-off
circuits
Qoff
INV
The Power On Reset (POR) circuit from the high side internal VBOOT supply
would turn on the HS logic path only when the VBOOT bootstrap voltage
rises above a starting threshold voltage level of 3.4 V (typical), and the
output will become active. The output will become inactive after the
VBOOT bootstrap voltage falls 0.15 V below the starting threshold.
The IC features a sequencing protection that prevents the output FETs
from turning on due to leakage when VDD and VBOOT are at a low voltage
level and the input voltage is applied. When VBOOT is low the active turn
off circuit in Figure 13 will be powered by VIN and will activate the Qoff
switch to keep the high side FET (Q1) off. This protection allows user not
to worry about sequencing..
Similar circuit is triggered by the low side loss of VDD supply to turn on
the QOFF switch for the LS FET (Q2). In this case the active turn off circuit is
powered by the SW node voltage.
Logic Inputs
The EPC23103 IC is capable of interfacing to digital and analog controllers
with 3.3 V or 5 V CMOS logic levels. The logic level translator at the frontend
level- shifts the PWM signal, HSIN and LSIN respectively, to internal IC level
to operate the logic, level shifting and gate drive circuits. Logic input
thresholds are 2.4 V minimum to trigger a “high” state and 0.8 V maximum
for a guaranteed “low” state. A hysteresis of 300 mV is built-in to increase
noise margin.
For interfacing with analog controller operating from VCC = 12 V that
outputs a 12 V PWM signal, a resistor network in series should be inserted
to divide the voltage to acceptable VIH level and limit the input current into
the logic input pins HSIN and LSIN which is clamped to the VDD supply by
ESD protection network.
Separate and independent high side (HSIN) and low side (LSIN) logic control
inputs allow external controllers to set fixed or adaptive deadtimes for
optimal operating efficiency. Cross conduction lockout logic commands
both FETs off when logic inputs are both high. Figure 14 shows how the
logic inputs interact with each other. Here the timing diagram applies with
the HS FET (Q1) and LS FET (Q2) in half-bridge configuration and current is in
the positive direction going out of the half-bridge. When HSIN and LSIN are
logic high at same time, both Q1 and Q2 will shut off. A built-in deadtime
of 5 ns is added, after that current then commutates to Q2 in 3rd quadrant
conduction and SW will be clamped at negative VSD voltage of Q2.
Figure 14: EPC23103 Input-to-Output Timing Diagram
HSIN
SW
LSIN
The Power On Reset (POR) circuit from the low side internal VDD supply
would turn off both HS and LS logic path when VDD voltage level is
below the VDD_POR threshold.
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
SW
| 10
Top View
eGaN® FET DATASHEET
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
w2
w1
Bottom View
A
N
Side View
T
D
C
Loaded tape
feed direction
Top View Detail
A
N
C
D
w1
w2
T
Ø330±2
Ø330±2
Ø330±2
Ø330±2
Ø100±2
Ø100±2
Ø100±2
Ø100±2
Ø13.1±0.2
Ø13.1±0.2
Ø13.1±0.2
Ø13.1±0.2
5.6±0.5
5.6±0.5
5.6±0.5
5.6±0.5
8.4+1.5
12.4+1.5
16.4+1.5
24.4+1.5
14.4
18.4
22.4
30,4
2.1±0.5
2.1±0.5
2.1±0.5
2.1±0.5
Bottom View Detail
| 11
EPC23103
Type
8MM
12MM
16MM
24MM
eGaN® FET DATASHEET
EPC23103
10
9
8
11
E
23 PC
C 1
12 YY 03
34 W W
56 E
7 6
4
5
3
13
Pads 1-7, 11, 12 and 13 are IC pins;
Pad 9 is a SW pin ;
Pad 8 is a PGND pin and 10 is a VIN pin
1
7 Nx
eee C
A
2.600
Die size
0.10 Max.
C
// ccc C
Site/date code
Lot code
D
2
12
A
A1
A1
B
b2
(2x)
3.86
Die size
K1 (2x)
9
L1
10
K
aaa C 2x
7
11
6
L
aaa C 2x
MIN
Nominal
MAX
0.60
0.00
0.65
0.02
0.20 Ref
0.25
0.43
0.54
3.50 BSC
5.00 BSC
0.50 BSC
0.60
0.17
0.825
0.20
0.70
0.05
0.55
0.12
0.775
0.15
0.30
0.48
0.59
0.65
0.22
0.875
0.25
5
Note
6
6
SYMBOL
L
L1
L2
aaa
bbb
ccc
ddd
eee
N
ND
NE
Notes
4
3
2
1
12
e
13
b (10x)
K3 (2x)
Bottom View
Side View 1
Dimension (mm)
0.20
0.38
0.49
6
bbb M C A B
ddd M C
A
Top View
A
A1
A3
b
b1
b2
D
E
e
K
K1
K2
K3
L2
K2
(2x)
Seating plane
5.00
A3
SYMBOL
b1
8
E
Exposed
die
A1
A3
Side View 2
Notes:
Dimension (mm)
MIN
Nominal
MAX
0.30
2.85
3.25
0.40
2.95
3.35
0.05
0.10
0.10
0.05
0.08
13
6
4
1, 2
0.50
3.05
3.45
Note
1. Dimensioning and tolerancing conform to
ASME Y14.5-2009
2. All dimensions are in millimeters
3. N is the total number of terminals
4. Dimension b applies to the metallized terminal. If the
terminal has a radius on the other end of it, dimension b
should not be measured in that radius area.
3
5
5
5. ND and NE refer to the number of terminals on each D
and E side respectively.
6. Dimension b applies to the metallized terminal and is
measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has a radius on the other end of it,
dimension b should not be measured in that radius area.
7. Coplanarity applies to the terminals and all the other
bottom surface metallization.
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
| 12
eGaN® FET DATASHEET
2500
1175
850
0
‐825
‐1325
‐1175
‐1675
‐ 2400
‐ 2425
‐2250
COPPER (units in μm)
EPC23103
1750
1650
780
1400
245 (8x)
575
75
0
990
‐425
795 (8x)
3890
‐925
1255
(2x)
‐1400
‐1650
‐ 1675
680
3210 (2x)
1030
270
1750
1550
1425
1310
270
505
2500
1175
850
0
‐825
‐1325
‐1175
‐1675
‐2175
‐1825
‐2300
SOLDER MASK (units in μm)
505
575
270 (8x)
490 (8x)
75
0
384
3309
750 (2x)
858
2941 (2x)
‐925
530 (2x)
‐1310
‐1425
‐1550
270
270
505
270
(12x)
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
‐425
230
(10x)
| 13
eGaN® FET DATASHEET
2500
1035
822
0
‐825
‐1325
‐1175
‐1675
‐2300
‐2255
‐2083
PASTE (units in μm)
EPC23103
1750
1550
1470
1375
188
263
575
125 (8x)
275 (8x)
75
0
215
3140
‐425
‐925
480 (2x)
‐1375
‐1480
‐1550
150
645
2500
1040
822
0
‐825
‐1325
‐1175
‐1675
‐2300
‐2175
‐1825
PACKAGE (units in μm)
2830 (2x)
1750
1550
1425
1310
250
450
575
250 (8x)
400 (8x)
75
0
430
‐425
2775
250
710 (2x)
‐925
540 (2x)
‐1310
‐1425
‐1550
450
800
250
250
(12x)
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
250
(10x)
2950 (2x)
| 14
eGaN® FET DATASHEET
EPC23103
Errata Sheet
STATUS
VERSION
DATE
REMARK
ENGRT
1.1
12/09/2022
The following features and parameters do not meet the datasheet
description and specifications:
1) The maximum operating VIN voltage should not exceed 64 V
2) The maximum transient voltage at the output switch node SW,
should not exceed 70 V. Recommend to use at least 4.7 Ω for
RBOOT and RDRV to module the over-voltage spike above VIN rail
and below PGND to less than 10 V.
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products
herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of
any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 |
Information subject to change
without notice.
Revisied May, 2023
| 15
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