EPC8002

eGaN® FET DATASHEET EPC8002 EPC8002 – Enhancement Mode Power Transistor VDS , 65 V RDS(on) , 480 mΩ ID , 2 A D G EFFICIENT POWER CONVERSION HAL S Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings PARAMETER VALUE UNIT Drain-to-Source Voltage (Continuous) 65 Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 78 Continuous (TA = 25°C, RθJA = 36°C/W) 2 Pulsed (25°C, TPULSE = 300 µs) 2 Gate-to-Source Voltage 6 Gate-to-Source Voltage –4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 VDS ID VGS V A V °C Thermal Characteristics PARAMETER TYP RθJC Thermal Resistance, Junction-to-Case 8.2 RθJB Thermal Resistance, Junction-to-Board 16 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 82 UNIT EPC8002 eGaN FETs are supplied only in passivated die form with solder bars Die Size: 2.1 mm x 0.85 mm Applications • Ultra High Speed DC-DC Conversion • RF Envelope Tracking • Wireless Power Transfer • Game Console and Industrial Movement Sensing (Lidar) Benefits • Ultra High Efficiency • Ultra Low RDS(on) • Ultra Low QG • Ultra Small Footprint °C/W Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details PARAMETER Static Characteristics (TJ= 25°C unless otherwise stated) TEST CONDITIONS TYP MAX UNIT VDS = 52 V, VGS = 0 V 20 100 µA Gate-to-Source Forward Leakage VGS = 5 V 0.1 1 mA Gate-to-Source Reverse Leakage VGS = -4 V 20 100 µA BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 µA IDSS Drain-Source Leakage IGSS VDS = VGS, ID = 0.1 mA MIN 65 0.8 V VGS(TH) Gate Threshold Voltage 1.4 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.5 A 380 480 mΩ VSD Source-Drain Forward Voltage IS = 0.4 A, VGS = 0 V 2.6 V Specifications are with substrate connected to source where applicable. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 1 eGaN® FET DATASHEET EPC8002 Dynamic Characteristics (TJ= 25˚C unless otherwise stated) PARAMETER TEST CONDITIONS CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance COSS(ER) Effective Output Capacitance, Energy Related (Note 2) COSS(TR) Effective Output Capacitance, Time Related (Note 3) RG Gate Resistance QG Total Gate Charge QGS Gate-to-Source Charge MIN VDS = 32.5 V, VGS = 0 V TYP MAX 20 24 0.12 0.18 6.7 10 UNIT pF 8.9 VDS = 0 to 32.5 V, VGS = 0 V 10 0.3 VDS = 32.5 V, VGS = 5 V, ID = 0.5 A Ω 133 167 57 VDS = 32.5 V, ID = 0.5 A QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge 15 26 46 VDS = 32.5 V, VGS = 0 V 334 pC 500 0 Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics 2.0 2.0 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V V DS = 3 V 1.5 ID– Drain Current (A) ID– Drain Current (A) 1.5 25˚C 125˚C 1.0 1.0 0.5 0.5 0 0 0.5 1.0 1.5 2.0 2.5 0 0.5 3.0 1.0 1.5 Figure 3: RDS(on) vs VGS for Various Drain Currents 3.0 3.5 4.0 4.5 5.0 Figure 4: RDS(on) vs VGS for Various Temperatures 1500 RDS(on) – Drain-to-Source Resistance (mΩ) 1500 RDS(on)– Drain-to-Source Resistance (mΩ) 2.5 VGS– Gate-to-Source Voltage (V) VDS– Drain-to-Source Voltage (V) ID= 0.5 A 1200 ID= 1.0 A ID= 1.5 A ID= 2.0 A 900 600 300 0 2.5 2.0 3.0 3.5 4.0 4.5 5.0 VGS– Gate-to-Source Voltage (V) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | 25˚C 125˚C 1200 ID = 0.5 A 900 600 300 0 2.5 3.0 3.5 4.0 4.5 5.0 VGS – Gate-to-Source Voltage (V) | 2 eGaN® FET DATASHEET EPC8002 Figure 5A: Capacitance (Log Scale) Figure 5: Capacitance (Linear Scale) 100 25 10 C – Capacitance (pF) C – Capacitance (pF) 20 COSS = CGD + CSD CISS = CGD + CGS 15 CRSS = CGD 10 COSS = CGD + CSD CISS = CGD + CGS 1 CRSS = CGD 0.1 5 0 0 10 20 30 40 50 0.01 60 0 10 20 ID= 0.5 A VDS = 32.5 V 4 3 2 1 0 0.05 0.1 1.0 0.5 0 0.15 25˚C 125˚C VGS = 0 V 1.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSD – Source-to-Drain Voltage (V) QG– Gate Charge (nC) Figure 9: Normalized Threshold Voltage vs Temperature Figure 8: Normalized On-State Resistance vs Temperature 1.4 2.2 ID = 0.5 A VGS = 5 V ID = 0.1 mA 1.3 Normalized Threshold Voltage (V) Normalized On-State Resistance – RDS(on) 60 2.0 ISD – Source-to-Drain Current (A) VGS – Gate-to-Source Voltage (V) 5 1.8 1.6 1.4 1.2 1.0 0.8 50 Figure 7: Reverse Drain-Source Characteristics Figure 6: Gate Charge 2.0 40 VDS– Drain-to-Source Voltage (V) VDS– Drain-to-Source Voltage (V) 0 30 1.2 1.1 1.0 0.9 0.8 0.7 0 25 50 75 100 125 150 TJ – Junction Temperature (°C) EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | 0.6 0 25 50 75 100 125 150 TJ– Junction Temperature (°C) | 3 eGaN® FET DATASHEET EPC8002 Figure 10: Gate Leakage Current Figure 11: Smith Chart 0.30 1.0 1.4 1.2 0.4 3. 0 S11 – Gate Reflection S22 – Drain Reflection 0.5 0.15 2.0 1.8 0.6 1.6 0.7 0.8 0.20 0.9 25˚C 125˚C 0.25 0.3 4.0 5.0 0.2 0.10 6.0 8.0 10 0.1 IG – Gate Current (mA) S-Parameter Characteristics VGSQ = 1.17 V, VDSQ = 30 V, IDQ = 0.2 A Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω 0.05 10 3.0 5.0 4.0 1.8 2.0 1.6 1.2 1.4 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.2 0.3 0 0.1 20 20 0.1 8.0 10 6.0 0.2 5.0 RF Café 2002 0.3 6 0 5 3. 4 0.4 1.6 1.4 0.7 0.6 1.8 2.0 0.5 VGS – Gate-to-Source Voltage (V) 1.2 3 1.0 2 0.9 1 0.8 0 4.0 0 All measurements were done with substrate shortened to source. Figure 13: Device Reflection Figure 12: Gain Chart 45 1.6 1.4 Gmax 35 1.2 30 1.0 25 0.8 20 0.6 15 0.4 10 0.2 5 0 Figure 14: Taper and Reference Plane details – Device Connection Micro-Strip design: 2-layer ½ oz (17.5 µm) thick copper 30 mil thick RO4350 substrate Gate (ZGS) Drain (ZDS) [MHz] [Ω] [Ω] 200 3.09 - j29.97 63.13 - j71.32 500 2.20 - j11.92 15.96 -j46.65 1000 1.14 - j4.46 3.35 - j23.47 1200 0.95 - j2.76 1.91 - j18.52 1500 0.87 - j0.55 1.66 - j12.66 2000 1.09 + j2.61 2.28 - j6.12 2400 1.44 + j4.87 4.35 - j2.80 3000 2.36 + j8.79 6.41 + j0.69 914 355 All dimensions in µm 914 1621 Frequency 271 Frequency (MHz) -0.2 1000 271 100 Z GS 1621 0 Z DS 1000 Amplitude (dB) 40 Device Outline S-Parameter Table - Download S-parameter files at www.epc-co.com EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | Gate Circuit Reference Plane 149 Drain Circuit Reference Plane | 4 eGaN® FET DATASHEET EPC8002 1 0.1 Figure 16: Safe Operating Area Junction-to-Board Duty Factors: 0.5 0.2 0.1 0.05 1 T 0.02 0.01 0.01 P DM Notes: Duty Factor = tp/T Peak TJ = PDM x ZθJB x RθJB + TB Single Pulse 0.001 10-5 tp 10-4 10-3 10-2 10-1 1 10 Limited by RDS(on) ID - Drain Current (A) ZθJB Normalized Thermal Impedance Figure 15: Transient Thermal Response Curves Pulse Width 100 ms 10 ms 1 ms 100 µs 10 µs tp– Rectangular Pulse Duration (s) ZθJC Normalized Thermal Impedance 1 0.1 0.1 Junction-to-Case Duty Factors: 0.5 0.1 1 10 VDS – Drain Voltage (V) 100 0.2 0.1 0.05 T P DM 0.02 0.01 0.01 Notes: Duty Factor = tp/T Peak TJ = PDM x ZθJC x RθJC + TC Single Pulse 0.001 10-5 tp 10-4 10-3 10-2 10-1 1 10 tp– Rectangular Pulse Duration (s) TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7”reel d e f Loaded Tape Feed Direction g 7” reel Die orientation dot b 8002 YYYY ZZZZ a c Die is placed into pocket solder bump side down (face side down) EPC8002 (note 1) Dimension (mm) target min a b c (see note) d e f (see note) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 max 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Gate pad bump is under this corner Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 8002 Die orientation dot YYYY ZZZZ Gate Pad bump is under this corner EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | Part Number EPC8002 Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 8002 YYYY ZZZZ | 5 eGaN® FET DATASHEET EPC8002 DIE OUTLINE A d e e i X2 5 2 j 1 C B 3 Dim f 4 6 h i (685) g x2 100 +/- 20 Side View 815 Max Solder Bar View Seating Plane A B C d e f g h i j Min 2020 820 555 400 600 200 175 425 175 400 Micrometers Nominal 2050 850 580 400 600 225 200 450 200 400 Max 2080 880 605 400 600 250 225 475 225 400 Pad no. 1 is Gate Pad no. 2 is Source Return for Gate Driver Pad no. 3 and 5 are Source Pad no. 4 is Drain Pad no. 6 is Substrate* *Substrate pin should be connected to Source RECOMMENDED LAND PATTERN (measurements in µm) 2050 600 The land pattern is solder mask defined. Solder mask opening is 5 µm smaller per side than bump. 4 6 3 5 400 190 850 600 2 190 1 570 400 190 Pad no. 1 is Gate Pad no. 2 is Source Return for Gate Driver Pad no. 3 and 5 are Source Pad no. 4 is Drain Pad no. 6 is Substrate* *Substrate pin should be connected to Source 440 RECOMMENDED STENCIL DRAWING (measurements in µm) 272 3 325 200 245 230 6 450 850 200 R60 2 4 200 1 592 250 2050 5 275 Blue = bump, Gray = stencil Recommended stencil should be 4 mil (100 μm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | Information subject to change without notice. Revised April, 2021 | 6