eGaN® FET DATASHEET
EPC2001C
EPC2001C – Enhancement Mode Power Transistor
VDS , 100 V
RDS(on) , 7 mΩ
ID , 36 A
D
EFFICIENT POWER CONVERSION
G
S
HAL
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
Maximum Ratings
PARAMETER
VDS
ID
VALUE
Drain-to-Source Voltage (Continuous)
100
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
120
Continuous (TA = 25°C, RθJA = 7.3)
36
Pulsed (25°C, TPULSE = 300 µs)
150
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
TJ
Operating Temperature
-40 to 150
TSTG
Storage Temperature
-40 to 150
VGS
UNIT
V
A
V
°C
Thermal Characteristics
PARAMETER
TYP
RθJC
Thermal Resistance, Junction-to-Case
1
RθJB
Thermal Resistance, Junction-to-Board
2
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
54
EPC2001C eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• High-Frequency DC-DC Conversion
• Industrial Automation
• Synchronous Rectification
• Class-D Audio
• Low Inductance Motor Drives
Benefits
• Ultra High Efficiency
• Ultra Low Switching and Conduction Losses
• Zero QRR
• Ultra Small Footprint
UNIT
°C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
100
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 300 μA
IDSS
Drain-Source Leakage
IGSS
TYP
MAX
UNIT
V
VGS = 0 V, VDS = 80 V
100
250
Gate-to-Source Forward Leakage
VGS = 5 V
1
5
Gate-to-Source Reverse Leakage
VGS = -4 V
0.1
0.25
µA
mA
VGS(TH)
Gate Threshold Voltage
VDS = VGS, ID = 5 mA
1.4
2.5
V
RDS(on)
Drain-Source On Resistance
VGS = 5 V, ID = 25 A
5.6
7
mΩ
VSD
Source-Drain Forward Voltage
IS = 0.5 A, VGS = 0 V
1.7
0.8
V
All measurements were done with substrate connected to source.
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| 1
eGaN® FET DATASHEET
EPC2001C
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER
CISS
Input Capacitance
COSS
Output Capacitance
TEST CONDITIONS
MIN
VDS = 50 V, VGS = 0 V
TYP
MAX
770
900
430
650
15
CRSS
Reverse Transfer Capacitance
10
RG
Gate Resistance
0.3
QG
Total Gate Charge
VDS = 50 V, VGS = 5 V, ID = 25 A
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
UNIT
pF
Ω
7.5
9
2.4
VDS = 50 V, ID = 25 A
1.2
2
nC
1.6
VDS = 50 V, VGS = 0 V
31
45
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
Figure 1: Typical Output Characteristics at 25°C
Figure 2: Transfer Characteristics
150
150
90
60
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
30
0
0
25
RDS(on) – Drain to Source Resistance (mΩ)
ID – Drain Current (A)
120
0.5
1
1.5
2
VDS – Drain-to-Source Voltage (V)
2.5
25
ID = 10 A
ID = 20 A
ID = 40 A
ID = 80 A
15
10
5
0
2
2.5
3
3.5
4
VGS – Gate-to-Source Voltage (V)
60
0
3
Figure 3: RDS(on) vs. VGS for Various Currents
20
90
30
RDS(on) – Drain to Source Resistance (mΩ)
ID – Drain Current (A)
120
25°C
125°C
VDS = 3 V
4.5
5
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0.5
1
1.5
2
2.5
3
3.5
VGS – Gate-to-Source Voltage (V)
4
4.5
5
Figure 4: RDS(on) vs. VGS for Various Temperatures
25˚C
125˚C
20
ID = 25 A
15
10
5
0
2
2.5
3
3.5
4
VGS – Gate-to-Source Voltage (V)
4.5
5
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eGaN® FET DATASHEET
EPC2001C
Figure 5a: Capacitance (Linear Scale)
1.2
Figure 5b: Capacitance (Log Scale)
0.8
Capacitance (nF)
Capacitance (nF)
1
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
1
0.6
0.4
0.1
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0.01
0.2
0
0
20
40
60
80
100
0.001
0
20
40
VDS – Drain-to-Source Voltage (V)
Figure 6: Gate Charge
72
5
ID = 25 A
VDS = 50 V
4
3.5
3
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
QG – Gate Charge (nC)
7
48
36
24
12
1.5
2
2.5
3
3.5
4
4.5
5
Figure 9: Normalized Threshold Voltage vs. Temperature
1.4
I D = 25 A
VGS = 5 V
1.3
Normalized Threshold Voltage
Normalized On-State Resistance – RDS(on)
1
VSD – Source-to-Drain Voltage (V)
Figure 8: Normalized On Resistance vs. Temperature
1.6
1.4
1.2
1
0.8
0.6
100
25˚C
125˚C
VGS = 0 V
0.5
8
2
1.8
80
Figure 7: Reverse Drain-Source Characteristics
60
ISD – Source to Drain Current (A)
VGS – Gate to Source Voltage (V)
4.5
60
VDS – Drain-to-Source Voltage (V)
I D = 5 mA
1.2
1.1
1
0.9
0.8
0.7
0
25
50
75
100
125
TJ – Junction Temperature ( ˚C )
150
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 |
0.6
0
25
50
75
100
125
150
TJ – Junction Temperature ( ˚C )
| 3
eGaN® FET DATASHEET
EPC2001C
25
Figure 10: Gate Current
25˚C
125˚C
IG – Gate Current (mA)
20
15
10
5
0
0
1
2
3
4
5
6
VGS – Gate-to-Source Voltage (V)
Figure 11: Transient Thermal Response Curves
Junction-to-Board
ZθJB, Normalized Thermal Impedance
1
0.1
Duty Factors:
0.5
0.1
0.05
T
PDM
0.02
0.01 0.01
Single Pulse
0.001
10-5
tp
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJB x RθJB + TB
10-4
10-3
10-2
tp - Rectangular Pulse Duration [s]
10-1
1
10
Junction-to-Case
ZθC, Normalized Thermal Impedance
1
Duty Factors:
0.5
0.2
0.1 0.1
0.05
0.02
0.01
0.01
T
PDM
0.001
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
0.0001
10-5
tp
10-4
10-3
10-2
tp - Rectangular Pulse Duration [s]
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 |
10-1
1
10
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eGaN® FET DATASHEET
EPC2001C
Figure 12: Safe Operating Area
I D- Drain Current (A)
100
10
limited by RDS(on)
Pulse Width
100 ms
10 ms
1 ms
100 us
1
0.1
0.1
1
10
100
VDS - Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
TAPE AND REEL CONFIGURATION
4 mm pitch, 12 mm wide tape on 7” reel
d
7” reel
e
f
g
Loaded Tape Feed Direction
Die
orientation
dot
b
2001
YYYY
ZZZZ
a
c
DIM
EPC2001 (Note 1)
a
b
c (Note 2)
d
e
f (Note 2)
g
Dimension (mm)
Target MIN MAX
12.00 11.90 12.30
1.75
1.65 1.85
5.50
5.45 5.55
4.00
3.90 4.10
4.00
3.90 4.10
2.00
1.95 2.05
1.50
1.50 1.60
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
DIE MARKINGS
2001
Die orientation dot
Gate Pad solder bar
is under this corner
YYYY
ZZZZ
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 |
Part
Number
EPC2001C
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
2001
YYYY
ZZZZ
| 5
eGaN® FET DATASHEET
EPC2001C
A
DIE OUTLINE
f
d
x2
Solder Bar View
f
x9
DIM
A
B
c
d
e
f
g
c
3
4
5
6
7
8
9
10
11
B
2
1
g
Seating Plane
4105
4
5
6
4135
1662
1385
583
265
205
400
7
*Substrate pin should be connected to Source
Pad no. 1 is Gate;
Pads no. 3, 5, 7, 9, 11 are Drain;
Pads no. 4, 6, 8, 10 are Source;
Pad no. 2 is Substrate.*
8
9
10
11
1635
802
3
MAX
4105
1635
1382
580
250
200
400
The land pattern is solder mask defined.
180
x9
1
1362
560
x2
(measurements in µm)
180
Nominal
100 +/- 20
(685)
Side View
RECOMMENDED
LAND PATTERN
MIN
4075
1602
1379
577
235
195
400
Pad no. 1 is Gate;
Pads no. 3, 5, 7, 9, 11 are Drain;
Pads no. 4, 6, 8, 10 are Source;
Pad no. 2 is Substrate.*
g
x8
815 Max
e
MICROMETERS
*Substrate pin should be connected to Source
2
400
RECOMMENDED
STENCIL DRAWING
400
x8
4105
180
180
x9
(units in µm)
Recommended stencil should be 4 mil (100 μm)
thick, must be laser cut , opening per drawing.
The corner has a radius of R60.
3
4
5
6
7
8
9
10
11
1635
1
1362
560
x2
R60
2
400
400
x8
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 |
Intended for use with SAC305 Type 3 solder,
reference 88.5% metals content.
Additional assembly resources available at
https://www.epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
Information subject to
change without notice.
Revised April, 2020
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