EPC9004

Figure 4: Waveforms for VIN = 150 V to 5 V/2 A (100kHz) Buck converter CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage NOTE. The EPC9004 development board does not have any current or thermal protection on board. Figure 3: Proper Measurement of Switch Node – OUT Minimize loop EFFICIENT POWER CONVERSION EPC The EPC9004 development board showcases the EPC1012 eGaN FET. Although the electrical performance surpasses that for traditional Si devices, their relatively smaller size does magnify the thermal management requirements. The EPC9004 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C. Place probe in large via at OUT Ground probe against TP3 THERMAL CONSIDERATIONS NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. EFFICIENT POWER CONVERSION Figure 1: Block Diagram of EPC9004 Development Board PWM Input Gate Drive Regulator OUT VIN Gate Drive Supply – VIN V Half-Bridge with Bypass Switch Node + IIN + Gate Drive Supply (Note Polarity) VDD Supply – 7 V – 12 V VIN Supply +