Development Board
EPC9004C
Quick Start Guide
200 V Half-bridge with Gate Drive, Using EPC2012C
Revision 4.1
QUICK START GUIDE
EPC9004C
DESCRIPTION
Table 1: Performance Summary (TA = 25°C) EPC9004C
Symbol
The EPC9004C is a half bridge development board with onboard gate
driver, featuring the 200 V rated EPC2012C GaN field effect transistor (FET).
The purpose of this development board is to simplify the evaluation
process of the EPC2012C by including all the critical components on a
single board that can be easily connected into the majority of existing
converter topologies.
PWM Logic Input
Voltage Threshold (3)
VEN
Enable Logic Input
Voltage Threshold (3)
PWM ‘High’ State
Input Pulse Width
PWM ‘Low’ State
Input Pulse Width (4)
EN
EN
Hin
Lin
DT
Logic and
dead-time
adjust
GND
* Default
- Independent PWM
- No-X conduction protection
*
LDO
Logic
V
160
Input ‘High’
Input ‘Low’
Input ‘High’
Input ‘Low’
VPWM rise and fall
time < 10ns
VPWM rise and fall
time < 10ns
3.5
0
3.5
0
50
2
A
5.5
1.5
5.5
1.5
V
V
ns
200
Back view
Q1
LDO
12
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing
must be kept under 200 V for EPC2012C.
(2) Maximum current depends on die temperature – actual maximum current is affected by
switching frequency, bus voltage and thermal cooling.
(3) When using the on board logic buffers, refer to the NCP51820 datasheet when bypassing the logic buffers.
(4) Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Gate driver
5V
Min Nominal Max Units
10
DBTST
Gate drive
regulator
PWM2
VPWM
EPC9004C development board
VDD
PWM1
IOUT
VIN
For more information on EPC2012C please refer to the datasheet
available from EPC at www.epc-co.com. The datasheet should be read in
conjunction with this quick start guide.
Front view
Conditions
Gate Drive Input
Supply Range
Bus Input Voltage
Range(1)
Switch Node Output
Current (2)
VDD
The EPC9004C evaluation board measures 2” x 2” and contains two
EPC2012C GaN FETs in a half bridge configuration. The EPC9004C features
the On-Semi NCP51820 gate driver. The board also contains all critical
components and the layout supports optimal switching performance.
There are also various probe points to facilitate simple waveform
measurement and efficiency calculation. A block diagram of the circuit
is given in figure 1.
Parameter
VIN
CBypass
LDO
L1
Level
shift
Out
Q2
LDO
Level
shift
Cout
PGND
GND jumper
Figure 1: Block diagram of EPC9004C development board
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EPC9004C
QUICK START PROCEDURE
The EPC9004C development board is easy to set up as a buck or boost
converter to evaluate the performance of two EPC2012C eGaN FETs.
In addition to the deadtime features of the NCP51820 gate driver, this board
includes a dead-time generating circuit that adds a delay from when the
gate signal of one FET is commanded to turn off, to when the gate signal
of the other FET is commanded to turn on. In the default configuration, the
NCP51820 gate driver is set mode D (no-dead time, no-cross conduction
protection - refer to datasheet for NCP51820) and the dead time circuit thus
ensures that both the high and low side FETs will not be turned on at the
same time thus preventing a shoot-through condition. The dead-time and/
or polarity changing circuits can be utilized or bypassed for added versatility.
Single input
Buck
PWM2
(a)
(b)
(c)
Figure 2: Input mode selection on J630
There are two PWM signal input ports on the board, PWM1 and PWM2. Both
input ports are used as inputs in dual-input mode where PWM1 connects to
the upper FET and PWM2 connects to the lower FET. The PWM1 input port
is used as the input in single-input mode where the circuit will generate the
required complementary PWM for the FETs. The input mode is set by choosing
the appropriate jumper positions for J630 (mode selection) as shown in figure
2(a) for a single-input buck converter (blue jumper across pins 1 & 2 of J630),
(b) for a single-input boost converter (blue jumpers across pins 3 & 4 of J630),
and (c) for a dual-input operation (blue jumpers across pins 5 & 6 of J630).
Upper FET turn on delay
Lower FET turn on delay
v
Note: In dual mode there is no shoot-through protection as both gate
signals can be set high at the same time. Refer to the NCP51820 datasheet
for details on setting the dead time using R84 and R86.
50%
Dead-time is defined as the time between when one FET turns off and the
other FET turns on, and for this board is referenced to the input of the gate
driver. The dead-time can be set to a specific value where resistor R620
delays the turn on of the upper FET and resistor R625 delays the turn on of
the lower FET as illustrated in figure 3.
The required resistance for the desired dead-time setting can be read off
the graph in figure 4. An example for 10 ns dead-time setting shows that
a 120 Ω resistor is needed.
50%
50%
t
Lower FET
turn on delay
Upper FET
turn on delay
Figure 3: Definition of dead-time between the upper-FET gate signal (DTQup)
and the lower-FET gate signal (DTQlow)
Resistance (Ω)
Bypass settings
Full Bypass
50%
DTQlow
0
Note: This is the default deadtime and resistor value installed. A minimum
dead-time of is 5 ns and maximum of 15 ns is recommended.
Both the polarity changer and the deadtime circuits can be bypassed using
the jumper settings on J640 (Bypass), for direct access to the gate driver
input. There are three bypass options: 1) No bypass, 2) Dead-time bypass,
3) Full bypass. The jumper positions for J640 for all three bypass options are
shown in figure 5.
Deadtime
Deadtime
DTQup
Dead-time settings
Bypass deadtime
Dual input
PWM1
Single/dual PWM signal input settings
No bypass
Single input
Boost
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
R(Ω) = 13.5 ∙ DT(ns) − 14
5
6
7
8
9
10
11
12
13
14
15
Dead-time (ns)
Figure 4: The required resistance values for R620 or R625 as a
function of desired dead-time
(a)
(b)
(c)
Figure 5: Bypass mode Jumper settings for J640
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EPC9004C
In no-bypass mode, figure 5(a) (red jumper across pins 5 & 6 of J640),
both the on-board polarity and dead-time circuits are fully utilized.
In dead-time bypass mode, figure 5(b) (red jumpers across pins 3
& 4 of J640), only the on-board polarity changer circuit is utilized,
effectively bypassing the dead-time circuit.
In full bypass mode, Figure 5(c) (red jumper across pins 1 & 2 of J640),
the inputs to the gate driver are directly connected to the PWM1 and
PWM2 pins and the on-board polarity and dead-time circuits are not
utilized. Furthermore, the dead-time settings for the NCP51820 gate
driver can now be utilized by placing the NCP51820 gate driver in either
Mode B or C. This can be done by changing the values of or installing
the following components: R84, R86 and C87. Refer to the NCP51820
datasheet for details.
Bypass mode warnings
• It is important to provide the correct PWM signals that includes
dead-time and polarity for either buck or boost operation when
making use of bypass modes.
• When operating in full bypass mode, the input signal
specifications revert to that of the NCP51820 gate driver IC. Refer to
the NCP51820 datasheet for details.
• It is not recommended to utilize both on board and gate driver
dead-time settings simultaneously.datasheet for details.
Enable Function
An enable input is available, shown in figure 1, that can be used to turn off
both FETs regardless of operating mode. Refer to the NCP51820 datasheet for
additional details. If this function is not needed, then leave the connection
(J81) empty and the gate driver will be enabled (default setting). Figure 6
shows three configurations that can be used for the enable function:
a) Using a shorting jumper or switch. When the enable terminals (J81) are
shorted together, the gate driver will be disabled. When the enable
terminals (J81) are open, then the gate driver will be enabled.
b) Using a transistor as a switch. This configuration is similar to (a) except
that an open collector/drain transistor, such as a MOSFET or BJT, is used
instead of a mechanical switch. The transistor must be rated to at least
10 V and be able to carry at least 20 mA. Note that pin 1 of the enable
function (J81) is connected to the ground of the development board and
hence the corresponding drive voltage/current needs to be referenced
to the same ground.
c) Using a voltage source to drive the enable function. In this configuration
a voltage source directly drives the enable/disable function. When the
applied voltage exceeds 3.5 V then the gate driver will be enabled. When
the drive voltage falls below 1.5 V then the gate driver will be disabled.
The voltage source must be capable of sinking and sourcing at least
20 mA. Warning: In this configuration do not exceed the input voltage
ratings of the gate driver. Refer to the NCP51820 datasheet for additional
details.
Warning
Do not exceed
max. voltages
Close to
disable
Power to
disable
5 V = Enable
0 V = Disable
GND
GND
Figure 6: Enable function configurations
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EPC9004C
Buck converter configuration
Note: It is important to provide the correct PWM signals that includes
dead-time and polarity when operating in bypass mode.
Once the input source, dead-time settings and bypass config-urations
have be chosen and set, then the boards can be operated.
4. With power off, connect the input PWM control signal to PWM1
and/or PWM2 according to the input mode setting chosen and
ground return to any of GND J80 pins indicated on the bottom side
of the board.
5. Turn on the gate drive supply – make sure the supply is set between
10 V and 15 V.
Must be in
“No Bypass”
position
PWM1
(default)
+
12 VDC
VDD supply
(Note
polarity)
Switch-node
output
DC load
(a)
Optional antiparallel diodes
Output
Capacitor
Buck
Inductor
VMain
supply
(Note
polarity)
Enable
All positions
permitted
6. Turn on the controller / PWM input source.
7. Making sure the initial input supply voltage is 0 V, turn on the
power and slowly increase the voltage to the required value (do
not exceed the absolute maximum voltage). Probe switch-node
to see switching operation.
PWM2
Lower
FET
9. For shutdown, please follow steps in reverse.
160 VDCmax
Jumper positions
for single-input
buck mode
PWM1
Upper
FET
8. Once operational, adjust the PWM control, bus voltage, and load
within the operating range and observe the output switching
behavior, efficiency, and other parameters.
VMain
supply
(Note
polarity)
+
3. With power off, connect the gate drive supply to VDD (J90, Pin-2)
and ground return to GND (J90, Pin-1 indicated on the bottom side
of the board).
Buck
Inductor
Enable
1. With power off, connect the input power supply bus to VIN and
ground / return to GND.
2. With power off, connect the switch node (SW) of the half bridge
to your circuit as required (half bridge configuration). Or use the
provided pads for inductor (L1) and output capacitors (Cout), as
shown in figure 7.
Output
Capacitor
+
To select Dual Input Buck Mode, the bypass jumper J640 may be
configured to any of the valid settings, the dual-input mode J630 must
be selected as shown in figure 7(b).
Optional antiparallel diodes
+
To select Single Input Buck Mode, the bypass jumper J640 must be
set to the no-bypass mode, the buck mode J630 must be selected as
shown in figure 7(a).
12 VDC
VDD supply
(Note
polarity)
+
To operate the board as a buck converter, either a single or dual PWM
inputs can be chosen using the appropriate jumper settings on J630
(mode).
160 VDCmax
+
+
Jumper positions
for dual-input
buck mode
DC load
(b)
Figure 7: (a) Single-PWM input buck converter (b) Dual-PWM input buck converter
configurations showing the supply, anti-parallel diodes, output capacitor,
inductor, PWM, and load connections with corresponding jumper positions.
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EPC9004C
Boost Converter configuration
Warning: Never operate the boost converter mode without a
load, as the output voltage can increase beyond the maximum
ratings.
To select Single Input Boost Mode, the bypass jumper J640 must
be set to the no-bypass mode, the boost mode J630 must be
selected as shown in figure 8(a).
To select Dual Input Boost Mode, the bypass jumper J640 may be
configured to any of the valid settings, the dual-input mode J630
must be selected as shown in figure 8(b).
Note: It is important to provide the correct PWM signals that
includes dead-time and polarity when operating in bypass mode.
5. Turn on the gate drive supply – make sure the supply is between
10 V and 15 V.
6. Turn on the controller / PWM input source.
7. Making sure the output is not open circuit, and the input
supply voltage is initially 0 V, turn on the power and slowly
increase the voltage to the required value (do not exceed
the absolute maximum voltage). Probe switch-node to see
switching operation.
8. Once operational, adjust the PWM control, bus voltage, and load
within the operating range and observe the output switching
behavior, efficiency, and other parameters. Observe device
temperature for operational limits.
DC load
160 VDCmax
PWM1
(default)
+
Jumper positions
for single-input
boost mode
12 VDC
+
VMain supply
(Note polarity)
(a)
Optional antiparallel diodes
Input
Capacitor
Boost
Inductor
+
4. With power off, connect the input PWM control signal to PWM1
and/or PWM2 according to the input mode setting chosen and
ground return to any of GND J2 pins indicated on the bottom
side of the board.
Boost
Inductor
Must be in
“No Bypass”
position
1. The inductor (L1) and input capacitors (labeled as Cout) can
either be soldered onto the board, as shown in figure 8, or
provided off board. Anti-parallel diodes can also be installed
using the additional pads on the right side of the FETs.
3. With power off, connect the gate drive supply to VDD (J90, Pin-1)
and ground return to GND (J90, Pin-2 indicated on the bottom
side of the board).
Input
Capacitor
VDD supply
(Note polarity)
Once the input source, dead-time settings and bypass configurations have be chosen and set, then the boards can be operated.
2. With power off, connect the input power supply bus to VOUT
and ground / return to GND, or externally across the capacitor
if the inductor L1 and Cout are provided externally. Connect the
output voltage (labeled as VIN) to your circuit as required, e.g.,
resistive load.
Optional antiparallel diodes
+
To operate the board as a boost converter, either a single or dual
PWM inputs can be chosen using the appropriate jumper settings
on J630 (mode).
12 VDC
VDD supply
(Note polarity)
DC load
160 VDCmax
All positions
permitted
PWM1
Upper
FET
PWM2
Lower
FET
+
+
+
Jumper positions
for dual-input
boost mode
VMain supply
(Note polarity)
(b)
Figure 8: (a) Single-PWM input boost converter (b) Dual-PWM input boost
converter configurations showing the supply, inductor, anti-parallel diodes, output
capacitor, PWM, and load connections with corresponding jumper settings.
9. For shutdown, please follow steps in reverse.
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EPC9004C
MEASUREMENT CONSIDERATIONS
Measurement connections are shown in figure 9.
Figure 10 shows an actual switch-node voltage
measurement when operating the board as a buck
converter.
When measuring the switch node voltage containing
high-frequency content, care must be taken to provide
an accurate high-speed measurement. An optional
two pin header (J33) and an MMCX connector (J32)
are provided for switch-node measurement.
A differential probe is recommended for measuring
the high-side bootstrap voltage. IsoVu probes from
Tektronix has mating MMCX connector.
For regular passive voltage probes (e.g. TPP1000)
measuring switch node using MMCX connector,
probe adaptor is available. PN: 206-0663-xx.
Voltage measurement:
Input voltage for Buck,
Output voltage for Boost
(HIGH VOLTAGE!)
+V
HIGH VOLTAGE
Upper FET Gate
Voltage MMCX
(HIGH VOLTAGE!)
HIGH VOLTAGE
Lower FET
Gate Voltage
Switch-node
oscilloscope probe
Ground oscilloscope probe
HIGH VOLTAGE
Voltage measurement:
Input voltage for Boost,
Output voltage for Buck
(HIGH VOLTAGE!)
V
+
(a)
Note:
PCB#: B5219
For information about measurement techniques, the
EPC website offers: “AN023 Accurately Measuring
High Speed GaN Transistors” and the How to
GaN educational video series, including: HTG09Measurement
HIGH VOLTAGE
Switch-node oscilloscope
probe (HIGH VOLTAGE!)
Ground oscilloscope probe
Switch-node MMCX
(HIGH VOLTAGE!)
HIGH VOLTAGE
(b)
Figure 9: Measurement points (a) front side, (b) Back side
30 V/div
10 ns/div
tf = 6.7 ns
90%–10%
fall time
tr = 1.9 ns
10%–90%
rise time
VIN = 150 V, VOUT = 5 V, IOUT = 2 A, fsw = 100 kHz, L = 30 μH
Figure 10: Typical switch-node waveform when operated as a buck converter
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EPC9004C
SPECIAL FEATURE: GND - PGND DISCONNECT
The EPC9004C board has been provided with the ability to
disconnect the signal ground (GND) from the power ground
(PGND) which is useful for applications where a shunt is used in
the PGND path. The grounds can be disconnected by removing
R85 as shown in figure 11. Note that the NCP51820 gate driver
has a maximum ground difference voltage limit of ±3.5 V.
Bootstrap supply
GND disconnected
The EPC9004C board is equipped with three mechanical
spacers that can be used to easily attach a heat-spreader or
heatsink as shown in figure 12 (a), and only requires a thermal
interface material (TIM), a custom shape heat-spreader/
heatsink, and screws. Prior to attaching a heat-spreader, any
component exceeding 1 mm in thickness under the heatspreader area will need to be removed from the board as
shown in figure 12 (b).
Gate driver
CBypass
Q1
EN
Hin
Lin
DT
VIN
LDO
LDO
THERMAL CONSIDERATIONS
The EPC9004C board is equipped with three mechanical
spacers that can be used to easily attach a heat-spreader or
heatsink as shown in figure 12 (a), and only requires a thermal
interface material (TIM), a custom shape heat-spreader/
heatsink, and screws. Prior to attaching a heat-spreader, any
component exceeding 1 mm in thickness under the heatspreader area will need to be removed from the board as
shown in figure 12 (b).
DBTST
VDD
L1
Level
shift
LDO
Out
Q2
Logic
Logic
LDO
Cout
Level
shift
GND
PGND
GND jumper
R85 Remove
DO NOT EXCEED
voltage rating of LDO
Figure 11: GND – PGND disconnect warnings
Components to remove prior
to Heat-spreader attach
20 mm
Spacers for heat-spreader
attach
9.2 mm
M2 screws (x3)
Heat-spreader
SMD spacer (x3)
16.7 mm
PCB
assembly
TIM
(b)
Insulator
eGaN FETs (x2)
Figure 12: Details for attaching a heatsink to the development board.
(a) 3D perspective, (b) top view details, (c) Assembled view with heatspreader attached.
(c)
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EPC9004C
45°C
Ø4.0
7.5
3.1
8.0
3.6
1.3
20.0
9.2
16.7
11.0
M2 screw flat heat
countersunk,
Scale 8:1
7.5
When assembling the heatsink, it may be necessary add a
thin insulation layer to prevent the heat-spreader from short
circuiting with components that have exposed conductors
such as capacitors and resistors, as shown in figure 13. Note
that the heat-spreader is ground connected by the lower
most mounting post. A rectangular opening in the insulator
must be provided to allow the TIM to be placed over the FETs
to be cooled with a minimum clearance of 3 mm on each side
of the rectangle encompassing the FETs. The TIM will then
be similar in size or slightly smaller than the opening in the
insulator shown by the red dashed outline in figure 14.
Ø2.2 thru
17.0
5.2
22.0
The heat-spreader is held in place using countersunk screws
that fasten to the mechanical spacers which will accept M2 x
0.4 mm thread screws such as McMasterCarr 91294A002.
39.0
14.0
>
The design of the heat-spreader is shown in figure 13 and can
be made using aluminum or tellurium copper for higher
performance.
Units: mm
Part thickness: 1.5 mm
Figure 13: Heat-spreader details
EPC recommends Laird P/N: A14692-30, Tgard™ K52 with
thickness of 0.051 mm the for the insulating material.
A TIM is added to improve the interface thermal conductance
between the FETs and the attached heat exchanger. The
choice of TIM needs to consider the following characteristics:
• Mechanical compliance – During the attachment of the
heat spreader, the TIM underneath is compressed from
its original thickness to the vertical gap distance between
the spacers and the FETs. This volume compression exerts
a force on the FETs. A maximum compression of 2:1 is
recommended for maximum thermal performance and to
constrain the mechanical force which maximizes thermal
mechanical reliability.
3.1
29.2
9.2
5.2
14.0
Ø4.6 (x3)
16.7
EFFICIENT POWER CONVERSION
11.0
EFFICIENT POWER CONVERSION
9.0
• Thermal performance – The choice of thermal interface
material will affect the thermal performance of the thermal
solution. Higher thermal conductivity materials is preferred
to provide higher thermal conductance at the interface.
20.0
23.0
• Electrical insulation – The backside of the eGaN FET is a
silicon substrate that is connected to source and thus the
upper FET in a half-bridge configuration is connected to the
switch-node. To prevent short-circuiting the switch-node
to the grounded thermal solution, the TIM must be of high
dielectric strength to provide adequate electrical insulation
in addition to its thermal properties.
39.0
Units: mm
28.0
Figure 14: Insulator sheet details with opening for the
TIM with location of the FETs
EPC recommends the following thermal interface materials:
•
•
•
•
t-Global
t-Global
Bergquist
Bergquist
P/N: TG-A1780 X 0.5 mm
P/N: TG-A6200 X 0.5 mm
P/N: GP5000-0.02
P/N: GPTGP7000ULM-0.020
(highest conductivity of 17.8 W/m·K)
(moderate conductivity of 6.2 W/m·K)
(~0.5 mm with conductivity of 5 W/m·K)
(conductivity of 7 W/m·K)
NOTE. The EPC9004C development board does not have any current or thermal protection on board. For more information
regarding the thermal performance of EPC eGaN FETs, please consult:
D. Reusch and J. Glaser, DC-DC Converter Handbook, a supplement to GaN Transistors for Efficient Power Conversion,
First Edition, Power Conversion Publications, 2015.
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EPC9004C
Table 2: Bill of Materials
Item Qty
1
10
2
3
4
5
6
7
3
1
1
3
Reference
Cm1, Cm2, Cm3, Cm4, Cm5, Cm6,
Cm7, Cm8, Cm9, Cm10
Ci1, Ci2, Ci3, Ci4, Ci5, Ci6, Ci7
C11, C100, C101
C60
C76
C80, C81, C83
Part Description
Manufacturer
Part Number
Capacitor, 150 nF 500 V
KEMET
C1210C154KCRAC7800
Capacitor, 22 nF 500 V
Capacitor, 1 μF 25 V XR7
Capacitor, 100 nF 25 V 10% x7r Low ESL
Capacitor, 15 pF 50 V
Capacitor, 1 μF 25 V XR5
KEMET
TDK
TDK
TDK
TDK
7
1
C82
Capacitor, 470 nF 25 V
TDK
8
9
2
6
C601, C602
C610, C611, C612, C614, C615, C616
Capacitor, 47 pF 50 V
Capacitor, 100 nF 25 V 10% x7r
Yageo
Yageo
10
2
C620, C625
Capacitor, 100 pF 50 V X7R 10%
Yageo
11
12
13
14
1
1
1
1
J3
J80
J90
J630, J640
Amphenol
Tyco
Tyco
Sullins
15
1
JP640
Harwin Inc
M50-2020005
16
17
18
2
3
2
Q1, Q2
R86, R90, R100
R620, R625
Bottom Side install
Bottom Side install
Bottom Side install
50 mil TH
'JMP_05_Blu_wHndl
JMP_05_Red_wHndl
eGaN FET, 200 V 100 mΩ 5 A
Resistor, 0 Ω 0.1 W
Resistor, 120 0.1 W
C0805W223KCRAC7800
C1608X7R1E105K080AB
C1005X7R1E104K050BB
CGA2B2C0G1H150J050BA
C1005X5R1E105K050BC
C2005X5R1E474K050BB,
GRT155R61E474ME01D
CC0402JRNPO9BN470
CC0402KRX7R8BB104
CC0402KRX7R9BB101,
CGA2B2NP01H101J050BA
67997-272HLF
4-103185-0-04
4-103185-0-02
GRPB032VWVN-RC
EPC
Panasonic
Yageo
19
1
R60
Resistor, 2 1/16 W
Stackpole
20
3
R70, R75, R77
Resistor, 2.2 0.1 W
Panasonic
21
12
R71, R76, R601, R602, R603, R604,
R605, R621, R626, R73, R641, R643
Resistor, 10 k 1/10
Yageo
22
2
R80, R82
Resistor, 20 Ω 1/16 W
Stackpole
EPC2012C
ERJ-3GEY0R00V
RC0603FR-07120RL
RMCF0402JT2R00,
RC0402FR-072RL
ERJ-2GEJ2R2X,
RMCF0402FT2R20
RC0402FR-0710KL,
RC0402JR-0710KL ,
ERJ-2RKF1002X
RMCF0402JT20R0
23
24
25
26
27
28
29
30
31
32
2
1
2
1
2
4
1
1
4
2
R81, R83
R85
SO1, SO2, SO3
D62
D620, D625
TP1, TP2, TP3, TP4
U80
U100
U610, U611, U612, U614
U615, U616
Resistor, 2 Ω 1/16 W
Resistor, 0 Ω 1/16 W
Spacer M2 1 mm
Diode, 600 V 200 mA
Diode, 30 V 30 mA
SMD probe loop
IC GATE DRVR HALF-BRIDGE HI SPD
IC REG LINEAR 5 V 250 MA 8DFN
IC CONFIG MULTI-FUNC GATE 8-XSON
Bi directional SW 5 Ω 5.5 V
Stackpole
Stackpole
Wurth
Rohm
Diodes Inc.
Keystone
On Semi
MicroChip
Nexperia
Texas Instruments
RMCF0402JT2R00
RMCF0402ZT0R00
9774010243R
RFU02VSM6STR
SDM03U40-7
5015
NCP51820AMNTWG
MCP1703T-5002E/MC
74LVC1G99GT,115
SN74LVC1G66DBV
Reference
Part Description
Manufacturer
Part Number
Table 3: Optional Components
Item
Qty
1
1
L1
TBD
TBD
TBD
2
3
4
5
6
7
8
9
10
3
2
1
1
2
1
1
1
2
J1, J2, J32
C70, C75
C87
Cout
D1, D2
J9
J81
R84
R11, R22
SMD MMCX
100 pF 50 V
100 nF 25 V
TBD
400 V, 1 A
7.62 mm TH
100 mil TH
10 k 0.1 W
0 Ω 1/16 W
Molex
Yageo
TDK
TBD
Diodes Inc.
Wurth
Tyco
Yageo
Stackpole
734152063
CC0402KRX7R9BB101
C1608X7R1E104K080AA
TBD
SBR1U400P1-7
691216410002
4-103185-0-02
RC0603JR-0710KL
RMCF0402ZT0R00
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
| 10
2
1
V dd12
100 mil TH
V CC
5V
GND
V dd12
VIN
R 90
0603
0 Ω 0.1W
C11
0603
1 μF 25 V
GND
Logic Supply
10-15 VDC
VIN
Cm1
1210
150 nF 500 V
GND
GND
GNDP
5 V Logic Regulator
Cm2
1210
150 nF 500 V
GNDP
2
1
100 mil TH
E MPT Y
EN
R 11
0402
0 Ω 1/16 W
Upper Gate
ELECTROSTATIC
SENSITIVE DEVICE
GND
ELECTROSTATIC
SENSITIVE DEVICE
PWM1
PWM2
PWM1
GD
P1029_Rev2_0_NCP51820_GateDriver.SCHDOC
GNDP
VIN
VIN
VIN
VIN
V CC
Vdd12
HI N
Cm4
1210
150 nF 500 V
GNDP
Cm5
1210
150 nF 500 V
GNDP
Cm6
1210
150 nF 500 V
GNDP
Cm7
1210
150nF 500V
GNDP
Cm8
1210
150 nF 500 V
GNDP
Cm9
1210
150 nF 500 V
GNDP
Qlow
EN
GND
100 mil TH
GND
Dead-time and buffers
GND
Signal Inputs
PS
EPC2012C_Rev1_0_PhaseLeg.SCHDOC
VGu
VIN
VIN
VGuH
VGuL
VGuL
VSW
V SW
SW
GND
VGl
Gate Driver
Power Stage
R 22
0402
0 Ω 1/16 W
E MPT Y
R 85
GND
0402
0 Ω 1/16 W
GNDP
Ground Connect
VIN
VIN
VIN
VIN
2
4
6
8
J22
GNDP
Hole 100mil 1 row, 2 pos.
HIGH VOLTAGE
ClassName: HighVoltage
Net C lass
i
V OUT
V OUT
L1
J9
1
2
T P3 SM D T P
Keystone5015
Cout
TBD
E MPT Y
GNDP
V Gl
GNDP
7.62 mm T H
E MPT Y
Sync Buck Output
GNDP
GNDP
ClassName: HighVoltage
Net C lass
i
V SW
J32
SMD MMCX
E MPT Y
J2
SMD MMCX
E MPT Y
1
2
T P4 SM D T P
Keystone5015
GNDP
VGl
GNDP
VIN
T P1 SM D T P
Keystone5015
VGlL
GNDP
1
3
5
7
T P2 SM D T P
K eystone5015
TBD
E MPT Y
VGlH
VGlL
GND
J3A
Main Supply Input
HIGH VOLTAGE
ATTENTION
PWML
EN
GNDP
Bottom Side install
Amphenol
67997-272HL F
HOT SURFACE
VGlH
LIN
Cm10
1210
150 nF 500 V
V Gu
VGuH
VSW
I n2
i Net C lass
ClassName: HighVoltage
Intermediate Capacitors
PWMH
I n1
PWM2
VIN
VIN
VIN
VIN
VIN
V Gu
V dd12
Qup
ATTENTION
GND
Cm3
1210
150 nF 500 V
V SW
ATTENTION
V CC
1
2
3
4
VIN
E MPT Y
DT
AP1010_Rev3_02_GeneralDeadtime.SCHDOC
J80
VIN
Net C lass
i ClassName: HighVoltageGate
J1
SMD MMCX
E MPT Y
J81
VIN
VCC
QUICK START GUIDE
J3B
V SW
V SW
V SW
V SW
9
11
13
15
V SW
V SW
V SW
V SW
10
12
14
16
Bottom Side install
SW Output
J33
1
2
Hole 100mil 1 row, 2 pos.
J3C
GNDP
GNDP
GNDP
17
19
21
23
GNDP
Switch-node
Lower Gate
18
20
22
24
Bottom Side install
GNDP
SO1
Spacer M2 1 mm
9774010243R
SO2
Spacer M2 1 mm
9774010243R
SO3
Spacer M2 1 mm
9774010243R
GND
GNDP
FD 1 FD 2 FD 3
PC
PCB Fiducial
Heatspreader Mount
Figure 15: EPC9004C Main schematic
GNDP
| 11
EPC9004C
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
V1
AP1006_Rev2_01_12Vto5VlinPSU.SCHDOC
J90
QUICK START GUIDE
VIN
VIN
VIN
Ci1
22 nF 500 V
0805
GNDP
GNDP
VIN
Ci2
22 nF 500 V
0805
GNDP
VIN
Ci3
22 nF 500 V
0805
GNDP
VIN
Ci4
22 nF 500 V
0805
GNDP
VIN
Ci5
22 nF 500 V
0805
GNDP
VIN
Ci6
22 nF 500 V
0805
GNDP
Ci7
22 nF 500 V
0805
GNDP
HF Loop Capacitors
GNDP
DC Input
160 Vmax.
Net Class
i ClassName: HighVoltageGate
VIN
VGu
VGuH
VGuL
VGlL
i
Net Class
ClassName: HighVoltage
R 80
0402
20 Ω 16 W
Q1
EPC2012C
200 V 100 mΩ 5 A
VGu
D1
SBR1U400P1-7
400 V, 1 A
E MPT Y
R 81
0402
2 Ω 1/16 W
SW
VGl
VGlH
VIN
SW
i Net Class
ClassName: HighVoltage
R 82
0402
20 Ω 16 W
D2
SBR1U400P1-7
400 V, 1 A
E MPT Y
Q2
EPC2012C
200 V 100 mΩ 5 A
VGl
R 83
0402
2 Ω 1/16 W
GNDP
Power Stage
Figure 16: EPC9004C Power Stage schematic
GNDP
Optional Diodes
| 12
EPC9004C
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
Vin
QUICK START GUIDE
Vdd12
C60
0402
100 nF 25 V
GND
Vdd12
GND
PWMH
D62
RFU02VSM6STR
600 V 200 mA
C82
0402
470 nF 25 V
Vdd12
R 70
0402
2.2 0.1 W
C70
0402
100 pF 50 V
EMPTY
C80
0402
1 μF 25 V
R 71
0402
10 k 1/16 W
GND
PWML
R 60
0402
2 1/16 W
GND
Net C lass
i ClassName: HighVoltageGate
GND
GND
Vdd12
R 75
0402
2.2 0.1W
R 76
0402
10 k 1/16 W
GND
GND
Bst
VDD
UVLO
12
Hin
11
Lin
13
EN
9
DT
Logic
&
DeadTime
Reg
UVLO
Level
Shift
Reg
C87
GND
0603
100 nF 25 V
E MPT Y
C81
0402
1 μF 25 V
2
3
VGuH
VGuL
4
VSW
PGND
Gate Driver
VGuH
VGuL
VSW
5
6
7
Level
Shift
SGND
1
VGlH
VGlL
VGlH
VGlL
8
C83
0402
1 μF 25 V
U80
NCP51820AMNTWG
R 86
0603
0 Ω 0.1 W
GND
Vdd12 14
10
R 84
0603
10 k 0.1 W
E MPT Y
C75
0402
100 pF 50 V
E MPT Y
15
Vdd12
GNDP
GNDP
GNDP
GNDP
GND
Default = Mode A: R77 = 0
External dead-time
Cross conduction protection
Vdd12
EN
R 73
0402
10 k 0.1 W
R 77
0402
2.2 0.1 W
C76
0402
15 pF 50 V
GND
Figure 17: EPC9004C Gate Driver schematic
| 13
EPC9004C
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
Vdd12
M50-2030005
50 mil
V CC
J630
PolQlow
PolQup
Dual
GND
1
3
5
2
4
6
M50-2020005
50 mil
Buck Single Signal
Boost Single Signal
Dual Signal
V CC
V CC
V CC
GRPB032VWVN-RC
50 mil TH
GND
C610
0402
100 nF 25 V
GND
3
C601
0402
47 pF 50 V
7
5
SWbyp
GND
R 620
R 603
0402
10 k 1/16 W
GND
Polarity 0=Non-invert, 1= Invert
Default = 10 ns
1
I n1
GND
I n2
3
Dual
7
5
GND
GND
Polarity 0=Non-invert, 1= Invert
G ND
R 641
0402
10 k 1/16 W
GND
Qup
GND
V CC
U614
74LV C1G99GN,115
SWbyp
V CC
1
V CC
C614
0402
100 nF 25 V
VCC
2
I nBufQlow
3
UseDT
D625
SD M03U40-7
30 V 30 mA
Deadtime Lower
Default = 10 ns
C625
0402
100 pF 50 V
GND
GND
DT Qup
Output Buffers and Signal Select
0603
120 0.1 W
C615
0402
100 nF 25 V
GND
GND
G ND
R 605
R 604
0402
0402
10 k 1/16 W 10 k 1/16 W
GND
GND
R 625
PolQlow 6
4
GND
C602
0402
47 pF 50 V
VCC
SW byp
U615
SN74LVC1G66DBV
Bi directional SW 5 Ω 5.5 V
V CC
G ND
GND
GND
GND
R 602
0402
10 k 1/16 W
R 621
0402
10 k 1/16 W
GND
I n1
V CC
6
C611
0402
100nF 25V
2
7
5
V CC
8
V CC
I n2
C620
0402
100 pF 50 V
Deadtime Upper
Signal Polarity and Input Buffers
I n2
UseDT
D620
SD M03U40-7
30 V 30 mA
GND
U611
74LV C1G99GN,115
3
0603
120 0.1 W
G ND
GND
4
GND
C612
0402
100 nF 25 V
VCC
1
2
I nBufQup
PolQup 6
GND
V CC
V CC
U612
74LVC1G99GN,115
8
2
GND
Full Bypass
No Bypass
DT Bypass
4
R 601
0402
10 k 1/16 W
V CC
8
I n1
V CC
V CC
V CC
GRPB032VWVN-RC
50 mil TH
V CC
VCC
1
I n1
I n1
2
4
6
Bypass Mode Select
8
V CC
1
3
5
UseDT
Dual/Single PWM, Buck, and Boost Mode Selector
U610
74LVC1G99GN,115
J640
SWbyp
R 626
0402
10 k 1/16 W
7
5
DT Qlow
I n2
VCC
SW byp
U616
SN74LVC1G66DBV
Bi directional SW 5 Ω 5.5 V
V CC
G ND
R 643
0402
10 k 1/16 W
GND
C616
0402
100 nF 25 V
GND
GND
Qlow
6
G ND
GND
GND
GND
| 14
EPC9004C
Figure 18: EPC9004C Dead-time and Bypass schematic
4
V CC
QUICK START GUIDE
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
JP640
JP630
QUICK START GUIDE
EPC9004C
U100
5.0 V 250 mA DFN
MCP1703T-5002E/MC
V CC
R100
IN
0603
0 Ω 0.1W
5V
OUT
G ND
C100
0603
1 μF 25 V
C101
0603
1 μF 25 V
GND
GND
GND
GND
GND
Figure 19: EPC9004C Logic Supply Regulator schematic
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 |
| 15
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Demonstration Board Notification
The EPC9004C board is intended for product evaluation purposes only. It is not intended for commercial use nor is it FCC approved for resale. Replace components on
the Evaluation Board only with those parts shown on the parts list (or Bill of Materials) in the Quick Start Guide. Contact an authorized EPC representative with any questions. This board is
intended to be used by certified professionals, in a lab environment, following proper safety procedures. Use at your own risk.
As an evaluation tool, this board is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board
builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
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