EPC9006C

Development Board EPC9006C - Rev. 3.0 Quick Start Guide EPC2007C 100 V Half Bridge with Gate Drive QUICK START GUIDE EPC9006C DESCRIPTION The EPC9006C development board is a 100 V maximum device voltage, 7 A maximum output current, half bridge with onboard gate drives, featuring the EPC2007C enhancement mode (eGaN®) field effect transistor (FET). The purpose of this development board is to simplify the evaluation process of the EPC2007C eGaN FET by including all the critical components on a single board that can be easily connected into any existing converter. The EPC9006C development board is 2” x 1.5” and contains two EPC2007C eGaN FETs in a half bridge configuration using, the Texas Instruments LM5113 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC2007Cs eGaN FET please refer to the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25°C) Symbol Parameter VDD Gate Drive Input Supply Range VIN Min Max Units 7 12 V Bus Input Voltage Range 80* V VOUT Switch Node Output Voltage 100 V IOUT Switch Node Output Current 7* A 6 1.5 V V PWM Logic Input Voltage Threshold Minimum ‘High’ State Input Pulse Width Minimum ‘Low’ State Input Pulse Width VPWM Conditions Input ‘High’ Input ‘Low’ 3.5 0 VPWM rise and fall time < 10 ns 50 ns VPWM rise and fall time < 10 ns 100# ns *Assumes inductive load, maximum current depends on die temperature – actual maximum current will be subject to switching frequency, bus voltage and thermals. # Limited by time needed to ‘refresh’ high side bootstrap supply voltage. QUICK START GUIDE Development board EPC9006C is easy to set up to evaluate the performance of the EPC2007C eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8). 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. VDD PWM Input Gate Drive Regulator Logic and Dead-time Adjust Gate Drive Supply Half Bridge with Bypass VIN LM5113 Gate Driver OUT 3. With power off, connect the gate drive supply to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2). 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range. Figure 1: Block Diagram of EPC9006C Development Board 6. Turn on the controller / PWM input. 7. Turn on the bus voltage supply, starting a zero, and adjust to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT) and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. PAGE 2 | | EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 QUICK START GUIDE 7 V – 12 V _ EPC9006C 6C, 100 VDD Supply + Gate Drive Supply (Note Polarity) A IIN + VIN _ Switch Node V (For Efficiency Measurement) +