EPC9024

NOTE. The development board does not have any current or thermal protection on board. The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C. Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter CH2: (VOUT) Switch node voltage –– CH4: VPWM Input voltage Figure 3: Proper Measurement of Switch Node – OUT Place probe tip on pad Minimize loop THERMAL CONSIDERATIONS Do not let probe tip touch the low-side die! NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. a. EPC9022, 65 V b. EPC9023, 100 V c. EPC9024, 40 V g. EPC9029, 65 V h. EPC9030, 100 V Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION EPC Figure 1: Block Diagram of Development Board With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below: The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: PWM Input – (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust – VIN V LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator External Circuit OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply See Table 1 + for max A + Gate Drive Supply (Note Polarity) VDD Supply – 7 V – 12 V Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Quick Start Procedure www.epc-co.com Demonstration Board EPC9022/23/24/25/27/28/29/30 Quick Start Guide Half Bridge with Gate Drive for EPC8000 Family The development board is 2” x 1.5” and contains two eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate VDD Demonstration Board Notification The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. www.epc-co.com The development board is in a half bridge topology with onboard gate drives, featuring the EPC8000 family of high frequency enhancement mode (eGaN®) field effect transistors (FETs). The purpose of these development boards is to simplify the evaluation process of the EPC8000 family of eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. SYMBOL EPC Products are distributed exclusively through Digi-Key. www.digikey.com 1. 2. 3. 4. 5. 6. d. EPC9025, 65 V e. EPC9027, 40 V f. EPC9028, 40 V Do not use probe ground lead Contact us: DESCRIPTION PARAMETER driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC8000 family of eGaN FETs, please refer to the datasheets available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25°C) CONDITIONS Gate Drive Input Supply Range VIN Bus Input Voltage Range VOUT Switch Node Output Voltage IOUT Switch Node Output Current VPWM PWM Logic Input Voltage Threshold Minimum ‘High’ State Input Pulse Width Minimum ‘Low’ State Input Pulse Width When using 40 V devices; EPC8004, EPC8007, EPC8008 When using 65 V devices; EPC8002, EPC8005, EPC8009 When using 100 V devices; EPC8003, EPC8010 When using 40 V devices; EPC8004, EPC8007, EPC8008 When using 65 V devices; EPC8002, EPC8005, EPC8009 When using 100 V devices; EPC8003, EPC8010 When using 40 V device EPC8004 When using 40 V device EPC8007 When using 40 V device EPC8008 When using 65 V device EPC8002 When using 65 V device EPC8005 When using 65 V device EPC8009 When using 100 V device EPC8003 When using 100 V device EPC8010 Input ‘High’ Input ‘Low’ VPWM rise and fall time < 10ns VPWM rise and fall time < 10ns * Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals. † Limited by time needed to ‘refresh’ high side bootstrap supply voltage. MIN MAX UNITS 7 12 28* 45* 70* 40 65 100 4.4 3.5* 2.2* 1.6* 2.2* 3.5* 2.2* 3.2* 6 1.5 V V V V V V V A A A A A A A A V V ns ns 3.5 0 20 50† NOTE. The development board does not have any current or thermal protection on board. The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C. Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter CH2: (VOUT) Switch node voltage –– CH4: VPWM Input voltage Figure 3: Proper Measurement of Switch Node – OUT Place probe tip on pad Minimize loop THERMAL CONSIDERATIONS Do not let probe tip touch the low-side die! NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION g. EPC9029, 65 V h. EPC9030, 100 V Figure 1: Block Diagram of Development Board With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below: The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: PWM Input EPC – (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust – VIN V LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator External Circuit OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply +