EPC9048

Development Board EPC9048 Quick Start Guide Half Bridge with Gate Drive for EPC2034 Revision 1.0 QUICK START GUIDE Demonstration System EPC9048 DESCRIPTION Table 1: Performance Summary (TA = 25°C) The EPC9048 development boards are in a half bridge topology with onboard gate drives, featuring the EPC2034 eGaN® field effect transistors (FETs). The purpose of these development boards is to simplify the evaluation process of these eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. The development board is 2” x 1.5” and contains two eGaN FETs in a half bridge configuration using the Texas Instruments UCC27611 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC2034 eGaN FET please refer to the data sheet available from EPC at www.epc-co.com. The data sheet should be read in conjunction with this quick start guide. Symbol Parameter VDD Gate Drive Input Supply Range VIN Conditions Min Max Units 7 12 V Bus Input Voltage Range 140 V VOUT Switch Node Output Voltage 160 V IOUT Switch Node Output Current 12* A VPWM PWM Logic Input Voltage Threshold Input ‘High’ Input ‘Low’ 3.5 0 6 1.5 V V Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 100 ns Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 100# ns *Assumes inductive load, maximum current depends on die temperature – actual maximum current will be subject to switching frequency, bus voltage and thermal management. # Dependent on time needed to ‘refresh’ high side bootstrap supply voltage. QUICK START PROCEDURE The development boards are easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8). 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2). 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. 5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range. VDD Gate Drive Regulator Enable PWM Input 6. Turn on the controller / PWM input source. 7. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 150 V on VOUT. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Gate Drive Supply Half Bridge with Bypass VIN Level shift, Dead-time Adjust and Gate Drive OUT Figure 1: Block Diagram of Development Board 2 | | EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 QUICK START GUIDE Demonstration System EPC9048 7 V – 12 V _ 48, 160 Additional bus capacitance can be added on back VDD Supply + Gate Drive Supply (Note Polarity) A IIN + VIN _ Switch Node V (For Efficiency Measurement) +