EPC9055

Development Board EPC9055 Quick Start Guide Half Bridge with Gate Drive for EPC2106 DESCRIPTION This development board is in a monolithic half bridge topology with onboard gate drives, featuring the EPC2106 eGaN (Enhancement-mode Gallium Nitride) Integrated Dual FET. The purpose of these development boards is to simplify the evaluation process of these eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. The development board is 2” x 1.5” and contains a dual integrated eGaN FET, in a half bridge configuration using the Texas Instruments LM5113 gate driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC2106 eGaN Integrated Dual FET, please refer to the datasheets available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25°C) SYMBOL PARAMETER VDD Gate Drive Input Supply Range VIN CONDITIONS MIN MAX UNITS 7 12 V Bus Input Voltage Range 80 V VOUT Switch Node Output Voltage 100 V IOUT Switch Node Output Current 3* A VPWM PWM Logic Input Voltage Threshold Input ‘High’ Input ‘Low’ 3.5 0 6 1.5 V V Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 60 ns Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 100# ns *Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals cooling. # Limited by time needed to ‘refresh’ high side bootstrap supply voltage. For More Information: Please contact info@epc-co.com or your local sales representative Visit our website: www.epc-co.com Sign-up to receive EPC updates at bit.ly/EPCupdates or text “EPC” to 22828 EPC Products are distributed through Digi-Key. www.digikey.com Demonstration Board Notification EPC9055 boards are intended for product evaluation purposes only and are not intended for commercial use. As evaluation tools, they are not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 QUICK START GUIDE EPC9055 QUICK START PROCEDURE The EPC9055 development board is easy to set up to evaluate the performance of the eGaN-IC monolithic half bridge. The board allows the on-board placement of buck output filter components. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: 1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8). 5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT of 100 V) 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2). 9. For shutdown, please follow steps in reverse. 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. VDD Gate Drive Regulator PWM Input Logic and Dead-time Adjust NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. Gate Drive Supply Monolithic Half Bridge VIN LM5113 Gate Driver OUT Figure 1: Block Diagram of Development Board EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 | | PAGE 2 QUICK START GUIDE EPC9055 QUICK START PROCEDURE 7 V – 12 V _ 55, 80 VDD Supply + Gate Drive Supply (Note Polarity) A IIN + VIN _ Switch Node V (For Efficiency Measurement) +