Development Board
EPC9066
Quick Start Guide
EPC8004
40 V Half Bridge with Sync FET Bootstrap Gate Drive
QUICK START GUIDE
EPC9066
DESCRIPTION
The EPC9066 development board is a 40 V maximum device voltage,
2.7 A maximum output current, half bridge with onboard gate drives,
featuring the EPC8004 enhancement mode (eGaN®) field effect transistor
(FET). The gate driver has been configured with a synchronous FET
bootstrap circuit featuring the EPC2038 eGaN FET that eliminates high
side device losses induced by the reverse recovery losses of the internal
bootstrap diode of the gate driver. The purpose of this development
board is to simplify the evaluation process of the EPC8004 eGaN FET by
including all the critical components on a single board that can be easily
connected into any existing converter. The inclusion of the synchronous
FET bootstrap circuit enables significant increase in operating frequency
capability of the half bridge circuit.
The EPC9066 development board is 2” x 1.5” and has two EPC8004 eGaN
FETs in a half bridge configuration using Texas Instruments LM5113 gate
driver with supply and bypass capacitors. The board contains all critical
components and layout for optimal switching performance. There are
also various probe points to facilitate simple waveform measurement
and efficiency calculation. The board includes pads for the inclusion of
customer components to facilitate testing in a Buck converter or ZVS
class-D amplifier configurations. A complete block diagram of the circuit
is given in figure 1.
Table 1: Performance Summary (TA = 25°C) EPC9066
Symbol
Parameter
VDD
Gate Drive Input Supply
Range
VIN
Bus Input Voltage Range
Conditions
Min
Max
Units
7.5
12
V
32*
V
VOUT
Switch Node Output Voltage
40
V
IOUT
Switch Node Output Current
2.7*
A
VPWM
PWM Logic Input Voltage
Threshold
Minimum ‘High’ State Input
Pulse Width
Minimum ‘Low’ State Input
Pulse Width
6
1.5
V
V
Input ‘High’
3.5
Input ‘Low’
0
VPWM rise and
fall time < 10ns 40
VPWM rise and
fall time < 10ns 160#
ns
ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current
with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
For more information on the EPC8004 and EPC2038 eGaN FETs please
refer to the datasheet available from EPC at www.epc-co.com. The
datasheet should be read in conjunction with this quick start guide.
QUICK START PROCEDURE
Development board EPC9066 is easy to set up to evaluate the performance
of the EPC8004 eGaN FET. Refer to figure 2 for proper connect and
measurement setup and follow the procedure below:
1. Configure the board for either ZVS class-D operation OR Buck converter
operation.
2. With power off, connect the input power supply bus to +VIN (J1) and
ground / return to –VIN (J4).
3. For ZVS class-D operation, with power off, connect a HF load to the HF
output (RF-J2 OR Vsw-J3 and GND-J4). For Buck converter operation,
with power off, connect a DC load to the DC output (+Vout-J5 and
GND-J4).
4. With power off, connect the gate drive input to +VDD (J90, Pin-1) and
ground return to –VDD (J90, Pin-2).
5. With power off, connect the input PWM control signal to PWM (J70,
Pin-1) and ground return to either Pin-2 or Pin-4 of J70.
6. Turn on the gate drive supply – make sure the supply is within the 7.5 V
and 12 V range.
7. Turn on the controller / PWM input source and probe switching node to
observe switching operation.
PAGE 2 |
EPC9066 amplifier board photo
8. Turn on the bus voltage to the required value (do not exceed the
absolute maximum voltage of 52 V on VOUT). Increase voltage slowly
while monitoring operation to ensure the FETs are operating within
their datasheet parameters.
9. Once operational, adjust the bus voltage and load PWM control
within the operating range and observe the output switching
behavior, efficiency and other parameters.
10. For shutdown, please follow steps in reverse.
When measuring the high frequency content switch node, care
must be taken to avoid long ground leads. Measure the switch node by
placing the oscilloscope probe tip through the large via on the switch
node (designed for this purpose) and grounding the probe directly
across the GND terminal provided. See figure 3 for proper scope probe
technique.
NOTE.
| EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016
QUICK START GUIDE
EPC9066
VIN
HF output
PWM
Gate drive
regulator
Logic and
dead-time
adjust
Q2
Level shift
VDD
L ZVS
DC output
L Buck
C OUT
C Bypass
Q1
C ZVS
GND
PGND
V
Figure 1: Block diagram of EPC9066 development board
7.5 – 12 VDC
+
VIN supply
(note polarity)
Main voltage
measurement
Switch-node
oscilloscope probe
Ground post
High frequency
connection
Dead-time
setting
(if installed)
Control
signal
inputs
SMA (optional)
32 VDCmax
+
VMain supply
(note polarity)
DC output
DC output
measurement
V
Figure 2: Proper connection and measurement setup
Do not use
probe ground lead
Ground probe
against post
Place probe tip
in large via
Minimize loop
Figure 3: Proper measurement of the switch node
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 |
|PAGE 3
QUICK START GUIDE
EPC9066
THERMAL CONSIDERATIONS
The EPC9066 development board showcases the EPC8004 eGaN FET.
Although the electrical performance surpasses that for traditional
silicon devices, their relatively smaller size does magnify the thermal
management requirements. The EPC9066 is intended for bench
evaluation with low ambient temperature and convection cooling.
The addition of heat-sinking and forced air cooling can significantly
increase the current rating of these devices, but care must be taken to
not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9066 development board does not have any current or thermal
protection on board.
Table 2: Bill of Materials - Amplifier Board
Item
Qty
Reference
Part Description
Manufacturer/Part Number
1
1
C40
Capacitors, Ceramic, 4.7 µF, 10 V, ±20%, X5R
Samsung, CL05A475MP5NRNC
2
3
C4, C5, C6
Capacitors, Ceramic, 1.0 µF, 100 V, ±10%, X7S
TDK, C2012X7S2A105K125AB
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
3
2
2
1
3
2
1
1
1
2
1
3
1
1
1
2
1
1
1
1
4
0.19
4
C95, C96, C97
C71, C72
C41, C44
C45
C1, C2, C3
C42, C43
R46
R70
R74
R45, R75
R44
D45, D74, D75
D40
D41
Q44
Q1, Q2
U95
U40
U72
U71
TP1, TP2, TP3, TP4
J70, J90, GP1 (See Note 1)
J1, J3, J4, J5
Capacitors, Ceramic, 1.0 µF, 25 V, ±10%, X5R
Capacitors, Ceramic, 100 nF, 25 V, ±10%, X7R
Capacitors, Ceramic, 100 nF, 16 V, ±10%, X7R
Capacitors, Ceramic, 22 nF, 25 V, ±10%, X7R
Capacitors, Ceramic, 10 nF, 100 V, ±20%, X7S
Capacitors, Ceramic, 22 pF, 50 V, ±5%, NPO
Resistors, 27 KΩ, ±1%, 1/10 W
Resistors, 10.0 KΩ, ±1%, 1/10 W
Resistors, 82 Ω, ±1%, 1/10 W
Resistors, 20 Ω, ±1%, 1/16 W
Resistors, 4.7 Ω, ±1%, ±/16 W
Diodes, Schottky Diode, 30 V, VF=370 mV @ 1 mA, 30 mA
Diodes, Schottky, 100 V, 0.2 A, VF=1 V @ 200 mA
Diodes, Zener, 5.1 V, 150 mW, ±5%
eGaN® FET, 100 V, 500 mA, RDS(on) =2.1 Ω @ 50 mA, 5 V
eGaN® FET, 40 V, 4.4 A, RDS(on) =125 mΩ @ 500 mA, 5 V
IC's, 5 V LDO, 250 mA, up to 16 VIN, Vdropout=0.33 V @ 250 mA
IC's, Gate Driver, 5.2 VDC, 1.2 A, 4.5 V to 5.5 V
IC's, Logic 2 NAND Gate, 1.65 V to 5.5 V, ±24 mA
IC's, 2 Input AND Gate, Tiny Logic, 1.65 V to 5.5 V, ± 32 mA
Test Point, Test Point Subminiature
Headers, Male Vertical, 36 Pin. 230" Contact Height, .1" Center Pitch
Headers, 2 Rows by 2 Pins .1" Male Vertical, .1" Center Pitch
Murata, GRM188R61E105KA12D
TDK, C1005X7R1E104K050BB
Murata, GRM155R71C104KA88D
TDK, C1005X7R1E223K050BB
TDK, C1005X7S2A103M050BB
TDK, C1005C0G1H220J050BA
Panasonic, ERJ-2RKF2702X
Panasonic, ERJ-6ENF1002V
Panasonic, ERJ-2RKF82R0X
Stackpole, RMCF0402FT20R0
Yageo, RC0402FR-074R7L
Diodes Inc, SDM03U40-7
ST Microelectronics, BAT41KFILM
Bourns Inc., CD0603-Z5V1
EPC, EPC2038
EPC, EPC8004
Microchip, MCP1703T-5002E/MC
Texas Instruments, LM5113TME/NOPB
Fairchild, NC7SZ00L6X
Fairchild, NC7SZ08L6X
Keystone, 5015
FCI, 68001-236HLF
TE Connectivity, 5-146256-2
Optional Components
Item
Qty
Reference
Part Description
Manufacturer/Part Number
1
1
C7
Capacitors, DNP, Ceramic, 1.0 µF, 100 V, ±10%, X7S
TDK, C2012X7S2A105K125AB
2
1
C46
Capacitor, DNP, Ceramic, 100 nF, 16 V, ±10%, X7R
Murata, GRM155R71C104KA88D
3
3
R71, R72, R73
2
P74, P75
5
1
Lbuck
6
7
8
1
1
1
Lzvs
D44
J2
9
1
HS1
Resistor, DNP, 0 Ω, 1/10 W, Jumper
Potentiometer, DNP, Multi-turn Potentiometer, 1 kΩ, ±10%, 1/4 W, 12 Turn
Top Adjustment Small
Inductor, DNP, 10 μH, ±20%, 3.5A, 33 mΩ, Resonance=40 MHz, Frequency
Tested=100 KHz
Inductor, DNP, 500 nH, Q=180, 50 MHz, DCR=16.5 mΩ, IRMS=4.3 A
Diodes, DNP, Schottky Diode, 30 V, VF=370 mV @ 1 mA, 30 mA
Connector, DNP, RP-SMA Plug, 50 Ω
Hardware, DNP, W= (0.590") 15 mm, by L= (0.590") 15 mm, H=(0.374")
9.5 mm, 26.2°C/W @ 200 LFM
Panasonic, ERJ-3GEY0R00V
4
Murata, PV37W102C01B00
Wϋrth, 744314101
Coilcraft, 2929SQ-501JEB
Diodes Inc, SDM03U40-7
Linx, CONREVSMA013.062
Advanced Thermal Solutions, ATS-54150D-C2-R0
Note 1 (36 pin Header to be cut as follows) J70 cut 4 pins used, J90 cut 2 pins used, GP1 cut 1 pin used
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 |
|PAGE 4
.1” Male Vert.
1
2
J90
1
2
3
4
J70
.1” Male Vert.
R73
DNP
PWM2
PWM2
PWM1
R70
10 K
PWM1
V7 in
PWM2
PWM1
PWM1
PWM1
B
C72
100 nF, 25 V
5V
A
C71
100 nF, 25 V
5V
B
A
V7 in
5V
5V
2
DNP 0 Ω
R71
1
2
DNP 0 Ω
R72
U72
NC 7SZ00L 6X
1
U71
NC 7SZ08L 6X
Y
IN
GND
OUT
2
DNP 100 Ω
R74
2
DNP 220 Ω
R75
D75
SDM0 3U40
DNP 1 K
P75
Deadtime Left
1
D74
SDM03U40
DNP 1 K
P74
Deadtime Right
1
Logic Supply Regulator
C95
1 μF, 25 V
L _Sig
H_Sig
C96
1 μF, 25 V
5V
C42
22 pF, 50 V
C43
22 pF, 50 V
L _Sig
H_Sig
C97
1 μF, 25 V
GL H1
GL H1
GRret1
GRH1
GRH1
5 VHS 1
HS 1
DNP
4.7 V
R45
20 Ω
Gbtst
C40
4.7 μF, 10 V
R46
27 K
1
GL H1
5V
D45
SDM0 3U40
D40
BAT5 4 K FIL M
C45
22 nF, 25 V
D44
E MP T Y
SDM0 3U40
Figure 4: EPC9066 - Schematic
Gate Driver
U40
L M5113T M
C46
E MP T Y
100 nF, 16 V
4.7 V
C44
100 nF, 16 V
5V
Q44
EPC2038
100 V, 2.8 Ω
1
2
U95
MCP1703T-5002E/MC
5.0 V, 250 mA DFN
1
2
1
2
1
2
2
C41
100 nF, 16 V
GRret1
PGND
PGND
Q2
EPC8004
Q1
EPC8004
Vmain
Vmain
PGND
Ground Post
.1” Male Vert.
1
GP1
SMD probe loop
1
T P2
GL H1
GRret1
GRH1
SMD probe loop
1
T P1
1
SMD probe loop
1
T P4
L buck
DNP
HF
PGND
PGND
C6
1 μF, 100 V
Output
C7
1 μF, 100 V
PGND
PGND
Vmain
2 x 2 .1” Male Vert.
1
2
3
4
J1
1
2
3
4
J5
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 |
GND
2 x 2 .1” Male Vert.
1
2
3
4
J4
PGND
HF Output
J2
SMA Board Edge
SW Output
2 x 2 .1” Male Vert.
1
2
3
4
J3
Buck Output
2 x 2 .1” Male Vert.
PGND
C5
1 μF, 100 V
Vmain
Main Supply Input
PGND
C4
1 μF, 100 V
Vmain
C3
10 nF, 100 V
Vmain
PGND
ZVS Tank Circuit
Output
SMD probe loop
L zvs
DNP 500 nH
T P3
C2
10 nF, 100 V
Vmain
PGND
PH1
ProbeHole
PGND
C1
10 nF, 100 V
Vmain
D41
CD 0603-Z5V1
5 VHS 1
Synchronous Bootstrap Power Supply
4E 7
R44
1
Logic Supply
7.5 VDC - 12 VDC
QUICK START GUIDE
EPC9066
|PAGE 5
For More Information:
Please contact info@epc-co.com
or your local sales representative
Visit our website:
www.epc-co.com
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or text “EPC” to 22828
EPC Products are distributed through Digi-Key.
www.digikey.com
Demonstration Board Notification
The EPC9066 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European
Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain
components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No
Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
