B37830R0220K023

Multilayer ceramic capacitors Array capacitors, C0G Date: October 2006 Data Sheet ã EPCOS AG 2006. Reproduction, publication and dissemination of this data sheet and the information contained therein without EPCOS’ prior express consent is prohibited. Multilayer ceramic capacitors Array C0G Ordering code system B37830 R 0 101 K 0 2 1 Packaging 1 ^ cardboard tape, 180-mm reel 3 ^ cardboard tape, 330-mm reel 2 ^ 2-fold array 4 ^ 4-fold array Internal coding: 0 or decimal place for cap. values 10 nF the time constant t = C · Rins is given. Please read Cautions and warnings and Important notes at the end of this document. 3 10/06 C0G 55/125/56 EIA Class 1 25, 50 2.5 · VR/5 s 10 pF … 1.0 nF (E6) 0 ± 30 · 10 –6/K 105 >104 >1000 >100 –55 … +125 none VDC VDC MW MW s s °C Multilayer ceramic capacitors C0G C0G Capacitance tolerances Code letter J K (standard) Tolerance ± 5% ±10% Dimensional drawing 2-fold array (case size 0405) 4-fold array (case sizes 0508 and 0612) u u b s s b k e k e e KKE0331-Z KKE0330-R Dimensions (mm) 2-fold array 4-fold array 0405 1012 0508 1220 0612 1632 l 1.37 ± 0.15 2.00 ± 0.2 3.20 ± 0.2 b 1.00 +0/–0.15 1.25 ± 0.15 1.60 ± 0.2 s 0.70 max. 0.85 ± 0.1 0.85 ± 0.1 k 0.36 ± 0.1 0.30 ± 0.1 0.40 ± 0.15 e 0.64 0.50 ± 0.1 0.80 ± 0.15 u 0.20 ± 0.1 0.20 +0.3/–0.1 0.20 +0.3/–0.1 Case size (inch) (mm) Tolerances to CECC 32101-801 Please read Cautions and warnings and Important notes at the end of this document. 4 10/06 Multilayer ceramic capacitors C0G C0G Recommended solder pad 2-fold array (case size 0405) 4-fold array (case sizes 0508 and 0612) P P D A B C B C A D KKE0302-L KKE0309-9 Recommended dimensions (mm) for reflow soldering Case size (inch/mm) Type A B C D P 0405/1012 2-fold array 0.50 … 0.55 0.45 … 0.50 1.45 … 1.60 0.30 … 0.35 0.64 ± 0.10 0508/1220 4-fold array 0.50 … 0.70 0.60 … 0.70 1.60 … 2.10 0.25 … 0.35 0.50 ± 0.005 0612/1632 4-fold array 0.70 … 0.90 0.80 … 1.00 2.20 … 2.80 0.30 … 0.40 0.80 ± 0.005 Termination Termination (nickel barrier) Ceramic body Inner electrode AgPd Substrate electrode Intermediate electrode External electrode Ag Ni Sn KKE0366-S-E Please read Cautions and warnings and Important notes at the end of this document. 5 10/06 Multilayer ceramic capacitors C0G C0G Product range array capacitors, C0G 2-fold arrays Size1) inch mm Type VR (VDC) CR 10 pF 15 pF 22 pF 33 pF 47 pF 68 pF 100 pF 150 pF 180 pF 220 pF 330 pF 470 pF 680 pF 4-fold arrays 0405 1012 0508 1220 0612 1632 B37830 B37940 B37871 25 50 50 1.0 nF 1) l ´ b (inch) / l ´ b (mm) Please read Cautions and warnings and Important notes at the end of this document. 6 10/06 Multilayer ceramic capacitors C0G; 0405 C0G Ordering codes and packing for C0G arrays, 25 VDC, nickel barrier terminations mm Cardboard tape, Æ 180-mm reel *^1 pcs/reel Cardboard tape, Æ 330-mm reel *^3 pcs/reel 0.6 ± 0.1 0.6 ± 0.1 0.6 ± 0.1 0.6 ± 0.1 0.6 ± 0.1 0.6 ± 0.1 0.6 ± 0.1 0.6 ± 0.1 0.6 ± 0.1 5000 5000 5000 5000 5000 5000 5000 5000 5000 20000 20000 20000 20000 20000 20000 20000 20000 20000 Chip thickness CR1) Ordering code 2) Case size 0405, 25 VDC, 2-fold arrays 10. 15. 22. 33. 47. 68. 100. 150. 180. pF pF pF pF pF pF pF pF pF B37830R0100K02* B37830R0150K02* B37830R0220K02* B37830R0330K02* B37830R0470K02* B37830R0680K02* B37830R0101K02* B37830R0151K02* B37830R0181K02* 1) Other capacitance values on request. 2) The table contains the ordering codes for the standard capacitance tolerance. For other available capacitance tolerances see page 128. Please read Cautions and warnings and Important notes at the end of this document. 7 10/06 Multilayer ceramic capacitors C0G C0G; 0508 and 0612 Ordering codes and packing for C0G arrays, 50 VDC, nickel barrier terminations mm Cardboard tape, Æ 180-mm reel *^1 pcs/reel Cardboard tape, Æ 330-mm reel *^3 pcs/reel 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 4000 4000 4000 4000 4000 4000 4000 4000 4000 16000 16000 16000 16000 16000 16000 16000 16000 16000 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 0.85 ± 0.1 4000 4000 4000 4000 4000 4000 4000 4000 4000 4000 4000 4000 4000 16000 16000 16000 16000 16000 16000 16000 16000 16000 16000 16000 16000 16000 Chip thickness CR1) Ordering code 2) Case size 0508, 50 VDC, 4-fold arrays 10. 15. 22. 33. 47. 68. 100. 150. 220. pF pF pF pF pF pF pF pF pF B37940R5100K04* B37940R5150K04* B37940R5220K04* B37940R5330K04* B37940R5470K04* B37940R5680K04* B37940R5101K04* B37940R5151K04* B37940R5221K04* Case size 0612, 50 VDC, 4-fold arrays 10. pF 15. pF 22. pF 33. pF 47. pF 68. pF 100. pF 150. pF 220. pF 330. pF 470. pF 680. pF 1.0 nF B37871R5100K04* B37871R5150K04* B37871R5220K04* B37871R5330K04* B37871R5470K04* B37871R5680K04* B37871R5101K04* B37871R5151K04* B37871R5221K04* B37871R5331K04* B37871R5471K04* B37871R5681K04* B37871R5102K04* 1) Other capacitance values on request. 2) The table contains the ordering codes for the standard capacitance tolerance. For other available capacitance tolerances see page 128. Please read Cautions and warnings and Important notes at the end of this document. 8 10/06 Multilayer ceramic capacitors C0G C0G Typical characteristics 1) Capacitance change DC/C25 versus temperature T (tolerance range ) ∆C C 25 Capacitance change DC/C0 versus superimposed DC voltage V KKE0107-F 1.0 % KKE0357-T 0.5 0.6 ∆C % C0 0.3 0.4 0.2 0.2 0.1 0 0 _ 0.2 _ 0.1 _ 0.4 _ 0.2 _ 0.6 _ 0.3 _ 0.8 _ 0.4 _ 1.0 _ 55 _ 40 _ 20 0 20 40 60 80 _ 0.5 ˚C 120 T 0 10 20 30 40 V 50 V Dissipation factor tan d versus temperature T Impedance |Z| versus frequency f KKE0367-4 10 5 10 _2 KKE0118-V Ω tan δ Z 10 4 10 3 10 2 10 1 10 pF 10 _3 100 pF 1 nF 10 _4 10 0 10 10 _1 _2 10 0 10 1 10 2 10 MHz 10 3 f _5 _ 60 _ 40 _ 20 0 20 40 60 80 100 C 140 ˚ T 1) For more detailed information on frequency behavior and characteristics see www.epcos.com/mlcc_impedance. Please read Cautions and warnings and Important notes at the end of this document. 9 10/06 Multilayer ceramic capacitors C0G C0G Typical characteristics 1) Capacitance change DC/C1 versus time t Insulation resistance Rins versus temperature T KKE0129-B 10 8 MΩ KKE0100-S 5 ∆C % C1 0 R ins 10 6 _5 10 5 _ 10 10 4 _ 15 10 3 10 2 0 20 40 60 80 100 _ 20 10 0 ˚C 140 T 10 1 10 2 h 10 3 t 1) For more detailed information on frequency behavior and characteristics see www.epcos.com/mlcc_impedance. Please read Cautions and warnings and Important notes at the end of this document. 10 10/06 Multilayer ceramic capacitors Cautions and warnings Notes on the selection of ceramic capacitors In the selection of ceramic capacitors, the following criteria must be considered: 1. Depending on the application, ceramic capacitors used to meet high quality requirements should at least satisfy the specifications to AEC-Q200. They must meet quality requirements going beyond this level in terms of ruggedness (e.g. mechanical, thermal or electrical) in the case of critical circuit configurations and applications (e.g. in safety-relevant applications such as ABS and airbag equipment or durable industrial goods). 2. At the connection to the battery or power supply (e.g. clamp 15 or 30 in the automobile) and at positions with stranding potential, to reduce the probability of short circuits following a fracture, two ceramic capacitors must be connected in series and/or a ceramic capacitor with integrated series circuit should be used. The MLSC from EPCOS contains such a series circuit in a single component. 3. Ceramic capacitors with the temperature characteristics Z5U and Y5V do not satisfy the requirements to AEC-Q200 and are mechanically and electrically less rugged than C0G or X7R/X8R ceramic capacitors. In applications that must satisfy high quality requirements, therefore, these capacitors should not be used as discrete components (see the chapter “Effects on mechanical, thermal and electrical stress”, point 1.4). 4. For ESD protection, preference should be given to the use of multilayer varistors (MLV) (see the chapter “Effects on mechanical, thermal and electrical stress”, point 1.4). 5. An application-specific derating or continuous operating voltage must be considered in order to cushion (unexpected) additional stresses (see the chapter “Reliability”). The following should be considered in circuit board design 1. If technically feasible in the application, preference should be given to components having an optimal geometrical design. 2. At least FR4 circuit board material should be used. 3. Geometrically optimal circuit boards should be used, ideally those that cannot be deformed. 4. Ceramic capacitors must always be placed a sufficient minimum distance from the edge of the circuit board. High bending forces may be exerted there when the panels are separated and during further processing of the board (such as when incorporating it into a housing). 5. Ceramic capacitors should always be placed parallel to the possible bending axis of the circuit board. 6. No screw connections should be used to fix the board or to connect several boards. Components should not be placed near screw holes. If screw connections are unavoidable, they must be cushioned (for instance by rubber pads). 11 10/06 Multilayer ceramic capacitors Cautions and warnings The following should be considered in the placement process 1. Ensure correct positioning of the ceramic capacitor on the solder pad. 2. Caution when using casting, injection-molded and molding compounds and cleaning agents, as these may damage the capacitor. 3. Support the circuit board and reduce the placement forces. 4. A board should not be straightened (manually) if it has been distorted by soldering. 5. Separate panels with a peripheral saw, or better with a milling head (no dicing or breaking). 6. Caution in the subsequent placement of heavy or leaded components (e.g. transformers or snap-in components): danger of bending and fracture. 7. When testing, transporting, packing or incorporating the board, avoid any deformation of the board not to damage the components. 8. Avoid the use of excessive force when plugging a connector into a device soldered onto the board. 9. Ceramic capacitors must be soldered only by the mode (reflow or wave soldering) permissible for them (see the chapter “Soldering directions”). 10. When soldering the most gentle solder profile feasible should be selected (heating time, peak temperature, cooling time) in order to avoid thermal stresses and damage. 11. Ensure the correct solder meniscus height and solder quantity. 12. Ensure correct dosing of the cement quantity. 13. Ceramic capacitors with an AgPd external termination are not suited for the lead-free solder process: they were developed only for conductive adhesion technology. This listing does not claim to be complete, but merely reflects the experience of EPCOS AG. 12 10/06 Multilayer ceramic capacitors Important notes The following applies to all products named in this publication: 1. Some parts of this publication contain statements about the suitability of our products for certain areas of application. These statements are based on our knowledge of typical requirements that are often placed on our products in the areas of application concerned. We nevertheless expressly point out that such statements cannot be regarded as binding statements about the suitability of our products for a particular customer application. As a rule, EPCOS is either unfamiliar with individual customer applications or less familiar with them than the customers themselves. For these reasons, it is always ultimately incumbent on the customer to check and decide whether an EPCOS product with the properties described in the product specification is suitable for use in a particular customer application. 2. We also point out that in individual cases, a malfunction of passive electronic components or failure before the end of their usual service life cannot be completely ruled out in the current state of the art, even if they are operated as specified. In customer applications requiring a very high level of operational safety and especially in customer applications in which the malfunction or failure of a passive electronic component could endanger human life or health (e.g. in accident prevention or life-saving systems), it must therefore be ensured by means of suitable design of the customer application or other action taken by the customer (e.g. installation of protective circuitry or redundancy) that no injury or damage is sustained by third parties in the event of malfunction or failure of a passive electronic component. 3. The warnings, cautions and product-specific notes must be observed. 4. In order to satisfy certain technical requirements, some of the products described in this publication may contain substances subject to restrictions in certain jurisdictions (e.g. because they are classed as “hazardous”). Useful information on this will be found in our Material Data Sheets on the Internet (www.epcos.com/material). Should you have any more detailed questions, please contact our sales offices. 5. We constantly strive to improve our products. Consequently, the products described in this publication may change from time to time. The same is true of the corresponding product specifications. Please check therefore to what extent product descriptions and specifications contained in this publication are still applicable before or when you place an order. We also reserve the right to discontinue production and delivery of products. Consequently, we cannot guarantee that all products named in this publication will always be available. 6. Unless otherwise agreed in individual contracts, all orders are subject to the current version of the “General Terms of Delivery for Products and Services in the Electrical Industry” published by the German Electrical and Electronics Industry Association (ZVEI). 7. The trade names EPCOS, EPCOS-JONES, Baoke, CeraDiode, CSSP, MLSC, PhaseCap, PhaseMod, SIFERRIT, SIFI, SIKOREL, SilverCap, SIMID, SIOV, SIP5D, SIP5K, UltraCap, WindCap are trademarks registered or pending in Europe and in other countries. Further information will be found on the Internet at www.epcos.com/trademarks. 13 10/06