CeraLink Capacitors
Series/Type:
B58031
The following products presented in this data sheet are being withdrawn.
Ordering Code
Substitute Product
Date of Withdrawal
B58031U5105M002
B58031I7504M002
B58031I5105M002
B58031U5105M062
B58031I7504M062
B58031I5105M062
2016-11-18
2016-11-18
2016-11-18
Deadline Last
Orders
2017-03-31
2017-03-31
2017-03-31
Last Shipments
2017-06-30
2017-06-30
2017-06-30
For further information please contact your nearest EPCOS sales office, which will also support you in selecting a suitable substitute. The
addresses of our worldwide sales network are presented at www.epcos.com/sales.
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Applications
• Power converters and inverters
• DC link/ snubber capacitor for power converters and inverters
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
High ripple current capability
High temperature robustness
Low equivalent serial inductance (ESL)
Low equivalent serial resistance (ESR)
Low power loss
Low dielectric absorption
Optimized for high frequencies up to several MHz
Increasing capacitance with DC bias up to operating voltage
High capacitance density
Minimized dielectric loss at high temperatures
High reliability
Qualification based on AEC-Q200 rev. D
Suitable for reflow soldering only
Construction
•
•
•
•
•
RoHS-compatible PLZT ceramic (lead lanthanum zirconium titanate)
Copper inner electrodes
Silver outer electrodes
Silver coated copper-invar lead frame
Epoxy resin adhesive
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 2 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Electrical specifications VR = 500 V
Vpk,max
= 650 V
VR
= 500 V
Operating voltage at maximum attenuation capability
Vop
= 400 V
Typical nominal capacitance
Cnom,typ
> 1 µF
Ceff,typ
= 0.6 µF
C0
= 0.35 µF ± 20%
tan δ
< 0.02
Rins,typ
> 1 GΩ
Tdevice
-40 °C... +150 °C
Maximum peak operating voltage
@ Vpk,max, 25 °C, 7 s
Rated voltage
Reference DC voltage for reliability tests
@ Vop, quasistatic, 25 °C. See glossary (page 21) for definition of the nominal capacitance.
Typical effective capacitance
@ Vop, 0.5 VRMS, 1 kHz, 25 °C
Initial capacitance
@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C
Dissipation factor
@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C
Insulation resistance
@ Vop, t > 240 s, 25 °C
Operating device temperature
approx. 1.3 g
Weight of device
Typical values
1)
ESL
Iop
1)
Iop
1)
ESR
ESR
0 VDC, 0.5 VRMS,
0 VDC, 0.5 VRMS,
100 kHz
100 kHz
25 °C, 1 MHz
25 °C, 1 kHz
TA = 85 °C
TA = 105 °C
mΩ
Ω
nH
ARMS
ARMS
12
3.3
2.5
7.5
5.2
Normal operating current without forced cooling at Tdevice = 125 °C. Higher values permissible at reduced lifetime.
Ordering codes
Packaging
Packaging unit pcs. Ordering code
Rated voltage
Terminal style
Cardboard box
100
B58031I5105M002
B58031U5105M002
500 V
500 V
L
J
330-mm reel
1000
B58031I5105M062
B58031U5105M062
500 V
500 V
L
J
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 3 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Electrical specifications VR = 700 V
Vpk,max
= 1000 V
VR
= 700 V
Operating voltage at maximum attenuation capability
Vop
= 600 V
Typical nominal capacitance
Cnom,typ
> 0.5 µF
Ceff,typ
= 0.25 µF
C0
= 0.14 µF ± 20%
tan δ
< 0.02
Rins,typ
> 1 GΩ
Tdevice
-40 °C... +150 °C
Maximum peak operating voltage
@ Vpk,max, 25 °C, 7 s
Rated voltage
Reference DC voltage for reliability tests
@ Vop, quasistatic, 25 °C. See glossary (page 21) for definition of the nominal capacitance.
Typical effective capacitance
@ Vop, 0.5 VRMS, 1 kHz, 25 °C
Initial capacitance
@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C
Dissipation factor
@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C
Insulation resistance
@ Vop, t > 240 s, 25 °C
Operating device temperature
approx. 1.3 g
Weight of device
Typical values
1)
ESL
Iop
1)
Iop
1)
ESR
ESR
0 VDC, 0.5 VRMS,
0 VDC, 0.5 VRMS,
100 kHz
100 kHz
25 °C, 1 MHz
25 °C, 1 kHz
TA = 85 °C
TA = 105 °C
mΩ
Ω
nH
ARMS
ARMS
28.7
9
2.5
5.4
4.4
Normal operating current without forced cooling at Tdevice = 125 °C. Higher values permissible at reduced lifetime.
Ordering codes
Packaging
Packaging unit pcs. Ordering code
Rated voltage
Terminal style
Cardboard box
100
B58031I7504M002
700 V
L
330-mm reel
1000
B58031I7504M062
700 V
L
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 4 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Code construction CeraLink™
1)
LP series: Terminal style 1 = L-style terminal, Terminal style 2 = J-style terminal
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 5 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Dimensional drawings
L-style terminal
J-style terminal
Recommended solder pads
Dimensions in mm
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 6 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Polarity
L-style terminal
J-style terminal
Marking of components
Manufacturer’s logo
CeraLink™ type
Nominal capacitance
Rated voltage
Lot number, 9 digits
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 7 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Typical characteristics as a function of temperature and voltage VR = 500 V
(VAC = 0.5 VRMS, frequency = 1 kHz)
All given temperatures are device temperatures.
The curves show the relative changes of the capacitance, dissipation factor and ESR. The 100%
values correspond to Ceff,typ and tan δ which are given on page 3 of this data sheet.
120
120
T [°C]
-25
25
85
125
110
100
Capacitance [%]
Capacitance [%]
100
90
80
70
Bias
[VDC]
0
400
500
110
90
80
70
60
60
50
50
40
0
100
200
300
400
500
-50
-25
0
Voltage [VDC]
600
50
75
100
125
150
600
T [°C]
-25
25
85
125
400
300
200
Bias
[VDC]
0
400
500
500
Dissipation factor [%]
500
Dissipation factor [%]
25
Temperature [°C]
100
400
300
200
100
0
0
0
100
200
300
400
500
-50
-25
0
Voltage [VDC]
25
50
75
100
125
150
Temperature [°C]
500
600
T [°C]
-25
25
85
125
400
Bias
[VDC]
0
400
500
500
ESR [%]
ESR [%]
400
300
200
300
200
100
100
0
0
0
100
200
300
400
500
-50
Voltage [VDC]
0
25
50
75
100
125
150
Temperature [°C]
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
-25
2016-07-28
Page 8 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Typical capacitance values as a function of voltage VR = 500 V
225
Variable
Large signal capacitance:
Quasistatic (slow variation of the voltage), 25 °C
The nominal capacitance is defined as the large
signal capacitance at Vop.
See glossary for further information.
large signal
small signal
200
Capacitance [%]
175
150
125
100
Small signal capacitance:
0.5 VRMS, 1 kHz, 25 °C
The effective capacitance is defined as the small
signal capacitance at Vop.
75
50
0
100
200
300
400
500
Voltage [VDC]
Typical impedance and ESR as a function of frequency VR = 500 V
1000
Variable
Z
ESR
100
VDC = 0 V, VAC = 0.5 VRMS, Tdevice = 25 °C
|Z|, ESR [Ohm]
10
1
0.1
0.01
0.001
1000
10000
100000
1000000
10000000
Frequency [Hz]
Typical permissible current as a function of frequency VR = 500 V
Normal operation current [Arms]
8
Tamb
[°C]
85
7
105
6
5
Measurement performed at Vop.
The values correspond to a device temperature
of 125 °C.
No forced cooling was used.
4
3
2
1
0
20
40
60
80
100
Frequency [kHz]
Aging
The capacitance has an aging behavior which shows a decrease of capacitance with time.
The typical aging rate is about 2.5% per logarithmic decade in hours.
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 9 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Typical characteristics as a function of temperature and voltage VR = 700 V
(VAC = 0.5 VRMS, frequency = 1 kHz)
All given temperatures are device temperatures.
The curves show the relative changes of the capacitance, dissipation factor and ESR. The 100%
values correspond to Ceff, typ and tan δ which are given on page 4 of this data sheet.
130
120
110
100
90
80
70
Bias
[VDC]
0
600
700
120
Capacitance [%]
Capacitance [%]
140
T/°C
-25
25
75
125
100
80
60
60
40
50
40
20
0
100
200
300
400
Voltage [VDC]
500
600
700
T/°C
-25
25
75
125
600
400
300
200
0
50
Temperature [°C]
100
150
Bias
[VDC]
0
600
700
600
500
Dissipation factor [%]
500
Dissipation factor [%]
-50
100
400
300
200
100
0
0
0
100
200
300
400
Voltage [VDC]
500
600
700
500
-50
50
Temperature [°C]
100
150
600
T/°C
-25
25
75
125
400
0
Bias
[VDC]
0
600
700
500
ESR [%]
ESR [%]
400
300
200
300
200
100
100
0
0
0
100
200
300
400
Voltage [VDC]
500
600
700
-50
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
0
50
Temperature [°C]
100
150
2016-07-28
Page 10 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Typical capacitance values as a function of voltage VR = 700 V
Variable
large signal * V
small signal * Bias [V]
200
Capacitance [%]
175
150
125
Large signal capacitance:
Quasistatic (slow variation of the voltage), 25 °C
The nominal capacitance is defined as the large
signal capacitance at Vop.
See glossary for further information.
100
Small signal capacitance:
0.5 VRMS, 1 kHz, 25 °C
The effective capacitance is defined as the small
signal capacitance at Vop.
75
50
0
100
200
300
400
500
Voltage [VDC]
600
700
Typical impedance and ESR as a function of frequency VR = 700 V
Variable
|Z| [Ohm]
ESR [Ohm]
100
VDC = 0 V, VAC = 0.5 VRMS, Tdevice = 25 °C
|Z|, ESR [Ohm]
10
1
0.1
0.01
0.001
10000
100000
1000000
Frequency [Hz]
10000000
Typical permissible current as a function of frequency VR = 700 V
Normal operation current [Arms]
6
Tamb
[°C]
85
105
5
4
Measurement performed at Vop.
The values correspond to a device temperature
of 125 °C.
No forced cooling was used.
3
2
1
0
20
40
60
Frequency [kHz]
80
100
Aging
The capacitance has an aging behavior which shows a decrease of capacitance with time.
The typical aging rate is about 2.5% per logarithmic decade in hours.
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 11 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Reliability
A. Preconditioning:
Reflow solder the capacitor on a PCB using the recommended soldering profile
Check of external appearance
Measurement of electrical parameters Rins, C0, tan δ
o Apply Vpk,max for 7 seconds and measure Rins at room temperature:
Isolation resistance (@ Vpk,max, 7 s, 25 °C)
Rins > 100 MΩ
o Measure C0 and tan δ within 10 minutes to 1 hour afterwards:
Initial capacitance (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C)
Dissipation factor (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C)
B. Performance of a specific reliability test.
C. After performing a specific test:
Check the external appearance again
Repeat the measurement of the electrical parameters
o Apply Vpk,max for 7 seconds and measure Rins at room temperature:
Isolation resistance (@ Vpk,max, 7 s, 25 °C)
Rins > 10 MΩ
o Measure C and tan δ:
Change of initial capacitance (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C) | Δ C / C0 | < 15%
o Dissipation factor (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C)
tan δ < 0.05
Test
Standard
External
appearance
Test conditions
Criteria
Visual inspection with magnifying glass
No defects that might
affect performance
High
temperature
operating life
MIL-STD-202,
method 108
150 °C, VR, 1000 hours
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Biased
humidity
MIL-STD-202,
method 103
85 °C, 85% rel. hum., VR, 1000 hours
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Temperature
shock
IEC 60384-9,
4.8
-55 °C to +150 °C
20 seconds transfer time
15 minutes dwell time
1000 cycles
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Terminal
strength test
AEC-Q200-005 Apply a force of 17.7 N for 60 seconds
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
No detaching of
termination. No rupture of
ceramic
| Δ C / C0 |, tan δ and Rins
within defined limits
2016-07-28
Page 12 of 25
CeraLink™
Capacitor for fast-switching semiconductors
Test
Standard
Tensile
strength test
(unsoldered)
Board flex
B58031*
Low profile (LP) series
Test conditions
Criteria
Apply a force of 10 N in the shown direction
Ceramic body is clamped
No detaching of
termination. No rupture of
ceramic
| Δ C / C0 |, tan δ and Rins
within defined limits
AEC-Q200-005 Bending of 2 mm for 60 seconds.
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Dimension drawing in mm.
Vibration
MIL-STD-202,
method 204
5 g/ 20 min, 12 cycles, 3 axis
10 Hz to 2000 Hz
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Mechanical
shock
MIL-STD-202,
method 213
Acceleration 400 m/s²
Half sine pulse duration 6 milliseconds
4000 bumps
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
3 times recommended reflow soldering profile
No mechanical damage
Proper solder coating of
contact areas
| Δ C / C0 |, tan δ and Rins
within defined limits
Reflow test
Leaching test
(lead frame
only)
MIL-STD-202,
method 210,
condition B
Dip test of contact areas in solder bath
(260 °C for 10 seconds)
No damage of lead frame
silver coating
Solderability
(lead frame
only)
J-STD-002,
method A @
235 °C,
category 3
Dip test of contact areas in solder bath
(235 °C for 5 ± 0.5 seconds)
> 95% wettability of lead
frame
Resistance to
solvent
Dipping and cleaning with isopropanol
Marking must be legible
| Δ C / C0 |, tan δ and
Rins within defined limits
Geometry
Using a caliper
Within specified tolerance
in the chapter construction
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 13 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Packaging
The CeraLink™ will be delivered in a blister tape (taping to IEC 60286-3).
Blister tape for L-style terminal
Part orientation
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 14 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Blister tape for J-style terminal
Part orientation
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 15 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Taping information
Trailer: There is a minimum of 160 mm of carrier tape with empty compartments and sealed by the cover tape.
Leader: There is a minimum of 400 mm of cover tape, which includes at least 100 mm of carrier tape with empty
compartments.
Dimensions in mm
Fixing peeling strength (top tape)
The peeling strength is 0.1 … 1.3 N.
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 16 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Reel packing
L-style terminal
J-style terminal
A
330 ±2
330 ±2
B
100 ±1
62 ±1
C
13 +0.5/ -0.2
12.8 +0.7
D
20.2 min.
19.1 min.
E
2.2 ±0.2
1.6 ±0.5
W
24.2 +2
16.4 +2
Dimensions in mm
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 17 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Recommended reflow soldering profile
Profile feature
SAC, Sn95.5Ag3.8Cu0.7 @ N2 atmosphere
Preheat and soak
- Temperature min
- Temperature max
- Time
Tsmin
Tsmax
tsmin to tsmax
150 °C
200 °C
60 … 180 seconds
Average ramp-up rate
TSmax to Tp
3 °C/ second max.
Liquidus temperature
Time at liquidus temperature
TL
tL
217 °C
60 … 150 seconds
Peak package body temperature
Tp
1)
3)
Time (tp) within 5 °C of specified
classification temperature (Tc)
Average ramp-down rate
Time 25 °C to peak temperature
245 °C … 260 °C max.
30 seconds
Tp to TSmax
2)
3)
6 °C/ second max.
maximum 8 minutes
1) Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
2) Depending on package thickness. For details please refer to JEDEC J-STD-020D.
3) Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Notes:
All temperatures refer to topside of the package, measured on the package body surface.
Max. number of reflow cycles: 3
After the soldering process, the capacitance is lowered. Applying V R to the device will re-establish the capacitance.
The components are suitable for reflow soldering to JEDEC J-STD-020D.
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 18 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
General technical information
Storage
Only store CeraLink™ capacitors in their original packaging. Do not open the package prior to
processing.
Storage conditions in original packaging: temperature −25 °C to +45 °C, relative humidity
≤ 75% annual average, maximum 95%, dew precipitation is inadmissible.
Do not store CeraLink™ capacitors where they are exposed to heat or direct sunlight.
Otherwise the packaging material may be deformed or CeraLink™ may stick together, causing
problems during mounting.
Avoid contamination of the CeraLink™ surface during storage, handling and processing.
Avoid storing CeraLink™ devices in harmful environments where they are exposed to
corrosive gases (e.g. SOx, Cl).
Use CeraLink™ as soon as possible after opening factory seals such as polyvinyl-sealed
packages.
Solder CeraLink™ components within 6 months after shipment from EPCOS.
Handling
Do not drop CeraLink™ components or allow them to be chipped.
Do not touch CeraLink™ with your bare hands - gloves are recommended.
Avoid contamination of the CeraLink™ surface during handling.
The CeraLink™ was tested to withstand the board flex test defined in the AEC-Q200 rev. D,
method 005.
The CeraLink™ uses copper lead frames to prevent mechanical stress to the ceramic. Too
much bending causes open mode. Avoid high mechanical stress like twisting after soldering
on a PCB.
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 19 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Mounting
Do not subject CeraLink™ devices to mechanical stress when encapsulating them with
sealing material or overmolding with plastic material. Encapsulation may lead to worse heat
dissipation too. Please ask for further information.
Do not scratch the electrodes before, during or after the mounting process.
Make sure contacts and housings used for assembly with CeraLink™ components are clean
before mounting.
The surface temperature of an operating CeraLink™ can be higher than the ambient
temperature. Ensure that adjacent components are placed at a sufficient distance from a
CeraLink™ to allow proper cooling.
Avoid contamination of the CeraLink™ surface during processing.
Soldering guidelines
The use of mild, non-activated fluxes for soldering is recommended, as well as proper
cleaning of the PCB.
Complete removal of flux is recommended to avoid surface contamination that can result in an
instable and/or high leakage current.
Use resin-type or non-activated flux.
Bear in mind that insufficient preheating may cause ceramic cracks.
Rapid cooling by dipping in solvent is not recommended, otherwise a component may crack.
Excessive usage of solder paste can reduce the mechanical robustness of the device,
whereas insufficient solder may cause the CeraLink™ to detach from the PCB. Use an
adequate amount of solder paste, but on the landing pads only.
If an unsuitable cleaning fluid is used, flux residue or foreign particles may stick to the
CeraLink™ surface and deteriorate its insulation resistance. Insufficient or improper cleaning
of the CeraLink™ may cause damage to the component.
Excessive washing like ultrasonic cleaning, can affect the connection between the ceramic
chip and the outer electrode. To avoid this, we give the following recommendation:
o Power: 20 W/l max.
o Frequency: 40 kHz max.
o Washing time: 5 minutes max.
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 20 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Glossary
Initial capacitance C0:
Effective capacitance Ceff:
Nominal capacitance Cnom:
Is the value at the origin of the hysteresis without any applied direct
voltage.
Occurs at Vop and is measured with an applied ripple voltage of
0.5 VRMS and 1 kHz. The CeraLink™ is designed to have its highest
capacitance value at the operating voltage Vop.
Is the value derived by the tangent of the mean hysteresis as the
derivation of the mean hysteresis is dQ/dV ~ C.
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 21 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Symbols and terms
AC
C0
Ceff,typ
Cnom,typ
DC
ESL
ESR
Iop
LP
PCB
PLZT
Rins
SAC
TA
tan δ
Vop
VR
VRMS
Vpk,max
Alternating current
Initial capacitance
Typical effective capacitance
Typical nominal capacitance
Direct current
Equivalent serial inductance
Equivalent serial resistance
Operating ripple current, root mean square value of sinusoidal AC current
Low profile
Printed circuit board
Lead lanthanum zirconium titanate
Insulation resistance
Tin silver copper alloy; lead-free solder paste
Ambient temperature
Dissipation factor
Device temperature. Tdevice = TA + ΔT (ΔT defines the self-heating of the device
due to applied current).
Operating voltage
Rated voltage
Root mean square value of sinusoidal AC voltage
Maximum peak operating voltage
ΔT
Increase of temperature during operation
Tdevice
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 22 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Cautions and warnings
General
Not for use in resonant circuits, where a voltage of alternating polarity occurs.
Not for AC applications. Consult your EPCOS representative for further details.
If used in snubber circuits, ensure that the sum of all voltages remains at the same polarity.
Some parts of this publication contain statements about the suitability of our CeraLink™ components
for certain areas of application, including recommendations about incorporation/design-in of these
products into customer applications. The statements are based on our knowledge of typical
requirements often made of our CeraLink™ devices in the particular areas. We nevertheless
expressly point out that such statements cannot be regarded as binding statements about the
suitability of our CeraLink™ components for a particular customer application. As a rule, EPCOS is
either unfamiliar with individual customer applications or less familiar with them than the customers
themselves. For these reasons, it is always incumbent on the customer to check and decide whether
the CeraLink™ devices with the properties described in the product specification are suitable for use
in a particular customer application.
Do not use EPCOS CeraLink™ components for purposes not identified in our specifications.
Ensure the suitability of a CeraLink™ in particular by testing it for reliability during design-in.
Always evaluate a CeraLink™ component under worst-case conditions.
Pay special attention to the reliability of CeraLink™ devices intended for use in safety-critical
applications (e.g. medical equipment, automotive, spacecraft, nuclear power plant).
Design notes
Consider derating at higher operating temperatures. As a rule, lower temperatures and
voltages increase the life time of CeraLink™ devices.
If steep surge current edges are to be expected, make sure your design is as low-inductive as
possible.
In some cases the malfunctioning of passive electronic components or failure before the end
of their service life cannot be completely ruled out in the current state of the art, even if they
are operated as specified. In applications requiring a very high level of operational safety and
especially when the malfunction or failure of a passive electronic component could endanger
human life or health (e.g. in accident prevention, life-saving systems, or automotive battery
line applications such as clamp 30), ensure by suitable design of the application or other
measures (e.g. installation of protective circuitry, fuse or redundancy) that no injury or damage
is sustained by third parties in the event of such a malfunction or failure.
Specified values only apply to CeraLink™ components that have not been subject to prior
electrical, mechanical or thermal damage. The use of CeraLink™ devices in line-to-ground
applications is therefore not advisable, and it is only allowed together with safety
countermeasures such as thermal fuses.
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 23 of 25
CeraLink™
Capacitor for fast-switching semiconductors
B58031*
Low profile (LP) series
Operation
Use CeraLink™ only within the specified operating temperature range.
Use CeraLink™ only within specified voltage and current ranges.
The CeraLink has to be operated in a dry atmosphere, which must not contain any additional
chemical vapors or substances.
Environmental conditions must not harm the CeraLink™. Use the capacitors under normal
atmospheric conditions only. A reduction of the oxygen partial pressure to below 1 mbar is not
permissible.
Prevent a CeraLink™ from contacting liquids and solvents.
Avoid dewing and condensation.
During operation, the CeraLink™ can produce audible noise due to its piezoelectric
characteristic.
EPCOS CeraLink™ components are mainly designed for encased applications. Under all
circumstances avoid exposure to:
o direct sunlight
o rain or condensation
o steam, saline spray
o corrosive gases
o atmosphere with reduced oxygen content
This listing does not claim to be complete, but merely reflects the experience of EPCOS AG.
Display of ordering codes for EPCOS products
The ordering code for one and the same EPCOS product can be represented differently in data
sheets, data books, other publications, on the EPCOS website, or in order-related documents such as
shipping notes, order confirmations and product labels. The varying representations of the
ordering codes are due to different processes employed and do not affect the specifications of
the respective products. Detailed information can be found on the Internet under
www.epcos.com/orderingcodes
PPD MT IC
Please read Cautions and warnings and
Important notes at the end of this document.
2016-07-28
Page 24 of 25
Important notes
The following applies to all products named in this publication:
1. Some parts of this publication contain statements about the suitability of our products for
certain areas of application. These statements are based on our knowledge of typical
requirements that are often placed on our products in the areas of application concerned. We
nevertheless expressly point out that such statements cannot be regarded as binding
statements about the suitability of our products for a particular customer application. As a
rule, EPCOS is either unfamiliar with individual customer applications or less familiar with them
than the customers themselves. For these reasons, it is always ultimately incumbent on the
customer to check and decide whether an EPCOS product with the properties described in the
product specification is suitable for use in a particular customer application.
2. We also point out that in individual cases, a malfunction of electronic components or failure
before the end of their usual service life cannot be completely ruled out in the current state
of the art, even if they are operated as specified. In customer applications requiring a very high
level of operational safety and especially in customer applications in which the malfunction or
failure of an electronic component could endanger human life or health (e.g. in accident
prevention or life-saving systems), it must therefore be ensured by means of suitable design of the
customer application or other action taken by the customer (e.g. installation of protective circuitry
or redundancy) that no injury or damage is sustained by third parties in the event of malfunction or
failure of an electronic component.
3. The warnings, cautions and product-specific notes must be observed.
4. In order to satisfy certain technical requirements, some of the products described in this
publication may contain substances subject to restrictions in certain jurisdictions (e.g.
because they are classed as hazardous). Useful information on this will be found in our Material
Data Sheets on the Internet (www.epcos.com/material). Should you have any more detailed
questions, please contact our sales offices.
5. We constantly strive to improve our products. Consequently, the products described in this
publication may change from time to time. The same is true of the corresponding product
specifications. Please check therefore to what extent product descriptions and specifications
contained in this publication are still applicable before or when you place an order.
We also reserve the right to discontinue production and delivery of products. Consequently,
we cannot guarantee that all products named in this publication will always be available.
The aforementioned does not apply in the case of individual agreements deviating from the
foregoing for customer-specific products.
6. Unless otherwise agreed in individual contracts, all orders are subject to the current version of
the “General Terms of Delivery for Products and Services in the Electrical Industry”
published by the German Electrical and Electronics Industry Association (ZVEI).
7. The trade names EPCOS, CeraDiode, CeraLink, CeraPad, CeraPlas, CSMP, CSSP, CTVS,
DeltaCap, DigiSiMic, DSSP, ExoCore, FilterCap, FormFit, LeaXield, MiniBlue, MiniCell, MKD,
MKK, MotorCap, PCC, PhaseCap, PhaseCube, PhaseMod, PhiCap, PQSine, SIFERRIT, SIFI,
SIKOREL, SilverCap, SIMDAD, SiMic, SIMID, SineFormer, SIOV, SIP5D, SIP5K, TFAP,
ThermoFuse, WindCap are trademarks registered or pending in Europe and in other countries.
Further information will be found on the Internet at www.epcos.com/trademarks.
Page 25 of 25
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