CeraLink®
Capacitors for fast-switching semiconductors
Series/Type:
Ordering code:
Low profile (LP) series
B58031*
Date:
Version:
2019-01-07
6.1
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Identification/Classification 1
CeraLink®
(header 1 + top left bar):
Identification/Classification 2
Capacitors for fast-switching semiconductors
(header 2 + bottom left header bar):
Ordering code: (top right header bar)
B58031*
Series/Type: (bottom right header bar)
Low profile (LP) series
Preliminary data (optional):
Department:
PPD PI AE/IE
Date:
2019-01-07
Version:
6.1
Prepared by:
Markus Hopfer
Signed by :
Markus Hopfer, Harald Kastl, Thomas Pirhofer
Modifications:
™ changed to ®, EPCOS to TDK; IEC 60068-2-58 added p. 17
TDK Electronics AG 2019. Reproduction, publication and dissemination of this publication, enclosures hereto and the
information contained therein without TDK Electronics' prior express consent is prohibited.
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Applications
Power converters and inverters
DC link/snubber capacitor for power converters and inverters
Features
High ripple current capability
High temperature robustness
Low equivalent serial inductance (ESL)
Low equivalent serial resistance (ESR)
Low power loss
Low dielectric absorption
Optimized for high frequencies up to several MHz
Increasing capacitance with DC bias up to operating voltage
High capacitance density
Minimized dielectric loss at high temperatures
Qualification based on AEC-Q200 rev. D
Suitable for reflow soldering only
Construction
RoHS-compatible PLZT ceramic (lead lanthanum zirconium titanate)
Copper inner electrodes
Silver outer electrodes
Silver coated copper-invar lead frame
General technical data
Dissipation factor
Insulation resistance
Operating device temperature
Weight of device
1)
tan 𝛿
Rins, typ1)
Tdevice
< 0.02
>1
-40 … +150
approx.. 1.3
GΩ
°C
g
Typical insulation resistance, measured at operating voltage V op and measurement time > 240s, 25 °C
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 2 of 2
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Electrical specifications and ordering codes
Lead
type
L-style
J-style
L-style
J-style
L-style
J-style
Vpk, max
V
650
650
1000
1000
1300
1300
VR
V
500
500
700
700
900
900
Vop
V
400
400
600
600
800
800
Cnom, typ
µF
1
1
0.5
0.5
0.25
0.25
Ceff, typ
µF
0.6
0.6
0.25
0.25
0.13
0.13
C0
µF
0.35 ±20%
0.35 ±20%
0.14 ±20%
0.14 ±20%
0.07 ±20%
0.07 ±20%
Ordering code
B58031I5105M062
B58031U5105M062
B58031I7504M062
B58031U7504M062
B58031I9254M062
B58031U9254M062
Typical values as a design reference for CeraLink applications
Rated voltage
VR
ESR
0 VDC,
0.5 VRMS,
25 °C, 1 kHz
ESR
0 VDC,
0.5 VRMS,
25 °C, 1 MHz
ESL
Iop 1)
100 kHz
Tamb = 85 °C
Iop 1)
100 kHz
Tamb = 105
°C
V
Ω
mΩ
nH
ARMS
ARMS
500
3
12
3
11
10
700
6
24
3
7
6
900
14
45
3
5
5
1)
Normal operating current without forced cooling at Tdevice = 150 °C. Higher values permissible at reduced lifetime.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 3 of 3
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Dimensional drawings
J-style
L-style
Recommended solder pads
Dimensions in mm
PPD PI AE/IE
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Important notes at the end of this document.
2019-01-07
Page 4 of 4
CeraLink®
Capacitors for fast-switching semiconductors
L-style
B58031*
Low profile (LP) series
J-style
Manufacturer’s logo
CeraLink type
X.XX = Nominal capacitance (1, 0.5, 0.25)
YYY = Rated voltage (500, 700, 900)
Note that polarity is only for incoming inspection purposes and it does not affect operation. If put under reverse
rated voltage VR, CeraLink is repoled and works identically.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 5 of 5
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Typical characteristics as a function of temperature and voltage VR = 500 V
(VAC = 0.5 VRMS, frequency = 1 kHz)
All given temperatures are device temperatures.
The curves show the relative changes of the capacitance, dissipation factor and ESR. The 100%
values correspond to Ceff,typ and tan δ which are given on page 2 and 3 of this data sheet.
120
120
T [°C]
-25
25
85
125
110
110
100
Capacitance [%]
Capacitance [%]
100
90
80
70
Bias
[VDC]
0
400
500
90
80
70
60
60
50
50
40
0
100
200
300
400
500
-50
-25
0
Voltage [VDC]
600
50
75
100
125
150
600
T [°C]
-25
25
85
125
400
300
200
Bias
[VDC]
0
400
500
500
Dissipation factor [%]
500
Dissipation factor [%]
25
Temperature [°C]
100
400
300
200
100
0
0
0
100
200
300
400
500
-50
-25
0
Voltage [VDC]
25
50
75
100
125
150
Temperature [°C]
500
600
T [°C]
-25
25
85
125
400
Bias
[VDC]
0
400
500
500
ESR [%]
ESR [%]
400
300
200
300
200
100
100
0
0
0
100
200
300
400
500
-50
Voltage [VDC]
0
25
50
75
100
125
150
Temperature [°C]
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
-25
2019-01-07
Page 6 of 6
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Application Notes
Further typical electrical characteristics as a design reference for CeraLink applications.
Typical capacitance values as a function of voltage VR = 500 V
225
Variable
large signal
small signal
200
Capacitance [%]
175
150
125
100
Small signal capacitance:
0.5 VRMS, 1 kHz, 25 °C
The effective capacitance is defined as the small signal
capacitance at Vop.
75
50
0
100
200
300
400
Large signal capacitance:
Quasistatic (slow variation of the voltage), 25 °C
The nominal capacitance is defined as the large signal
capacitance at Vop.
See glossary for further information.
500
Voltage [VDC]
Typical impedance and ESR as a function of frequency VR = 500 V
1000
Variable
Z [Ohm]
ESR [Ohm]
100
VDC = 0 V, VAC = 0.5 VRMS, Tdevice = 25 °C
|Z|, ESR [Ohm]
10
1
0,1
0,01
0,001
1k
10k
100k
Frequency [Hz]
1M
10M
Typical permissible current as a function of frequency VR = 500 V
Tamb
85 °C
105 °C
Normal Operation Current [Arms]
11
10
9
8
7
6
Measurement performed at Vop.
The values correspond to a device temperature
of 150 °C.
No forced cooling was used.
Note hat with additional cooling the typical permissible
current can be significantly higher.
5
4
3
2
0
20
40
60
Frequency [kHz]
80
100
Aging
The capacitance has an aging behavior which shows a decrease of capacitance with time.
The typical aging rate is about 2.5% per logarithmic decade in hours.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 7 of 7
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Typical characteristics as a function of temperature and voltage VR = 700 V
(VAC = 0.5 VRMS, frequency = 1 kHz)
All given temperatures are device temperatures.
The curves show the relative changes of the capacitance, dissipation factor and ESR. The 100%
values correspond to Ceff, typ and tan δ which are given on page 2 and 3 of this data sheet.
130
120
110
100
90
80
70
Bias
[VDC]
0
600
700
120
Capacitance [%]
Capacitance [%]
140
T/°C
-25
25
75
125
100
80
60
60
40
50
40
20
0
100
200
300
400
Voltage [VDC]
500
600
700
T/°C
-25
25
75
125
600
400
300
200
0
50
Temperature [°C]
100
150
Bias
[VDC]
0
600
700
600
500
Dissipation factor [%]
500
Dissipation factor [%]
-50
100
400
300
200
100
0
0
0
100
200
300
400
Voltage [VDC]
500
600
700
500
-50
50
Temperature [°C]
100
150
600
T/°C
-25
25
75
125
400
0
Bias
[VDC]
0
600
700
500
ESR [%]
ESR [%]
400
300
200
300
200
100
100
0
0
0
100
200
300
400
Voltage [VDC]
500
600
700
-50
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
0
50
Temperature [°C]
100
150
2019-01-07
Page 8 of 8
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Application Notes
Further typical electrical characteristics as a design reference for CeraLink applications.
Typical capacitance values as a function of voltage VR = 700 V
Variable
large signal * V
small signal * Bias [V]
200
Capacitance [%]
175
150
125
Large signal capacitance:
Quasistatic (slow variation of the voltage), 25 °C
The nominal capacitance is defined as the large signal
capacitance at Vop.
See glossary for further information.
100
Small signal capacitance:
0.5 VRMS, 1 kHz, 25 °C
The effective capacitance is defined as the small signal
capacitance at Vop.
75
50
0
100
200
300
400
500
Voltage [VDC]
600
700
Typical impedance and ESR as a function of frequency VR = 700 V
Variable
Z [Ohm]
ESR [Ohm]
1000
VDC = 0 V, VAC = 0.5 VRMS, Tdevice = 25 °C
|Z|, ESR [Ohm]
100
10
1
0,1
0,01
0,001
1k
10k
100k
Frequency [Hz]
1M
10M
Typical permissible current as a function of frequency VR = 700 V
Tamb
85 °C
105 °C
Normal Operation Current [Arms]
7
6
5
4
Measurement performed at Vop.
The values correspond to a device temperature
of 150 °C.
No forced cooling was used.
Note that with additional cooling the typical permissible
current can be significantly higher.
3
2
1
0
20
40
60
Frequency [kHz]
80
100
Aging
The capacitance has an aging behavior which shows a decrease of capacitance with time.
The typical aging rate is about 2.5% per logarithmic decade in hours.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 9 of 9
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Typical characteristics as a function of temperature and voltage VR = 900 V
(VAC = 0.5 VRMS, frequency = 1 kHz)
All given temperatures are device temperatures.
The curves show the relative changes of the capacitance, dissipation factor and ESR. The 100%
values correspond to Ceff, typ and tan δ which are given on page 2 and 3 of this data sheet.
140
100
80
Bias [V]
0
800
900
120
110
Capacitance [%]
120
Capacitance [%]
130
T/°C
-25
25
75
125
100
90
80
70
60
60
50
0
100
200
300
400
500
Voltage [VDC]
600
700
800
T/°C
-25
25
75
125
600
500
400
300
200
50
Temperature [°C]
100
150
Bias [V]
0
800
900
600
500
400
300
200
100
100
0
0
700
700
Dissipation Factor [%]
40
-50
900
Dissipation Factor [%]
40
0
100
200
300
400
500
Voltage [VDC]
600
700
800
0
-50
900
500
50
Temperature [°C]
100
150
600
T/°C
-25
25
75
125
400
0
Bias [V]
0
800
900
500
ESR [%]
ESR [%]
400
300
200
300
200
100
100
0
0
100
200
300
400
500
Voltage [VDC]
600
700
800
900
0
-50
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
0
50
Temperature [°C]
100
150
2019-01-07
Page 10 of 10
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Application Notes
Further typical electrical characteristics as a design reference for CeraLink applications.
Typical capacitance values as a function of voltage VR = 900 V
Variable
large signal
small signal
200
Capacitance [%]
175
150
125
100
Large signal capacitance:
Quasistatic (slow variation of the voltage), 25 °C
The nominal capacitance is defined as the large
signal capacitance at Vop.
See glossary for further information.
Small signal capacitance:
0.5 VRMS, 1 kHz, 25 °C
75
50
0
100
200
300
400
500
600
Voltage [VDC]
700
800
The effective capacitance is defined as the small
signal capacitance at Vop.
900
Typical impedance and ESR as a function of frequency VR = 900 V
10000
Variable
Z [Ohm]
ESR [Ohm]
1000
VDC = 0 V, VAC = 0.5 VRMS, Tdevice = 25 °C
|Z|, ESR [Ohm]
100
10
1
0,1
0,01
1k
10k
100k
1M
Frequency [Hz]
10M
Typical permissible current as a function of frequency VR = 900 V
Tamb
85 °C
105 °C
Normal Operation Current [Arms]
5
4
3
Measurement performed at Vop.
The values correspond to a device temperature
of 150 °C.
No forced cooling was used.
Note that with additional cooling the typical
permissible current can be significantly higher.
2
1
0
20
40
60
Frequency [kHz]
80
100
Aging
The capacitance has an aging behavior which shows a decrease of capacitance with time. The typical aging
rate is about 2.5% per logarithmic decade in hours.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 11 of 11
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Reliability
A. Preconditioning:
Reflow solder the capacitor on a PCB using the recommended soldering profile
Check of external appearance
Measurement of electrical parameters Rins, C0, tan δ
o Apply Vpk,max for 7 seconds and measure Rins at room temperature:
Isolation resistance (@ Vpk,max, 7 s, 25 °C)
Rins > 100 MΩ
o Measure C0 and tan δ within 10 minutes to 1 hour afterwards:
Initial capacitance (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C)
Dissipation factor (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C)
B. Performance of a specific reliability test.
C. After performing a specific test:
Check the external appearance again
Repeat the measurement of the electrical parameters
o Apply Vpk,max for 7 seconds and measure Rins at room temperature:
Isolation resistance (@ Vpk,max, 7 s, 25 °C)
Rins > 10 MΩ
o Measure C and tan δ:
Change of initial capacitance (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C) | Δ C / C0 | < 15%
o Dissipation factor (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C)
tan δ < 0.05
Test
Standard
External
appearance
Test conditions
Criteria
Visual inspection with magnifying glass
No defects that might affect
performance
High
temperature
operating life
MIL-STD-202,
method 108
150 °C, VR, 1000 hours
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Biased
humidity
MIL-STD-202,
method 103
85 °C, 85% rel. hum., VR, 1000 hours
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Temperature
shock
IEC 60384-9,
4.8
-55 °C to +150 °C
20 seconds transfer time
15 minutes dwell time
1000 cycles
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Terminal
strength test
AEC-Q200-005 Apply a force of 17.7 N for 60 seconds
PPD PI AE/IE
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Important notes at the end of this document.
No detaching of termination.
No rupture of ceramic
| Δ C / C0 |, tan δ and Rins
within defined limits
2019-01-07
Page 12 of 12
CeraLink®
Capacitors for fast-switching semiconductors
Test
Standard
Tensile
strength test
(unsoldered)
Board flex
B58031*
Low profile (LP) series
Test conditions
Criteria
Apply a force of 10 N in the shown direction.
Ceramic body is clamped :
No detaching of termination.
No rupture of ceramic
| Δ C / C0 |, tan δ and Rins
within defined limits
AEC-Q200-005 Bending of 2 mm for 60 seconds
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Dimensions in mm
Vibration
MIL-STD-202,
method 204
5 g/ 20 min, 12 cycles, 3 axis
10 Hz to 2000 Hz
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
Mechanical
shock
MIL-STD-202,
method 213
Acceleration 400 m/s²
Half sine pulse duration 6 milliseconds
4000 bumps
No mechanical damage
| Δ C / C0 |, tan δ and Rins
within defined limits
3 times recommended reflow soldering
profile
No mechanical damage
Proper solder coating of
contact areas
| Δ C / C0 |, tan δ and Rins
within defined limits
Reflow test
Leaching test
(lead frame
only)
MIL-STD-202,
method 210,
condition B
Dip test of contact areas in solder bath
(260 °C for 10 seconds)
No damage of lead frame
silver coating
Solderability
(lead frame
only)
J-STD-002,
method A @
235 °C,
category 3
Dip test of contact areas in solder bath
(235 °C for 5 ± 0.5 seconds)
> 95% wettability of lead frame
Resistance to
solvent
Dipping and cleaning with isopropanol
Marking must be legible
| Δ C / C0 |, tan δ and Rins
within defined limits
Geometry
Using a caliper
Within specified tolerance in
the chapter construction
PPD PI AE/IE
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Important notes at the end of this document.
2019-01-07
Page 13 of 13
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Packaging
The CeraLink LP types will be delivered in a blister tape (taping to IEC 60286-3).
Blister tape for L-style terminal
Blister tape for J-style terminal
PPD PI AE/IE
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Important notes at the end of this document.
2019-01-07
Page 14 of 14
CeraLink®
Capacitors for fast-switching semiconductors
Part orientation for L-style terminal
B58031*
Low profile (LP) series
Part orientation for J-style terminal
Taping information
Trailer: There is a minimum of 160 mm of carrier tape with empty compartments and sealed by the cover tape.
Leader: There is a minimum of 400 mm of cover tape, which includes at least 100 mm of carrier tape with empty
compartments.
Dimensions in mm
Fixing peeling strength (top tape)
The peeling strength is 0.1 … 1.3 N.
PPD PI AE/IE
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Important notes at the end of this document.
2019-01-07
Page 15 of 15
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Reel packing
L-style terminal
J-style terminal
A
330 ±2
330 ±2
B
100 ±1
62 ±1
C
13 +0.5/ -0.2
12.8 +0.7
D
20.2 min.
19.1 min.
E
2.2 ±0.2
1.6 ±0.5
W
24.2 +2
16.4 +2
Dimensions in mm
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Important notes at the end of this document.
2019-01-07
Page 16 of 16
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Recommended reflow soldering profile
Profile feature
SAC, Sn95.5Ag3.8Cu0.7 @ N2 atmosphere
Preheat and soak
- Temperature min
- Temperature max
- Time
Tsmin
Tsmax
tsmin to tsmax
150 °C
200 °C
60 … 120 seconds
Average ramp-up rate
TL to Tp
3 °C/ second max.
Liquidus temperature
Time at liquidus temperature
TL
tL
217 °C
60 … 150 seconds
Peak package body temperature
Tp
1)
3)
Time (tp) within 5 °C of specified
classification temperature (Tc)
Average ramp-down rate
Time 25 °C to peak temperature
245 °C … 260 °C max.
30 seconds
Tp to TL
2)
3)
6 °C/ second max.
maximum 8 minutes
1) Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
2) Depending on package thickness (cf. JEDEC J-STD-020D).
3) Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Notes:
All temperatures refer to topside of the package, measured on the package body surface.
Max. number of reflow cycles: 3
After the soldering process, the capacitance is lowered. Applying V R to the device will re-establish the capacitance.
The proposed soldering profile is based on IEC 60068-2-58 (respectively JEDEC J-STD-020D) recommendations.
PPD PI AE/IE
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Important notes at the end of this document.
2019-01-07
Page 17 of 17
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
General technical information
Storage
Only store CeraLink capacitors in their original packaging. Do not open the package prior to
processing.
Storage conditions in original packaging: temperature −25 °C to +45 °C, relative humidity ≤ 75%
annual average, maximum 95%, dew precipitation is inadmissible.
Do not store CeraLink capacitors where they are exposed to heat or direct sunlight. Otherwise the
packaging material may be deformed or CeraLink may stick together, causing problems during
mounting.
Avoid contamination of the CeraLink surface during storage, handling and processing.
Avoid storing CeraLink devices in harmful environments where they are exposed to corrosive
gases (e.g. SOx, Cl).
Use CeraLink as soon as possible after opening factory seals such as polyvinyl-sealed packages.
Solder CeraLink components within 6 months after shipment.
Handling
Do not drop CeraLink components or allow them to be chipped.
Do not touch CeraLink with your bare hands - gloves are recommended.
Avoid contamination of the CeraLink surface during handling.
The CeraLink LP series was tested to withstand the board flex test defined in the AEC-Q200 rev.
D, method 005.
The CeraLink LP series uses copper-invar lead frames to prevent mechanical stress to the
ceramic. Too much bending causes open mode. Avoid high mechanical stress like twisting after
soldering on a PCB.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 18 of 18
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Mounting
Do not subject CeraLink devices to mechanical stress when encapsulating them with sealing
material or overmolding with plastic material. Encapsulation may lead to worse heat dissipation
too. Please ask for further information.
Do not scratch the electrodes before, during or after the mounting process.
Make sure contacts and housings used for assembly with CeraLink components are clean before
mounting.
The surface temperature of an operating CeraLink can be higher than the ambient temperature.
Ensure that adjacent components are placed at a sufficient distance from a CeraLink to allow
proper cooling.
Avoid contamination of the CeraLink surface during processing.
Soldering
The use of mild, non-activated fluxes for soldering is recommended, as well as proper cleaning of
the PCB.
Complete removal of flux is recommended to avoid surface contamination that can result in an
insable and/or high leakage current.
Use resin-type or non-activated flux.
Bear in mind that insufficient preheating may cause ceramic cracks.
Rapid cooling by dipping in solvent is not recommended, otherwise a component may crack.
Excessive usage of solder paste can reduce the mechanical robustness of the device, whereas
insufficient solder may cause the CeraLink to detach from the PCB. Use an adequate amount of
solder paste, but on the landing pads only.
If an unsuitable cleaning fluid is used, flux residue or foreign particles may stick to the CeraLink
surface and deteriorate its insulation resistance. Insufficient or improper cleaning of the CeraLink
may cause damage to the component.
o
Excessive washing like ultrasonic cleaning, can affect the connection between the ceramic
chip and the outer electrode. To avoid this, we give the following recommendation: Power:
20 W/l max.
o Frequency: 40 kHz max.
o Washing time: 5 minutes max.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 19 of 19
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Glossary
Initial capacitance C0:
Effective capacitance Ceff:
Nominal capacitance Cnom:
Is the value at the origin of the hysteresis without any applied direct
voltage.
Occurs at Vop and is measured with an applied ripple voltage of
0.5 VRMS and 1 kHz. The CeraLink is designed to have its highest
capacitance value at the operating voltage Vop.
Is the value derived by the tangent of the mean hysteresis as the
derivative of the mean hysteresis is dQ/dV ~ C.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 20 of 20
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Symbols and terms
AC
C0
Ceff,typ
Cnom,typ
DC
ESL
ESR
Iop
LP
PCB
PLZT
Rins
Rins, typ
SAC
Tamb
tan δ
Tdevice
Vop
VR
VRMS
Vpk,max
ΔT
Alternating current
Initial capacitance @ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C
Typical effective capacitance @ Vop, 0.5 VRMS, 1 kHz, 25 °C
Typical nominal capacitance @ Vop, quasistatic, 25 °C. See glossary on
previous page for definition of the nominal capacitance
Direct current
Equivalent serial inductance
Equivalent serial resistance
Operating ripple current, root mean square value of sinusoidal AC current
Low profile
Printed circuit board
Lead lanthanum zirconium titanate
Insulation resistance @ Vpk, measurement time t = 7 s, 25 °C
Insulation resistance @ Vop, measurement time t > 240 s, 25 °C
Tin silver copper alloy; lead-free solder paste
Ambient temperature
Dissipation factor @ 0 Vdc, 0.5 Vrms 1 kHz, 25°C
Device temperature. Tdevice = Tamb + ΔT (ΔT defines the self-heating of the device
due to applied current).
Operating voltage
Rated voltage
Root mean square value of sinusoidal AC voltage
Maximum peak operating voltage
Increase of temperature during operation
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 21 of 21
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Cautions and warnings
General
Not for use in resonant circuits, where a voltage of alternating polarity occurs.
Not for AC applications. Consult our local representative for further details.
If used in snubber circuits, ensure that the sum of all voltages remains at the same polarity.
Some parts of this publication contain statements about the suitability of our CeraLink components for
certain areas of application, including recommendations about incorporation/design-in of these
products into customer applications. The statements are based on our knowledge of typical
requirements often made of our CeraLink devices in the particular areas. We nevertheless expressly
point out that such statements cannot be regarded as binding statements about the suitability of our
CeraLink components for a particular customer application. As a rule, TDK is either unfamiliar with
individual customer applications or less familiar with them than the customers themselves. For these
reasons, it is always incumbent on the customer to check and decide whether the CeraLink devices
with the properties described in the product specification are suitable for use in a particular customer
application.
Do not use CeraLink components for purposes not identified in our specifications.
Ensure the suitability of a CeraLink in particular by testing it for reliability during design-in.
Always evaluate a CeraLink™ component under worst-case conditions.
Pay special attention to the reliability of CeraLink devices intended for use in safety-critical
applications (e.g. medical equipment, automotive, spacecraft, nuclear power plant).
Design notes
Consider derating at higher operating temperatures. As a rule, lower temperatures and voltages
increase the life time of CeraLink devices.
If steep surge current edges are to be expected, make sure your design is as low-inductive as
possible.
In some cases the malfunctioning of passive electronic components or failure before the end of
their service life cannot be completely ruled out in the current state of the art, even if they are
operated as specified. In applications requiring a very high level of operational safety and
especially when the malfunction or failure of a passive electronic component could endanger
human life or health (e.g. in accident prevention, life-saving systems, or automotive battery line
applications such as clamp 30), ensure by suitable design of the application or other measures
(e.g. installation of protective circuitry, fuse or redundancy) that no injury or damage is sustained
by third parties in the event of such a malfunction or failure.
Specified values only apply to CeraLink components that have not been subject to prior electrical,
mechanical or thermal damage. The use of CeraLink devices in line-to-ground applications is
therefore not advisable, and it is only allowed together with safety countermeasures such as
thermal fuses.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 22 of 22
CeraLink®
Capacitors for fast-switching semiconductors
B58031*
Low profile (LP) series
Operation
Use CeraLink only within the specified operating temperature range.
Use CeraLink only within specified voltage and current ranges.
The CeraLink has to be operated in a dry atmosphere, which must not contain any additional
chemical vapors or substances.
Environmental conditions must not harm the CeraLink. Use the capacitors under normal
atmospheric conditions only. A reduction of the oxygen partial pressure to below 1 mbar is not
permissible.
Prevent a CeraLink from contacting liquids and solvents.
Avoid dewing and condensation.
During operation, the CeraLink can produce audible noise due to its piezoelectric characteristic.
CeraLink components are mainly designed for encased applications. Under all circumstances
avoid exposure to:
o
o
o
o
o
direct sunlight
rain or condensation
steam, saline spray
corrosive gases
atmosphere with reduced oxygen content
This listing does not claim to be complete, but merely reflects the experience of TDK.
Display of ordering codes for TDK Electronics products
The ordering code for one and the same product can be represented differently in data sheets, data books,
other publications, on the company website, or in order-related documents such as shipping notes, order
confirmations and product labels. The varying representations of the ordering codes are due to
different processes employed and do not affect the specifications of the respective products.
Detailed information can be found on the Internet under www.tdk-electronics.tdk.com/orderingcodes.
PPD PI AE/IE
Please read Cautions and warnings and
Important notes at the end of this document.
2019-01-07
Page 23 of 23
Important notes
The following applies to all products named in this publication:
1. Some parts of this publication contain statements about the suitability of our products for
certain areas of application. These statements are based on our knowledge of typical
requirements that are often placed on our products in the areas of application concerned. We
nevertheless expressly point out that such statements cannot be regarded as binding
statements about the suitability of our products for a particular customer application. As a
rule we are either unfamiliar with individual customer applications or less familiar with them than
the customers themselves. For these reasons, it is always ultimately incumbent on the customer
to check and decide whether a product with the properties described in the product specification is
suitable for use in a particular customer application.
2. We also point out that in individual cases, a malfunction of electronic components or failure
before the end of their usual service life cannot be completely ruled out in the current state
of the art, even if they are operated as specified. In customer applications requiring a very high
level of operational safety and especially in customer applications in which the malfunction or
failure of an electronic component could endanger human life or health (e.g. in accident
prevention or life-saving systems), it must therefore be ensured by means of suitable design of the
customer application or other action taken by the customer (e.g. installation of protective circuitry
or redundancy) that no injury or damage is sustained by third parties in the event of malfunction or
failure of an electronic component.
3. The warnings, cautions and product-specific notes must be observed.
4. In order to satisfy certain technical requirements, some of the products described in this
publication may contain substances subject to restrictions in certain jurisdictions (e.g.
because they are classed as hazardous). Useful information on this will be found in our Material
Data Sheets on the Internet (www.tdk-electronics.tdk.com/material). Should you have any more
detailed questions, please contact our sales offices.
5. We constantly strive to improve our products. Consequently, the products described in this
publication may change from time to time. The same is true of the corresponding product
specifications. Please check therefore to what extent product descriptions and specifications
contained in this publication are still applicable before or when you place an order.
We also reserve the right to discontinue production and delivery of products. Consequently,
we cannot guarantee that all products named in this publication will always be available.
The aforementioned does not apply in the case of individual agreements deviating from the
foregoing for customer-specific products.
6. Unless otherwise agreed in individual contracts, all orders are subject to our General Terms
and Conditions of Supply.
7. Our manufacturing sites serving the automotive business apply the IATF 16949 standard.
The IATF certifications confirm our compliance with requirements regarding the quality
management system in the automotive industry. Referring to customer requirements and
customer specific requirements (“CSR”) TDK always has and will continue to have the policy of
respecting individual agreements. Even if IATF 16949 may appear to support the acceptance of
unilateral requirements, we hereby like to emphasize that only requirements mutually agreed
upon can and will be implemented in our Quality Management System. For clarification
purposes we like to point out that obligations from IATF 16949 shall only become legally binding if
individually agreed upon.
Page 24 of 24
Important notes
8. The trade names EPCOS, CeraCharge, CeraDiode, CeraLink, CeraPad, CeraPlas, CSMP, CTVS,
DeltaCap, DigiSiMic, ExoCore, FilterCap, FormFit, LeaXield, MiniBlue, MiniCell, MKD, MKK,
MotorCap, PCC, PhaseCap, PhaseCube, PhaseMod, PhiCap, PowerHap, PQSine, PQvar,
SIFERRIT, SIFI, SIKOREL, SilverCap, SIMDAD, SiMic, SIMID, SineFormer, SIOV, ThermoFuse,
WindCap are trademarks registered or pending in Europe and in other countries. Further
information will be found on the Internet at www.tdk-electronics.tdk.com/trademarks.
Release 2018-10
Page 25 of 25
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