S1D15E06T00A00A

MF1393-05 S1D15E06 Series Rev. 2.1 NOTICE No part of this material may be reproduced or duplicated in any from or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notics. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no repersesnation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. ©SEIKO EPSON CORPORATION 2003, All rights reserved. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. Rev. 2.1 SED1575 Series Contents 1. DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. BLOCK DIAGRAM ............................................................................................................................................. 2 4. PIN ASSIGNMENT ............................................................................................................................................ 3 5. PIN DESCRIPTION ........................................................................................................................................... 7 6. FUNCTIONAL DESCRIPTION ........................................................................................................................ 11 7. COMMAND ...................................................................................................................................................... 27 8. ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 50 9. DC CHARACTERISTICS ................................................................................................................................. 51 10. TIMING CHARACTERISTICS ......................................................................................................................... 58 11. MPU INTERFACE (Reference example) ......................................................................................................... 66 12. CONNECTION BETWEEN LCD DRIVERS (Reference example) .................................................................. 67 13. LCD PANEL WIRING (Reference example) .................................................................................................... 68 14. S1D15E06T00A*** TCP PIN LAYOUT ........................................................................................................ 69 15. TCP DIMENSIONS (Reference example) ....................................................................................................... 70 16. CAUTIONS ...................................................................................................................................................... 71 –i– Rev. 2.1 S1D15E06 Series 1. DESCRIPTION The S1D15E06 series is a single chip MLS driver for dot matrix liquid crystal displays which can be directly connected to the microcomputer bus. It accepts the 8bit parallel or serial display data from the microcomputer to store the data in the on-chip display data RAM, and issues liquid crystal drive signals independently of the microcomputer. The S1D15E06 series provides both 4 gray-scale display and binary display. It incorporates a display data RAM (132 × 160 × 2 bits). In the case of 4 gray-scale display, 2 bits of the on-chip RAM respond to one-dot pixels, while in the case of binary display, 1 bit of the on-chip RAM respond to one-dot pixels. The S1D15E06 series features 132 common output circuits and 160 segment output circuits. A single chip provides a display of 10 characters by 8 lines with 132 × 160 dots (16 × 16 dots) and display of 13 characters by 11 lines by the 12 × 12 dot-character font. Display data RAM read/write operations do not require operation clock from outside, thereby ensuring operation with the minimum current consumption. Furthermore, it incorporates a LCD-drive power supply characterized by low power consumption and a CR oscillator circuit for display clock; therefore, the display system of a handy and high-performance instrument can be realized by use of the minimum current consumption and minimum chip configuration. 2. FEATURES • Direct RAM data display by display data RAM • 4 gray-scale display (Normally white in normal display mode) RAM bit data (high order and low order) (1,1) : gray-scale 3, black (1,0) : gray-scale 2 (0,1) : gray-scale 1 (0,0) : gray-scale 0, white • Binary display (Normally white display is in normal mode) RAM bit data “1” : On and black “0” : Off and white • RAM capacity 132 × 160 × 2 = 42,240 bits • Liquid crystal drive circuit 132 common outputs and 160 segment outputs • High-speed 8-bit MPU interface (directly connectable to the MPUs of both 80/68 series) /serial interface possible • A variety of command functions Area scroll display, partial display, n-line reversal, display data RAM address control, contrast control, display ON/OFF, display normal/reverse rotation, display all lighting ON/OFF, liquid crystal drive power supply circuit control, display clock built-in oscillator circuit control • Lower power MLS drive technology Built-in high precision voltage regulation function • High precision CR oscillator circuit incorporated • Very low power consumption • Power supply Logic power supply: VDD – VSS = 1.7 to 3.6 V Liquid crystal drive power supply: V3 – VSS = 3.4 to 14.0 V (S1D15E06D01****), V3 – VSS = 3.4 to 16.0 V (S1D15E06D03****) • Wide operation temperature range: –40 to 85°C • CMOS process • Shipping form : Bare chips, TCP • Light and radiation proof measures are not taken in designing. Series specifications Product name S1D15E06D01B000 S1D15E06D03B000 S1D15E06D01E000 S1D15E06D03E000 S1D15E06T00A00A Bias 1/7 1/7 1/7 1/7 1/7 LCD driving voltage range 3.4V~14.0V 3.4V~16.0V 3.4V~14.0V 3.4V~16.0V 3.4V~14.0V Duty (Max.) Form of shipping 1/132 1/132 1/132 1/132 1/132 Bare chip Bare chip Bare chip Bare chip TCP Chip thickness 0.400mm 0.400mm 0.625mm 0.625mm — Rev. 2.1 EPSON 1 S1D15E06 Series 3. BLOCK DIAGRAM VDD VSS V3 V2 V1 VC MV1 MV2 MV3 (VSS) SEG Drivers COM Drivers Decode circuit Display data latch circuit CAP1+ Power supply circuit CAP1– CAP2+ CAP2– VOUT CAP3+ CAP3– CAP4+ CAP4– Display timing generator circuit COM131 SEG159 COM0 SEG0 FR CA F1 F2 CL DOF M/S Page address Display data RAM 160 x 132 x 2 Column address Line address I/O buffer Oscillator circuit CLS Bus holder Command decoder Status MPU Interface D6 (SCL) WR (R/W) D7 (SI) RD (E) RES CS1 CS2 C86 P/S D5 D4 D3 D2 D1 2 EPSON D0 A0 Rev. 2.1 S1D15E06 Series 4. PIN ASSIGNMENT 4.1 Chip Assignment 98 99 D15E6D1B Die No. (0, 0) 166 167 344 345 1 412 S1D15E06 Series Item Chip size Chip thickness Bump pitch Bump size PAD No.1 to 98 PAD No.99 to 166, 345 to 412 PAD No.167 to 175, 336 to 344 PAD No.176 to 335 Bump height Size X Y 10.26 × 3.98 0.4/0.625 50 (Min.) 70 × 92 116 × 33 61 × 61 33 × 116 22.5 (Typ.) Unit mm mm µm µm µm µm µm µm 4.2 Alignment mark Alignment coordinate 1 (–4761.4, 1830.0) µm 2 ( 4926.0, –1819.1) µm Mark size a = 80 µm b = 20 µm b a Rev. 2.1 EPSON 3 S1D15E06 Series 4.3 Pad Center Coordinates Unit: µm PAD Pin No. Name 1 NC 2 NC 3 TEST0 4 TEST1 5 TEST2 6 TEST3 7 TEST4 8 TEST5 9 VSS 10 TEST6 11 TEST7 12 TEST8 13 TEST9 14 TEST10 15 TEST11 16 TEST12 17 TEST13 18 TEST14 19 TEST15 20 TEST16 21 TEST17 22 TEST18 23 VSS 24 FR 25 CL 26 DOF 27 F1 28 F2 29 CA 30 VSS 31 TEST 32 CS1 33 RES 34 A0 35 WR, R/W 36 RD, E 37 CS2 38 VDD 39 M/S 40 VSS 41 CLS 42 VDD 43 C86 44 VSS 45 P/S 46 VDD 47 D0 48 D1 49 D2 50 D3 X 4494 4402 4310 4218 4126 4034 3942 3850 3742 3634 3542 3450 3358 3266 3174 3082 2990 2898 2806 2714 2622 2530 2422 2314 2222 2130 2038 1946 1854 1762 1670 1578 1486 1394 1302 1210 1118 1026 934 842 750 658 566 474 382 290 198 106 14 –78 Y 1830 PAD Pin No. Name 51 D4 52 D5 53 D6, SCL 54 D7, SI 55 VSS 56 VSS 57 VSS 58 VDD 59 VDD 60 VDD 61 VOUT 62 VOUT 63 CAP1+ 64 CAP1+ 65 CAP1– 66 CAP1– 67 CAP2– 68 CAP2– 69 CAP2+ 70 CAP2+ 71 CAP3+ 72 CAP3+ 73 CAP3– 74 CAP3– 75 CAP4– 76 CAP4– 77 CAP4+ 78 CAP4+ 79 V3 80 V3 81 V2 82 V2 83 V1 84 V1 85 VC 86 VC 87 MV1 88 MV1 89 MV2 90 MV2 91 MV3 92 MV3 93 CPP+ 94 CPP– 95 CPM+ 96 CPM– 97 NC 98 NC 99 NC 100 COM65 X Y PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Pin X Name COM64 –4958 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 Y 1575 1525 1475 1425 1375 1325 1275 1225 1175 1125 1075 1025 975 925 875 825 775 725 675 625 575 525 475 425 375 325 275 225 175 125 75 25 –25 –75 –125 –175 –225 –275 –325 –375 –425 –475 –525 –575 –625 –675 –725 –775 –825 –875 –170 1830 –262 –354 –446 –538 –630 –722 –814 –906 –998 –1090 –1182 –1274 –1366 –1458 –1550 –1642 –1734 –1826 –1918 –2010 –2102 –2194 –2286 –2378 –2470 –2562 –2654 –2746 –2838 –2930 –3022 –3114 –3206 –3298 –3390 –3482 –3574 –3666 –3758 –3850 –3942 –4034 –4126 –4218 –4310 –4402 –4494 –4958 1675 1625 4 EPSON Rev. 2.1 S1D15E06 Series Unit: µm PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pin Name COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 NC NC NC NC NC NC NC NC NC NC SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 X Y PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Pin Name SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 X Y PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Pin Name SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 X Y –4958 –925 –975 –1025 –1075 –1125 –1175 –1225 –1275 –1325 –1375 –1425 –1475 –1525 –1575 –1625 –1675 –4704 –1846 –4621 –4539 –4456 –4374 –4291 –4209 –4126 –4044 –3975 –1818 –3925 –3875 –3825 –3775 –3725 –3675 –3625 –3575 –3525 –3475 –3425 –3375 –3325 –3275 –3225 –3175 –3125 –3075 –3025 –2975 –2925 –2875 –2825 –2775 –2725 –1818 –2675 –2625 –2575 –2525 –2475 –2425 –2375 –2325 –2275 –2225 –2175 –2125 –2075 –2025 –1975 –1925 –1875 –1825 –1775 –1725 –1675 –1625 –1575 –1525 –1475 –1425 –1375 –1325 –1275 –1225 –1175 –1125 –1075 –1025 –975 –925 –875 –825 –775 –725 –675 –625 –575 –525 –475 –425 –375 –325 –275 –225 –1818 –175 –125 –75 –25 25 75 125 175 225 275 325 375 425 475 525 575 625 675 725 775 825 875 925 975 1025 1075 1125 1175 1225 1275 1325 1375 1425 1475 1525 1575 1625 1675 1725 1775 1825 1875 1925 1975 2025 2075 2125 2175 2225 Rev. 2.1 EPSON 5 S1D15E06 Series Unit: µm PAD No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 Pin Name SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 NC NC NC NC NC NC NC NC NC NC COM66 COM67 COM68 COM69 COM70 X Y PAD No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 Pin X Y Name COM71 4958 –1375 COM72 –1325 COM73 –1275 COM74 –1225 COM75 –1175 COM76 –1125 COM77 –1075 COM78 –1025 COM79 –975 COM80 –925 COM81 –875 COM82 –825 COM83 –775 COM84 –725 COM85 –675 COM86 –625 COM87 –575 COM88 –525 COM89 –475 COM90 –425 COM91 –375 COM92 –325 COM93 –275 COM94 –225 COM95 –175 COM96 –125 COM97 –75 COM98 –25 COM99 25 COM100 75 COM101 125 COM102 175 COM103 225 COM104 275 COM105 325 COM106 375 COM107 425 COM108 475 COM109 525 COM110 575 COM111 625 COM112 675 COM113 725 COM114 775 COM115 825 COM116 875 COM117 925 COM118 975 COM119 1025 COM120 1075 PAD No. 401 402 403 404 405 406 407 408 409 410 411 412 Pin X Name COM121 4958 COM122 COM123 COM124 COM125 COM126 COM127 COM128 COM129 COM130 COM131 NC Y 1125 1175 1225 1275 1325 1375 1425 1475 1525 1575 1625 1675 2275 –1818 2325 2375 2425 2475 2525 2575 2625 2675 2725 2775 2825 2875 2925 2975 3025 3075 3125 3175 3225 3275 3325 3375 3425 3475 3525 3575 3625 3675 3725 3775 3825 3875 3925 3975 4044 –1846 4126 4209 4291 4374 4456 4539 4621 4704 4958 –1675 –1625 –1575 –1525 –1475 –1425 6 EPSON Rev. 2.1 S1D15E06 Series 5. PIN DESCRIPTION 5.1 Power Pin Pin name VDD I/O Description Connect to system MPU power supply pin VCC. Connect to the system GND. MV3 is short circuited with MV3 inside the IC chip. A liquid crystal drive multi-level power supply. The voltages determined by the liquid crystal cell are impedance-converted by resistive divider and operational amplifier for application. The following order must be maintained: V3 ≥ V2 ≥ V1 ≥ VC ≥ MV1 ≥ MV2 ≥ MV3 (=VSS) Master operation: When power supply is turned on, the following voltage is applied to each pin by the built-in power supply circuit. MV3 is connected to with VSS inside the IC chip. V2 V1 VC MV1 MV2 11/14 • V3 9/14 • V3 7/14 • V3 5/14 • V3 3/14 • V3 Power supply Power VSS supply V3, V2, V1, Power VC, MV1, supply MV2, MV3, (=VSS) Number of pins 6 8 14 (2 each) 5.2 LCD Power Supply Circuit Pin Number of pins 2 2 2 2 2 2 2 2 2 1 1 1 1 Pin name CAP1+ CAP1– CAP2+ CAP2– VOUT CAP3+ CAP3– CAP4+ CAP4– CPP+ CPP– CPM+ CPM– I/O O O O O O O O O O O O O O Description Pin connected to the positive side of the step-up capacitor. Connect the capacitor between this pin and CAP1– pin. Pin connected to the negative side of the step-up capacitor. Connect the capacitor between this pin and CAP1+ pin. Pin connected to the positive side of the step-up capacitor. Connect the capacitor between this pin and CAP2– pin. Pin connected to the negative side of the step-up capacitor. Connect the capacitor between this pin and CAP2+ pin. Output pin for step-up. Connect the capacitor between this pin and VDD. Pin connected to the positive side of the step-up capacitor. Connect the capacitor between this pin and CAP3– pin. Pin connected to the negative side of the step-up capacitor. Connect the capacitor between this pin and CAP3+ pin. Pin connected to the positive side of the step-up capacitor. Connect the capacitor between this pin and CAP4– pin. Pin connected to the negative side of the step-up capacitor. Connect the capacitor between this pin and CAP4+ pin. Keep it open. Keep it open. Keep it open. Keep it open. Rev. 2.1 EPSON 7 S1D15E06 Series 5.3 System Bus Connection Pin Pin name D7 to D0 (SI) (SCL) I/O I/O Description Connects to the 8-bit or 16-bit MPU data bus via the 8-bit bi-directional data bus. When the serial interface is selected (P/S = LOW), D7 serves as the serial data input (SI) and D6 serves as the serial clock input (SCL), In this case, D0 through D5 go to a high impedance state. When the Chip select is inactive, D0 through D7 go to a high impedance state. Normally, the least significant bit MPU address bus is connected to distinguish between data and command. A0 = HIGH : indicates that D0 to D7 are display data or command parameters. A0 = LOW : indicates that D0 to D7 are control commands. When the RES is LOW, initialization is achieved. Resetting operation is done on the level of the RES signal. A chip select signal. When CS1 = LOW and CS2 = HIGH, signals are active, and data/command input/output are enabled. • When the 80 series MPU is connected. A pin for connection of the RD signal of the 80 series MPU. When this signal is LOW, the data bus of the S1D15E06 series is in the output state. • When the 68 series MPU is connected. Serves as a 68 series MPU enable clock input pin. • When the 80 series MPU is connected. A pin for connection of the WR signal of the 80 series MPU. Signals on the data bus are latched at the leading edge of the WR signal. • Serves as a read/write control signal input pin when the 68 series MPU is connected. R/W = HIGH : Read R/W = LOW : Write A MPU interface switching pin. C86 = HIGH : 68 series MPU interface C86 = LOW : 80 series MPU interface Parallel data input/serial data input select pin P/S = HIGH : Parallel data input P/S = LOW : Serial data input The following Table shows the summary: P/S Data/Command HIGH A0 LOW A0 Data D0 to D7 SI (D7) Read/Write Serial clock RD, WR Write only SCL (D6) Number of pins 8 A0 I 1 RES CS1 CS2 RD (E) I I I 1 2 1 WR (R/W) I 1 C86 I 1 P/S I 1 When P/S = LOW, D0 to D5 are high impedance. D0 to D5 can be HIGH, LOW or open. RD(E) and WR(R/W) are locked to HIGH or LOW. The serial data input does not allow the RAM display data to be read. 8 EPSON Rev. 2.1 S1D15E06 Series Number of pins 1 Pin name CLS I/O I Description A pin used to select Enable/Disable state of the built-in oscillator circuit for display clock. CLS = HIGH : Built-in oscillator circuit Enabled CLS = LOW : Built-in oscillator circuit Disabled (External input) When CLS is LOW, display clock is input from the CL pin. When the S1D15E06 series is used in the master/slave mode, each CLS pins must be set to the same level. Display clock Built-in oscillator circuit used External input Master HIGH LOW Slave HIGH LOW M/S I A pin used to select the master/slave operation for S1D15E06 series. Liquid crystal display system is synchronized when the master operation outputs the timing signal required for liquid crystal display, while the slave operation inputs the timing signal required for liquid crystal display. M/S = HIGH : Master operation M/S = LOW : Slave operation The following Table shows the relation in conformance to the M/S and CLS: M/S HIGH CLS Oscillation circuit Enabled Disabled Disabled Disabled Power circuit Enabled Enabled Disabled Disabled CL Output Input Input Input FR, DOF, F1, F2, CA Output Output Input Input 1 HIGH LOW HIGH LOW LOW CL I/O The slave power supply circuit can also operate, but do not use it. Display clock input/output pin. The following Table shows the relation in conformance to the M/S and CLS state: CLS HIGH HIGH LOW HIGH LOW LOW M/S CL Output Input Input Input 1 FR I/O F1, F2, CA I/O DOF I/O When you want to use the S1D15E06 series in the master/slave mode, connect each CL pin. A liquid crystal alternating current input/output pin. M/S = HIGH : Output M/S = LOW : Input When you want to use the S1D15E06 series in the master/slave mode, connect each FR pin. A liquid crystal sync signal input/output pin. M/S = HIGH : Output M/S = LOW : Input When you want to use the S1D15E06 series in the master/slave mode, connect each F1, F2 and CA pins. A liquid crystal blanking control pin. M/S = HIGH : Output M/S = LOW : Input When you want to use the S1D15E06 series in the master/slave mode, connect each DOF pin. 1 3 (1 each) 1 Rev. 2.1 EPSON 9 S1D15E06 Series 5.4 Liquid crystal drive pin Pin name SEG0 to SEG159 COM0 to COM131 I/O O Description Liquid crystal segment drive output pins. One of the V2, V1, VC, MV1, and MV2 levels is selected by a combination of the display RAM content and FR/F1/F2 signals. Liquid crystal common drive output pins. One of the V3, VC, MV3 (VSS) levels is selected by a combination of the scan data and FR/F1/F2 signals. Number of pins 160 O 132 5.5 Test pins Pin name TEST, TEST2 to 5 TEST0, 1, 6 to 18 I/O I I/O Description IC chip test pins. Lock them to LOW. IC chip test pins. Open them and make sure that the capacity is not consumed by wiring, etc. Number of pins 5 15 10 EPSON Rev. 2.1 S1D15E06 Series 6. FUNCTIONAL DESCRIPTION 6.1 MPU Interface 6.1.1 Selection of Interface Type S1D15E06 series allows data to be sent via the 8-bit bi-directional data buses (D7 to D0) or serial data input (SI). By setting the polarity of the P/S pin to HIGH or LOW, you can select either 8-bit parallel data input or serial data input, as shown in Table 6.1. Table 6.1 P/S HIGH : Parallel input LOW : Serial input CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD WR C86 D7 D6 D5 to D0 RD WR C86 D7 D6 D5 to D0 — — — SI SCL (HZ) —: Fixed to HIGH or LOW HZ: High impedance state 6.1.2 parallel interface When the parallel interface is selected (P/S = HIGH), direction connection to the MPU bus of either 80 series MPU or 68 series MPU is performed by setting the 86 pin to either HIGH or LOW, as shown in Table 6.2. Table 6.2 P/S HIGH : 68 series MPU bus LOW : 80 series MPU bus CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD E RD WR R/W WR D7 to D0 D7 to D0 D7 to D0 The data bus signals are identified by a combination of A0, RD (E), and WR (R/W) signals as shown in Table 6.3. Table 6.3 Common A0 1 1 0 68 series R/W 1 0 1 0 1 1 80 series RD WR 1 0 0 Function Display data read, status read Display data write, command parameter write Command write 6.1.3 Serial interface When the serial interface is selected (P/S =LOW), the chip is active (CS1 = LOW, CS2 = HIGH), and reception of serial data input (SI) and serial clock input (SCL) is enabled. Serial interface comprises a 8-bit shift register and 3-bit counter. The serial data are latched by the rising edge of serial clock signals in the order of D7, D6, .... and D0 starting from the serial data input pin. On the rising edge of 8th serial clock signal, they are converted into 8-bit parallel data to be processed. Whether serial data input is a display data or command is identified by A0 input. A0 = HIGH indicates display data, while A0 = LOW shows command data. The A0 input is read and identified at every 8 × n-th rising edge of the serial clock after the chip has turned active. Fig. 6.1 shows the serial interface signal chart. Rev. 2.1 EPSON 11 S1D15E06 Series CS1 CS2 SI SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 A0 Fig. 6.1 * When the chip is inactive, the counter is reset to the initials state. * Reading is not performed in the case of serial interface. * For the SCL signal, a sufficient care must be taken against terminal reflection of the wiring and external noise. Recommend to use an actual equipment to verify the operation. 6.1.4 Chip Selection The S1D15E06 series has two chip select pins; CS1 and CS2. MPU interface or serial interface is enabled only when CS1 = LOW and CS2 = HIGH. When the chip select pin is inactive, D0 to D5 are in the state of high impedance, while A0, RD and WR inputs are disabled. When serial interface is selected, the shift register and counter are reset. 6.1.5 Access to display data RAM and internal register Access to S1D15E06 series viewed from the MPU side is enabled only if the cycle time requirements are kept. This does not required waiting time; hence, high-speed data transfer is allowed. Furthermore, at the time of data transfer with the MPU, S1D15E06 series provides a kind of inter-LSI pipe line processing via the bus holder accompanying the internal data bus. For example, when data is written to the display data RAM by the MPU, the data is once held by the bus holder. It is written to the display data RAM before the next data write cycle comes. On the other hand, when the MPU reads the content of the display data RAM, it is read in the first data read cycle (dummy), and the data is held in the bus holder. Then it is read onto on the system bus from the bus holder in the next data read cycle. Restrictions are imposed on the display data RAM read sequence. When the address has been set, specified address data is not output to the Read command immediately after that. The specified address data is output in the second data reading. This must be carefully noted. Therefore, one dummy read operation is mandatory subsequent to address setting or write cycle. Fig. 6.2 illustrates this relationship. 12 EPSON Rev. 2.1 S1D15E06 Series Write A0 MPU WR DATA White Latch N N+1 N+2 Internal timing Command BUS Holder Write Signal N N+1 N+2 Read A0 WR MPU RD DATA Read Command Dumy n n+1 Internal timing Read Signal Column Address Bus Holder Preset N Read command code Increment N+1 n n+1 N+2 n+2 Dummy Read Data Read Data Read Fig. 6.2 6.2 Display data RAM 6.2.1 Display Data RAM This is a RAM to store the display dot data, and comprises 132 × 160 × 2 bits. Access to the desired bit is enabled by specifying the page address and column address. When the 4 gray-scale is selected by the Display Mode command, display data input for gray-scale display are processed as a two-bit pair. Combination is as follows: (MSB, LSB) = (D1,D0), (D3,D2), (DS,D4), (D7,D6) When the RAM bit data is gray-scale 1 and 2, gray-scale display is realized according to the parameter of the Gray-scale Pattern Set command. RAM bit data (high order and low order) (1,1) : gray-scale 3 Black (when display is in normal mode) (1,0) : gray-scale 2 (0,1) : gray-scale 1 (0,0) : gray-scale 0 White (when display is in normal mode) When binary display is selected by the Display Mode command, the RAM 1 bit built in the one-dot pixel responds to it. When the RAM bit data is “1”, the display is black. If it is “0”, the display is given in white. RAM bit data “1” : Light On Black (when display is in normal mode) “0” : Light Off White (when display is in normal mode) Rev. 2.1 EPSON 13 S1D15E06 Series Display data D7 to D0 from the MPU correspond to LCD common direction, as shown in Fig. 6.3 and 6.4. Therefore, less restrictions when multi-chip usage. Furthermore, read/write operations from the MPU to the RAM are carried out via the input/output buffer. The read operation from Display data RAM is designed as an independent operation. Accordingly, even if the MPU accesses the RAM asynchronously during LCD display, no adverse effect is given to display. (D1,D0) (0,0) (1,1) (1,1) (D3,D2) (1,1) (0,0) (0,0) (D5,D4) (0,0) (1,0) (0,1) (D7,D6) (0,0) (0,0) (0,0) Display data RAM (0,0) (0,0) (0,0) (0,0) COM0 COM1 COM2 COM3 LCD Fig. 6.3 4 gray-scale D0 D1 D2 D3 D4 0111 1000 0000 0111 1000 0 0 0 0 0 COM0 COM1 COM2 COM3 COM4 Display data RAM LCD Fig. 6.4 Binary 6.2.2 Gray-scale display When the 4 gray-scale is selected by the Display Mode command, gray-scale is represented by the FRM control carried out according to the gray-scale data written in the display data RAM. Of the 4 gray-scale, 2 gray-scale of halftones (grayscale 2 and 1) has its level of contrast specified by the Gray-scale Set command. Gray-scale can be selected from 6 levels of contrast. 6.2.3 Page address circuit/column address circuit The address of the display data RAM to be accessed is specified by the Page Address Set command and Column Address Set command, as shown in Fig. 6.5 and Fig. 6.6. For Address incremental direction, either the column direction or page direction can be selected by the Address Direction command. Whichever direction is chosen, increment is carried out by positive one (+1) after write or read operation. When the column direction is selected for address increment, the column address is increased by +1 for every write or read operation. After the column address has accessed up to 9FH, the page address is incremented by +1 and the column address shifts to 0H. When the page direction is selected for address increment, the page address is increased with the column address locked in position. When the page address has accessed up to 32H, the column address is incremented by +1, and the page address goes to 0H. Whichever direction is selected for address increment, the page address goes back to 0H and the column address to 0H after access up to the column address 9FH of page address 32H. As shown in Fig. 6.4, relationship between the display data RAM column address and segment output can be reversed by the Column Address Set Direction command. This will reduce restrictions on IC layout during LCD module assembling. 14 EPSON Rev. 2.1 S1D15E06 Series Table 6.4 SEG output ADC “0” (D0) “1” SEG0 SEG159 0(H)→ Column Address →9F(H) 9F(H)← Column Address ←0(H) dynamic modification of the line address, screen scroll and page change are enabled. 6.2.5 Area scroll The display area can be divided into the display area fixed in the COM direction and scrollable area by the area scroll command. The scroll area is set by a scroll mode, scroll start line address (AS), scroll end address (AE), and scroll display line count (AL) as parameters for the area scroll command. Display start line address (DL) in the scroll area can be specified by the display start line address set command. 6.2.4 Line address circuit The line address circuit specifies the line address corresponding to COM output when the contents of the display data RAM is displayed, as shown in Fig. 6.5 and 6.6. Normally, the top line of the display (COM0 output in the case of normal rotation of the common output status and COM131 output in the case of reverse rotation) is specified by the Display Start Line Address Set command. The display area starts from the specified display start line address to cover the area corresponding to the lines specified by the DUTY Set command in the direction where the line address increments. If the display start line address set command is used for Fixed area Scrollable Scrollable Scrollable Fixed area Mode 0 Mode 1 Scroll mode Mode 2 Fixed area Scrollable Fixed area Mode 3 00H Upper fixed area Number of line : AS AS-1 DL Scroll area Number of line : AL AE+1 Lower fixed area Number of line Final line address 6.2.5.1 Mode 0 (full screen scroll) This mode releases the area scroll. Parameters AS, AE and AL are disabled, 6.2.5.2 Mode 1 (Upper scroll ) Reading starts from the line address DL to read AL lines as a scroll area. If the line address AE is read in the middle of reading the scroll area, the line address to be read next will be 00H. When all the AL lines have been read, the address to be read next will be AE + 1. When reading is completed up to the final line address, the control goes back to the line address DL, and parameter AS is disabled. DL can be specified in the range from 00H to AE. Rev. 2.1 EPSON 15 S1D15E06 Series 6.2.5.3 Mode 2 (lower scroll) Reading starts from line address 00H to reach the line address AS-1 in the continuous reading mode. Upon completion of reading of line address AS-1, the line address moves to the DL to read the area corresponding to AL lines from the line address DL as a scroll area. If the final line address is read in the middle of reading the scroll area, the line address to be read next will be AS. When all AL lines have been read, the control goes back to the line address 00H, and parameter AE is disabled. DL can be specified in the range from AS to the final line address. 6.2.5.4 Mode 3 (Center scroll) Reading starts from line address 00H to reach the line address AS-1 in the continuous reading mode. Upon completion of reading of line address AS-1, the line address moves to the DL to read the area corresponding to AL lines from the line address DL as a scroll area. If the final line address is read in the middle of reading the scroll area, the line address to be read next will be AS. When all AL lines have been read, the line address will be AE+1. When up to the final line address has been read, the control goes back to the line address 00H, DL can be specified in the range from AS to AE. 6.2.6 Display data latch circuit The display data latch circuit is a latch to temporarily latch the display data output from then display data RAM to the liquid crystal drive circuit. Display normal/ reverse, display ON/OFF, and display all lighting ON/ OFF commands control the data in this latch, without the data in the display data RAM being controlled. 6.2.7 Partial display Partial display of the screen is provided by the partial display ON/OFF command. The partial area (display start line, number of display lines) are set by the partial display set command. The display start line of the parameter shows the line assigned in the COM direction of the liquid crystal screen. It is different from the line address given in Fig. 6.5 and 6.6. Example: When the point is set at 1 (COM4 to 7) by the Duty Reset command, the display line is assigned as shown below. If the display start line 4 and display line count 3 are specified by the partial display set command, the display area is COM8 to COM10. Display line 0 1 2 3 4 5 6 7 8 9 10 LCD panel COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 16 EPSON Rev. 2.1 S1D15E06 Series 4 gray-scale display Data When the display start line is set to 11H D1,D0 D3,D2 D5,D4 D7,D6 D1,D0 D3,D2 D5,D4 D7,D6 D1,D0 D3,D2 D5,D4 D7,D6 D1,D0 D3,D2 D5,D4 D7,D6 D1,D0 D3,D2 D5,D4 D7,D6 D1,D0 D3,D2 D5,D4 D7,D6 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H Start 132 lines Page Address D5 D4 D3 D2 D1 D0 Common Output state: Normal rotation COM Output COM0 COM1 COM2 COM3 COM4 COM4 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 0 0 0 0 0 0 Page 0 0 0 0 0 0 1 Page 1 0 0 0 0 1 0 Page 2 0 0 0 0 1 1 Page 3 0 0 0 1 0 0 Page 4 0 0 0 1 0 1 Page 5 0 1 1 1 1 1 D1,D0 D3,D2 D5,D4 D7,D6 D1,D0 D3,D2 D5,D4 D7,D6 SEG0 9F 00 SEG1 9E 01 SEG2 9D 02 SEG3 9C 03 SEG4 9B 04 SEG5 9A 05 Page 31 7CH 7DH 7EH 7FH 80H 81H 82H 83H SEG156 03 9C SEG157 02 9D SEG154 05 9A SEG155 04 9B SEG158 01 9E SEG159 00 9F Column Address D0 D0 0 ADC 1 0 0 0 0 0 Page 32 COM124 COM125 COM126 COM127 COM128 COM129 COM130 COM131 LCD 1 Fig. 6.5 4 gray-scale Rev. 2.1 EPSON Out 17 S1D15E06 Series Binary display Page Address D5 D4 D3 D2 D1 D0 Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 When the display start line is set to 0CH Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 4FH 50H F9H FAH FBH FCH FDH FEH FFH 100H 101H 102H 103H 104H 105H 106H 107H Common output state: Normal mode COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 COM129 COM130 COM131 0 0 0 0 0 0 Page 0 0 0 0 0 0 1 Page 1 Start 0 0 0 0 1 0 Page 2 0 0 0 0 1 1 Page 3 0 0 0 1 0 1 Page 5 ......... ......... 132 lines 0 0 0 1 0 0 Page 4 0 0 1 1 1 1 Page 15 0 1 0 0 0 0 Page 16 0 1 0 0 0 1 Page 17 0 1 0 0 1 0 Page 18 ......... ......... 0 1 1 1 1 1 Page 31 1 0 0 0 0 0 Page 32 ......... ......... SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 Fig. 6.6 Binary display 18 EPSON LCD Out D0 D0 ADC Column Address 98 99 9A 9B 9C 9D 9E 9F 00 01 02 03 04 05 06 07 9F 9E 9D 9C 9B 9A 99 98 07 06 05 04 03 02 01 00 1 0 ......... Rev. 2.1 S1D15E06 Series 6.3 Oscillator circuit A display clock is generated by the CR oscillator. The oscillator circuit is enabled only when M/S = HIGH and CLS = HIGH. Oscillation starts after input of the builtin oscillator circuit ON command input. When CLS = LOW, oscillation stops, and display clock is input from the CL pin. flicker. Furthermore, the display clock generates internal common timing, liquid crystal alternating signal(FR), field start signal (CA) and drive pattern signal (Fl and F2). The FR normally generates 2-frame alternating drive system drive waveform to the liquid crystal drive circuit. The n-line reverse alternating drive waveform is generated for each 4 × (a+1) line by setting data on the n-line reverse drive register. When there is a display quality problem including crosstalk,the problem may be solved using the n-line reverse alternating drive. Execute liquid crystal display to determine the number of lines “n” for alternation. When you want to use the S1D15E06 series in multichip configuration, supply display timing signal (FR, CA, F1, F2, CL, DOF) to the slave side from the master side. Table 6.5 shows the statuses of FR, CA, F1, F2, CL, DOF. 6.4 Display timing generation circuit Timing signals are generated from the display clock to the line address circuit and display data latch circuit. Synchronized with display clock, display data is latched in display data latch circuit, and is output to the segment drive output pin. Reading of the display data into the LCD drive circuit is completely independent of access from the MPU to the display data RAM. Accordingly, asynchronous access to the display data RAM during LCD display does not give any adverse effect; like as Table 6.5 Operating mode Master (M/S = HIGH) Built-in oscillator circuit enabled (CLS = HIGH) Built-in oscillator circuit disabled (CLS = LOW) Slave (M/S = LOW) Built-in oscillator circuit enabled (CLS = HIGH) Built-in oscillator circuit disabled (CLS = LOW) CL Output Input Input Input FR, CA, F1, F2, DOF Output Output Input Input 6.5 Liquid crystal drive circuit 6.5.1 SEG Drivers This is a SEG output circuit. It selects the five values of V2, V1, VC, MV1 and MV2 using the driver control signal determined by the decoder, and output them. 6.5.2 COM Drivers This is a COM output circuit. It selects three values of V3, VC and MV3(VSS) using the driver control signal determined by the decoder, and output them. S1D15E06 series allows the COM output scanning direction to be set by the common output status select command. (See Table 6.6). This will reduce restrictions on IC layout during LCD module assembling. Table 6.6 Status Normal Reverse Direction of COM scanning COM 0 → COM 131 COM 131 → COM 0 Rev. 2.1 EPSON 19 S1D15E06 Series 6.6 Power supply circuit This is a power supply circuit to generate voltage required for liquid crystal drive, and is characterized by a low power consumption. It consists of a step-up circuit, voltage regulating circuit and liquid crystal drive voltage generating circuit, and is enabled only during master operation. The power supply circuit uses the power control set command to provide an on/off control of step-up circuit, voltage regulating circuit and liquid crystal drive potential generating circuit. This allows a combined use of the external power supply and part of built-in power supply functions. Table 6.7 shows functions controlled by the 5-bit data of the control set command, and Table 6.8 shows reference combinations. The power supply circuit is enabled only during master operation. Table 6.7 Control by 5-bit data of the control set command Item D4 Step-cut circuit scaling factor select bit 1 D3 Step-cut circuit scaling factor select bit 2 D2 Step-cut circuit control bit D1 Voltage regulator circuit (VC regulator circuit) control bit D0 LCD driving potential generating circuit (LCDV circuit) control bit Table 6.8 Reference combination Circuits used D4 D3 D2 D1 D0 Step-up VC regulator circuit circuit 1 Use of all built-in power supplies Triple step-up 11111 “1” “1” Double step-up 10111 “1” “1” VOUT = VDD 01111 “1” “1” × “0” “1” 2 VC regulating circuit and 0 0 0 1 1 LCDV circuit only × “0” × “0” 3 LCDV circuit only 00001 × “0” × “0” 4 External power supply 00000 only (S1D15E06D00B*) * Any combinations other than the above are not available. State “1” “0” – – – – ON OFF ON OFF ON OFF Triple Double Single 1 1 – – – 1 0 – – – 0 1 – – – LCDV circuit Eternal input power supply “1” “1” “1” “1” “1” × “0” – – – VOUT VC V 3, V2, V 1, VC , MV1, MV2 *100ms or more should be kept from VC regulator circuit ON to LCDV circuit ON. 20 EPSON Rev. 2.1 S1D15E06 Series 6.6.1 Step-up circuit VDD-VSS potential can be triple and double step-up by the step-up circuit built in the S1D15E06 series. The status of VOUT = VDD can be selected by stopping the operation of the triple and double step-up circuit using the command 1 When used by switching between the triple, double step-up and VOUT = VDD using a command: Capacitors C1 are connected between CAP1+ CAP1, between CAP2+ CAP2 and between VDD VOUT for use. 2 When used by switching between the double step-up and VOUT = VDD using a command: Capacitors C1 are connected between CAP1+ CAP1 and between VDD VOUT for use. 3 Only VOUT = VDD is used. VDD pin and VOUT pin are connected for use. VDD C1 + VOUT S1D15E06 C1 + VDD VOUT S1D15E06 VDD VOUT S1D15E06 + C1 CAP1+ CAP1– CAP2– + C1 CAP1+ CAP1– OPEN OPEN OPEN OPEN CAP1+ CAP1– CAP2– CAP2+ OPEN CAP2– CAP2+ C1 + CAP2+ 1 Triple, double step-up or VOUT = VDD 2 Double step-up or VOUT = VDD 3 VOUT = VDD (without step-up) Fig.6.7 shows the potential relationship for boosting. VOUT = 3 x VDD = 6V VOUT = 2 x VDD = 6V VDD = 3V VDD = 2V VSS = 0V VSS = 0V VSS = 0V VOUT = VDD = 3.6V Triple step-up potential relationship Double step-up potential relationship Fig. 6.7 VOUT = VDD potential relationship * Set the VDD voltage range so that the VOUT pin voltage does not exceed the absolute maximum rating. Rev. 2.1 EPSON 21 S1D15E06 Series 6.6.2 Voltage Regulating Circuit VOUT generated from the step-up circuit or VOUT input from the outside produces liquid crystal drive voltage V C v ia the voltage regulating circuit. The voltage regulating circuit is controlled by liquid crystal drive voltage change command and electronic volume. The S1D15E06 series has a high precision constant voltage source, and incorporates 4-step liquid crystal drive voltage change command and 128-step electronic volume functions. This makes it possible to provide a high precision liquid crystal drive voltage regulation only by the command without adding any external parts. The variable range of the VC voltage is from about 1.6 to 7.0 [V]. When the internal step-up is used, or VOUT is input for use, the V OUT p otential should be, in principle, the voltage 20% or more higher than the maximum voltage of the V C t o be used, giving consideration to temperature characteristics. Example: When VC output is 7 [V], VOUT ≥ 8.4 [V] (three times 2.8 [V], etc.) When VC output is 4 [V], VOUT ≥ 4.8 [V] (two times 2.4 [V], three times 1.8 [V]) • Electronic volume α of Table 6.9 indicates an electronic volume command value. It takes one of 128 states when the data is set in the 7-bit electronic volume register. Table 6.9 shows the value of α by setting the data in the electronic volume register. Table 6.9 D6 0 0 0 1 1 1 D5 0 0 0 1 1 1 D4 0 0 0 1 1 1 D3 0 0 0 1 1 1 D2 0 0 0 1 1 1 D1 0 0 1 0 1 1 D0 0 1 0 1 0 1 α 0 1 2 125 126 127 Voltage VC Small ↑ ↓ Large • Liquid crystal drive voltage selection The liquid drive voltage range can be selected from 3 states by the liquid crystal drive voltage select command using the two-bit crystal drive voltage select command register. Table 6.10 D1 0 1 1 D0 0 0 1 VC voltage output range 1.77V to 3.50V 2.53V to 5.00V 3.54V to 7.00V 22 EPSON Rev. 2.1 S1D15E06 Series Equation A-1 represents VC logical values. For the output voltage of VC, a manufacturing dispersion of up to ± 3% should be taken into account. Equation A-1 Unit [V] Electronic VR α 0 to 31 32 to 63 64 to 95 96 to 127 D1 D0 0 0 VC (Max.) = 3.50V 1.77 + 0.0195 × α 2.39 + 0.0156 × (α–32) 2.89 + 0.0117 × (α–64) 3.26 + 0.0078 × (α–96) LCD voltage selection D1 D0 1 0 VC (Max.) = 5.00V 2.53 + 0.028 × α 3.42 + 0.0223 × (α–32) 4.12 + 0.0167 × (α–64) 4.65 + 0.0112 × (α–96) D1 D0 1 1 VC (Max.) = 7.00V 3.54 + 0.039 × α 4.78 + 0.0313 × (α–32) 5.77 + 0.0234 × (α–64) 6.52 + 0.0156 × (α–96) 7 6 5 4 VC 3 2 1 0 32 64 Value of electronic volume α 96 127 Figure 6.8 Rev. 2.1 EPSON 23 S1D15E06 Series 6.6.3 Liquid crystal drive voltage generation circuit Voltage VC is boosting in the IC to generate potential V3. Furthermore, voltages V3 and VC are converted by resistive divider to produce V2, V1, MV1 and MV2 voltages. V2, V2, MV1 and MV2 voltages are impedance-converted by the voltage follower, and is supplied to the liquid crystal drive circuit. V2 V1 VC MV1 MV2 11/14 • V3 9/14 • V3 7/14 • V3 5/14 • V3 3/14 • V3 An example of circuit around the power supply circuit 1 Use of all built-in power supplies When used by switching between the triple, double boosting and VOUT = VDD: (12 C’s) When used by switching between the double boosting and VOUT = VDD: (11 C’s) C1 C1 C1 C1 C1 + + + + CAP1+ CAP1– CAP2– CAP2+ VOUT VDD CAP3+ CAP3– CAP4– CAP4+ CPP+ CPP– CPM+ CPM– VDD VSS + C1 C1 + CAP1+ CAP1– CAP2– CAP2+ VOUT VDD CAP3+ CAP3– CAP4– CAP4+ CPP+ CPP– CPM+ CPM– VDD VSS + C1 C1 C1 C1 + + S1D15E06 Series + + + + C3 × 6 + + + + V3 V2 V1 VC MV1 MV2 MV3(VSS) + + C3 × 6 + + + + V3 V2 V1 VC MV1 MV2 MV3(VSS) 24 EPSON S1D15E06 Series Rev. 2.1 S1D15E06 Series Only VOUT = VDD is used: (9 C’s) 2 VC regulating circuit and LCDV circuit VOUT external input (10 C’s) CAP1+ CAP1– CAP2– CAP2+ VOUT VDD C1 C1 + CAP3+ CAP3– CAP4– CAP4+ CPP+ CPP– CPM+ CPM– + + C3 × 6 + + + + V3 V2 V1 VC MV1 MV2 MV3(VSS) VDD VSS + C1 VOUT CAP1+ CAP1– CAP2– CAP2+ VOUT VDD C1 C1 + CAP3+ CAP3– CAP4– CAP4+ CPP+ CPP– CPM+ CPM– VDD VSS + C1 S1D15E06 Series + + + C3 × 6 + + + + + V3 V2 V1 VC MV1 MV2 MV3(VSS) 3 LCDV circuit only VC external input (9 C’s) 4 External power supply only external input (1 C) CAP1+ CAP1– CAP2– CAP2+ VOUT VDD C1 C1 + CAP3+ CAP3– CAP4– CAP4+ CPP+ CPP– CPM+ CPM– + + + + + + VDD VSS + C1 CAP1+ CAP1– CAP2– CAP2+ VOUT VDD CAP3+ CAP3– CAP4– CAP4+ CPP+ CPP– CPM+ CPM– VDD VSS + C1 S1D15E06 Series + C3 × 6 VC V3 V2 V1 VC MV1 MV2 MV3(VSS) External Power Supply V3 V2 V1 VC MV1 MV2 MV3(VSS) Rev. 2.1 EPSON S1D15E06 Series S1D15E06 Series 25 S1D15E06 Series Examples of common reference settings Item Settings Unit C1 1.0 to 4.7 µF C2 0.47 to 1.0 C3 0.47 to 1.0 *5 Precautions when installing the COG When installing the COG, it is necessary to duly consider the fact that there exists a resistance of the ITO wiring occurring between the driver chip and the externally connected parts (such as capacitors and resistors). By the influence of this resistance, non-conformity may occur with the indications on the liquid crystal display. When installing the COG, we recommend to use the "4 External power supply only" 6.6.4 Temperature gradient select circuit This is a circuit to select the temperature gradient characteristics of the liquid crystal drive power supply voltage. Temperature gradient characteristics can be selected from eight states by the Temperature Gradient command. Selection of temperature gradient characteristics conforming to the temperature characteristics of the liquid crystal to be used makes it possible to configure a system without providing an external element for temperature characteristics compensation. The optimum values for above-mentioned Cl, C2 and C3 vary according to the LCD panel to drive. Use the above-mentioned values as references. Actually verify the display of a pattern with big load to make a decision. 6.7 Reset circuit When the RES input becomes LOW, this LSI is set to the initialized state. The following shows the initially set state: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Display : OFF Display OFF mode : VSS output Display : normal mode Display all lighting : OFF Common output status : normal Display start line : Set to 1st line Page address : Set to 0 page Column address : Set to 0 address Display data input direction : Column direction Column address direction : forward n-line a.c. reverse drive : OFF (reverse drive for each frame) n-line reverse drive register : (D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0) Display mode : 4 gray-scale display Gray-scale pattern register : (D7, D6, D5, D4, D3, D2, D1, D0) = (*, 1, 0, 1, *, 0, 1, 0) Area scroll : Scroll mode : (D1, D0) = (0, 0) Scroll start address : (D7, D6, D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0, 0) Scroll terminating address : (D7, D6, D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0, 0) Number of display lines : (D7, D6, D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0, 0) 16. DUTY register : (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0) (1/132 duty) Start spot (block) register : (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0) (COM0) 17. Partial display : OFF 18. Partial display start line : (D7, D6, D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0) Number of partial display lines : (D7, D6, D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0) 19. Read modify write : OFF 20. Built-in oscillation circuit : stop 21. Oscillation frequency register : (D3, D2, D1,D0) = (0, 0, 0, 0) (120 kHz) 22. Power control register : (D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0) 23. Clock frequency for step-up/step-down Step-up : (D2, D1, D0) = (1, 0, 1) Step-down : (D6, D5, D4) = (1, 0, 1) 24. Liquid crystal drive voltage selection register : (D1,D0) = (0, 0) 25. Electronic volume register : (D6, D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0, 0) 26. Discharge : ON (only for when RES = LOW) 27. Power save : OFF 28. Temperature gradient resistor : (D2, D1, D0) = (0, 0, 0) (–0.06/°C) 29. Register data in the serial interface : Clear When the Reset command is used, only the abovementioned inilialized items 7, 8 and 19 are executed. When power is turned on, initialization by the RES pin is necessary. After initialization by the RES pin, each input pin must be controlled correctly. Furthermore, when control signals from the MPU have a high impedance, the excessive current may flow to the IC. After VDD i s applied, measures should be taken to ensure that the input pin does not have a high impedance. The S1D15E06 series discharges the electric charge of VOUT and liquid crystal drive voltage (V3, V2, V1, VC, MV1, MV2) at the level of RES pin = LOW. When liquid crystal drive external power supply is used, external power supply should not be supplied during the period of RES = LOW to prevent external power supply and VDD from being short circuited. 26 EPSON Rev. 2.1 S1D15E06 Series 7. COMMAND The S1D15E06 series identifies data bus signals by a combination of A0, RD(E) and WR(R/W). Interpretation and execution of the command are executed by the internal timing alone which is independent of the external clock. This allows high-speed processing. The 80 series MPU interface allows the command to be started by entering the low pulse in the RD pin during reading and by entering the low pulse in the WR pin during writing. The 68 series MPU interface allows a read state to occur by entering HIGH in the R/W pin, and permits a write state to occur by entering LOW. It also allows the command to be started by entering the high pulse in the pin E. (For timing, see the description of “10. Timing characteristics”). Accordingly, the 68 series MPU interface is different from 80 series MPU interface in that RD(E) is “1(H)” in the case of display data/read shown in the Command Description and Command Table. The following describes the commands, based on the example of the 80 series MPU interface: When the serial interface is selected, enter data sequentially starting from D7. Command Description (1) Display ON/OFF This command sets the display ON/OFF. When display OFF is specified, segment and common drivers outputs the level selected by the display OFF Mode Select command. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 Output level Display OFF Display ON (2) Display OFF Mode Select This command is used to set the output level of the segment and common driver when the display is off. In the initial setting state, it becomes "D0 = 0". * When D0 = 0 is selected in the case of S1D15E06D00B*, the MV2 and common driver VSS level is output by segment driver when display is off. Select D0 = 1 to use the S1D15E06D00B*. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 1 D1 1 D0 0 1 Output level VSS VC (3) Display Normal/Reverse This command allows the display ON/OFF state to be reversed, without having to rewrite the contents of the display data RAM. In this case, contents of the display data RAM are maintained. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 Setting RAM data = HIGH LCD ON Voltage (normal) RAM data = LOW LCD ON Voltage (reverse) 1 Rev. 2.1 EPSON 27 S1D15E06 Series (4) Display All Lighting ON/OFF This command forces all the displays to be turned on independently of the contents of the display data RAM. In this case, the contents of the display data RAM are maintained. Fully white display can also be made by a combination of the Display Reverse command. E RD 1 R/W WR 0 A0 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 1 Setting Normal display status Display all lighting (5) Common Output Status Select This command allows the scanning direction of the COM output pin to be selected. For details, see the description of “6.5.2 COM Drivers” in the Function Description. A0 0 E RD 1 R/W WR D7 D6 D5 D4 D3 D2 D1 D0 Selected state 0 11000100 Normal COM0 → COM131 1 Reverse COM131 → COM0 (6) Display Start Line set (Parameter: 1 byte (4 gray-scale) and 2 bytes (binary)) The parameter following this command specifies the display start line address of the display data RAM shown in Fig. 6.5 and 6.6. When the Display Mode command is used to select 4 gray-scale display, a 1-byte parameter must be entered. When the binary display is selected, a 2-byte parameter must be entered. The display area is indicated in the direction where line address numbers are incremented, starting from the specified line address. If a dynamic change of the line address is made by this command, smooth scrolling in the longitudinal direction and page breaking are enabled. For details, see the description of “6.2.4 Line address circuit” in the Function Description. E RD 1 1 1 R/W WR 0 0 0 A0 0 1 1 D7 1 P7 * D6 0 P6 * D5 0 P5 * D4 0 P4 * D3 1 P3 * D2 0 P2 * D1 1 P1 * D0 0 P0 P8 Mode setting Register setting 1 Register setting 2 (only binary display required) *: denote invalid bits. 28 EPSON Rev. 2.1 S1D15E06 Series • Display Start Line Set command parameter (i) When the display mode is a 4 gray-scale mode: The one-byte parameter is used to specify the address. P7 0 0 0 P6 0 0 0 P5 0 0 0 P4 0 0 0 ↓ 1 0 0 0 0 0 1 1 0 0 0 0 0 1 Set to the line address 00H at the time of resetting. (ii) When the display mode is binary: To specify the address, continuous 2-byte data is necessary. The first byte D0 is LSB, and the second byte D0 is MLB. P7 1st byte 2nd byte 0 * 0 * 0 * P6 0 * 0 * 0 * P5 0 * 0 * 0 * P4 0 * 0 * 0 * P3 0 * 0 * 0 * P2 0 * 0 * 0 * P1 0 * 0 * 1 * P0 P8 0 0 1 0 0 0 Line address 00H 01H 02H 0 1 P3 0 0 0 P2 0 0 0 P1 0 0 1 P0 0 1 0 Line address 00H 01H 02H ↓ 82H 83H ↓ 0 0 0 0 0 1 * * * * * * 0 0 0 0 0 1 * * * * * * Set to line address 000H at the time of resetting. • Line address setting sequence ↓ 1 0 106H * 1 1 1 107H * 1 *: denote invalid bits. Set Line Address Mode Set Line Address Register No Change Completed? Yes One byte for 4 gray-scale Two bytes for binary display Reset Line Address Mode Fig. 7.1 Rev. 2.1 EPSON 29 S1D15E06 Series (7) Page Address Set This command specifies the page address corresponding to row address when MPU access to the display data RAM shown in Fig. 6.5 and 6.6. For details, see the description of “6.2.2 Page address circuit” in the Function Description. E RD 1 1 R/W WR 0 0 A0 0 1 D7 1 * D6 0 * D5 1 P5 D4 1 P4 D3 0 P3 D2 0 P2 D1 0 P1 D0 1 P0 Page address Command Page address setting *: denote invalid bits. P5 0 0 0 1 P4 0 0 1 0 P3 0 0 ↓ 1 0 P2 0 0 1 0 P1 0 0 1 0 P0 0 1 1 0 Page address 0 1 ↓ 31 32 (8) Column Address Set This command sets the display data RAM column address given in Fig. 6.5 and 6.6. For details, see the description of “6.2.3 Column address circuit” in the Function Description. A0 0 1 E RD 1 1 R/W WR 0 0 D7 0 P7 D6 0 P6 D5 0 P5 D4 1 P4 D3 0 P3 D2 0 P2 D1 1 P1 D0 1 P0 Column address 0 1 2 ↓ 158 159 P7 0 0 0 1 1 (9) Display Data Write P6 0 0 0 0 0 P5 0 0 0 0 0 P4 0 0 0 ↓ 0 1 P3 0 0 0 0 1 P2 0 0 0 0 1 P1 0 0 1 1 1 P0 0 1 0 0 1 This command allows the 8-bit data to be written to the address specified by the display data RAM. After writing, column address or page address is automatically incremented +1 by the Display Data Input Direction Select command. This enables the MPU to write the display data continuously. E RD 1 1 R/W WR 0 0 A0 0 1 D7 0 D6 0 D5 0 D4 D3 1 1 Write Data D2 1 D1 0 D0 1 30 EPSON Rev. 2.1 S1D15E06 Series (10) Display Data Read This command allows the 8-bit data to be read from the address specified by the display data RAM. After reading, column address or page address is automatically incremented +1 by the Display Data Input Direction select command. This enables the MPU to read multiple word data continuously. It should be noted that one dummy reading is essential immediately after the column address or page address has been set. For details, see the description of “6.1.5 Access to display data RAM and internal register” in the Function Description. When the serial interface is used, display data cannot be read. E RD 1 0 R/W WR 0 1 A0 0 1 D7 0 D6 0 D5 0 D4 D3 1 1 Read Data D2 1 D1 0 D0 0 (11) Display Data Input Direction Select This command sets the direction where the display RAM address number is automatically incremented. For details, see the description of “6.2.3 Column address circuit” in the Function Description. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 0 1 Direction Column Page (12) Column Address Set Direction This command can reverse the relationship between the display RAM data column address and segment driver output shown in Fig. 6.5 and 6.6. So you can reverse the sequence of segment driver output pins using this command. When the display data is written or read, the column address is incremented by (+1) according to the column address given in Fig. 6.4 and 6.5. For details, see the description of “6.2.3 Column address circuit” in the Function Description. E RD 1 R/W WR 0 A0 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 1 Setting Normal Reverse (13) n-line Inversion Drive Register Set This command sets the liquid crystal alternating drive reverse line count in the register to start line reverse driving operation. The line count to be set is 4 to 128 (32 states for each 4 lines. For details, see the description of “6.4 Display timing generation circuit” in the Function Description. A0 0 1 E RD 1 1 R/W WR 0 0 D7 0 * D6 0 * D5 1 * D4 1 P4 D3 0 P3 D2 1 P2 D1 1 P1 D0 0 P0 Reverse line count Command Reverse line count *: denote invalid bits. P4 0 0 1 1 P3 0 0 1 1 P2 0 0 ↓ 1 1 1 1 0 1 P1 0 0 P0 0 1 Reverse line count 4 (1 × 4) 8 (2 × 4) ↓ 124 (31 × 4) 128 (32 × 4) Rev. 2.1 EPSON 31 S1D15E06 Series (14) n-line ON/OFF This command provides ON/OFF control of n-line inverting drive. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 1 n-line OFF ON (15) Display Mode This command sets the display mode. 4 gray-scale and binary display each have a different RAM configuration. For details, see the description of “6.2.1 Display Data RAM” in the Function Description. A0 0 1 E RD 1 1 R/W WR 0 0 D7 0 * D6 1 * D5 1 * D4 0 * D3 0 * D2 1 * D1 1 P1 D0 0 P0 Display mode Command Display mode *: denote invalid bits. P1 0 0 Set to 4 gray-scale (D1, D0) = (0, 0) at the time of resetting. (16) Gray-scale Pattern Set This command sets the level of gray-scale. E RD 1 1 R/W WR 0 0 P0 0 1 Display mode 4gray-scale Binary value A0 0 1 D7 0 * D6 0 P6 D5 1 P5 D4 1 P4 D3 1 * D2 0 P2 D1 0 P1 D0 1 P0 Gray-scale pattern Command Selection of gray-scale level * (P6, P5, P4) : Selects the level of gray-scale bit (1, 0) * (P2, P1, P0) : Selects the level of gray-scale bit (0, 1) Gray-scale bit (1, 0) – – – Gray-scale bit (0, 1) – – – P6 0 0 1 P6 – – – P5 0 1 1 P5 – – – P4 1 0 0 P4 – – – – – – P2 – – – P2 0 0 1 P1 – – ↓ – P1 0 1 ↓ 1 P0 – – – P0 1 0 0 Level of gray-scale White ↓ Black Level of gray-scale White ↓ Black – – – 32 EPSON Rev. 2.1 S1D15E06 Series (17) Area Scroll Set This command sets the area scroll. When the binary display is selected by the Display Mode Set command, the scroll end line address becomes a two-byte parameter. 1 4 gray-scale display E RD 1 1 1 1 1 R/W WR 0 0 0 0 0 A0 0 1 1 1 1 D7 0 * P27 P37 P47 D6 0 * P26 P36 P46 D5 0 * P25 P35 P45 D4 1 * P24 P34 P44 D3 0 * P23 P33 P43 D2 0 * P22 P32 P42 D1 0 P11 P21 P31 P41 D0 0 P10 P20 P30 P40 Area scroll Command Scroll mode Scroll start line address Scroll end line address Scroll display line count *: denote invalid bits. P11 0 0 1 1 P27 0 0 1 1 P37 0 0 1 1 P47 0 0 1 1 P26 0 0 0 0 P36 0 0 0 0 P46 0 0 0 0 P25 0 0 0 0 P35 0 0 0 0 P45 0 0 0 0 P24 0 0 0 0 P34 0 0 0 0 P44 0 0 0 0 P23 0 0 0 0 P33 0 0 0 0 P43 0 0 0 0 P22 0 0 0 0 P32 0 0 0 0 P42 0 0 0 1 P21 0 0 ↓ 1 1 P31 0 0 ↓ 1 1 P41 0 1 ↓ 1 0 P10 0 1 0 1 P20 0 1 0 1 P30 0 1 0 1 P40 1 0 1 0 Scroll mode 0 (full screen) 1 (Upper) 2 (Lower) 3 (Central) Scroll start line address 00H 01H ↓ 82H 83H Scroll end line address 00H 01H ↓ 82H 83H Scroll display line count 1 2 ↓ 131 132 Rev. 2.1 EPSON 33 S1D15E06 Series 2 Binary display A0 0 1 1 1 1 1 E RD 1 1 1 1 1 1 R/W WR 0 0 0 0 0 0 D7 0 * P27 P37 * P47 D6 0 * P26 P36 * P46 D5 0 * P25 P35 * P45 D4 1 * P24 P34 * P44 D3 0 * P23 P33 * P43 D2 0 * P22 P32 * P42 D1 0 P11 P21 P31 * P41 D0 0 P10 P20 P30 P38 P40 Area scroll Command Scroll mode Scroll start line address Scroll end line address Scroll display line count *: denote invalid bits. • Specifications on the parameters for scroll mode, scroll start line address and scroll display line count are the same as those on 4 gray-scale display. P37 1st byte 2nd byte 0 * 0 * 0 * 0 * (18) Duty Set Command Liquid crystal drive at a lower power consumption is ensured by using this command to change the duty. Use of this command also allows display at a desired position on the panel (continuous COM pins on a 4-line basis). This command is used with a pair of the duty set parameter and start point (block) parameter, so be sure to set both parameters so that one of them will immediately follow the other. A0 0 1 1 E RD 1 1 1 R/W WR 0 0 0 D7 0 * * D6 1 * * D5 1 P15 P25 D4 0 P14 P24 D3 1 P13 P23 D2 1 P12 P22 D1 0 P11 P21 D0 1 P10 P20 Selected state Duty set command Duty set Start point set *: denote invalid bits. • Duty set Duty can be set in the range from 1/4 duty to 1/132 duty by 4 steps. Set to 1/132 duty after resetting. P15 0 0 0 0 0 1 P14 0 0 0 0 1 0 P13 0 0 0 0 1 0 P12 0 0 0 0 ↓ 1 0 P11 0 0 1 1 1 0 P10 0 1 0 1 1 0 Duty set 1/4 duty set 1/8 duty set 1/12 duty set 1/16 duty set ↓ 1/128 duty set 1/132 duty set P36 0 * 0 * 0 * 0 * P35 0 * 0 * 0 * 0 * P34 0 * 0 * 0 * 0 * P33 0 * 0 * 0 * 0 * P32 0 * 0 * 1 * 1 * P31 0 * 0 * ↓ 1 * 1 * P30 P38 0 0 1 0 0 1 1 1 Scroll end line address Binary value 00H 01H ↓ 106H 107H 34 EPSON Rev. 2.1 S1D15E06 Series • Start point (block) register set parameter Use this parameter to set 6-bit data in the start point (block) register. Then one of 33 start point blocks will be determined. * Use the Display Start Line Set command (6) for display scroll. Do not use this command for display scroll. P25 0 0 0 0 1 P24 0 0 0 1 0 P23 0 0 0 ↓ 1 0 1 0 1 0 1 0 P22 0 0 0 P21 0 0 1 P20 0 1 0 Start piont setting 0 (COM0 to 3) 1 (COM4 to 7) 2 (COM8 to 11) ↓ 31 (COM124 to 127) 32 (COM128 to 131) Set to 0 block (D7 to D0: ***00000) at the time of resetting * Voltage optimum to liquid crystal drive is changed when the duty is changed. Use the electronic volume and set the voltage to get the optimum display. • Duty command setup example 1. Duty 1/88 When 1 (COM4 to COM7) is specified as the start point (block) Display area COM4 to COM91 2. Duty 1/68 When 26 (COM104 to COM107) is specified as the start point (block) Display area COM104 to COM131 and COM0 to COM39 * If the COM pin is not shared by the master and slave in the master/slave 2-chip operation (for vertical drive such as SEG132, COM80+COM80), the same duty must be used on the master and slave. Otherwise, display contrast will be different on the master and slave. When you want to disable display on either the master and slave, use the display OFF Mode Select command to set the side you want to disable, so that VC level is output. (19) Partial Display ON/OFF The LCD partial display is turned on or off by this command. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 1 D0 0 1 Partial display OFF ON (20) Partial Display Set This command sets the LCD partial display area. Duty is placed in the state selected by the Duty Set command. When partial display is switched by this command, liquid crystal drive voltage need not be changed. For details, see the description of “6.2.7 Partial Display” in the Function Description. A0 0 1 1 E RD 1 1 1 R/W WR 0 0 0 D7 0 P17 P27 P17 0 0 0 1 1 D6 0 P16 P26 P16 0 0 0 0 0 D5 1 P15 P25 P15 0 0 0 0 0 D4 1 P14 P24 P14 0 0 0 0 0 D3 0 P13 P23 P13 0 0 0 0 0 D2 0 P12 P22 P12 0 0 0 0 0 D1 1 P11 P21 P11 0 0 1 ↓ 1 1 D0 0 P10 P20 P10 0 1 0 0 1 Partial display Command Display start line Display line count Display start line 0 1 2 ↓ 131 132 Rev. 2.1 EPSON 35 S1D15E06 Series P17 0 0 1 1 P16 0 0 0 0 P15 0 0 0 0 P14 0 0 0 0 P13 0 0 0 0 P12 0 0 0 1 P11 0 1 ↓ 1 0 P10 1 0 1 0 Display start line 1 2 ↓ 131 132 * The result of display start line added to display line count exceeding 132 should be disregarded. (21) Read Modify Write This command is paired with end command for use. If this command is entered, the column address is not changed by the Display Data Read command. It can be incremented +1 by the Display Data Read command alone. This state s retained until the End command is input. If the End command is input, the column address goes back to the address when the Read Modify Write command is input. This function reduces the MPU loads when changing the data repeated in the specific display area such as blinking cursor. E RD 1 R/W WR 0 A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 * A command other than display data Read/Write command can be used in the Read Modify Write mode. However, you cannot use the column address set command. • Sequence for cursor display Page Address Set Column Address Set Read Modify Write Dummy Read Data Read Data Manipulation Data Write No Change Completed? Yes End Fig. 7.2 36 EPSON Rev. 2.1 S1D15E06 Series (22) End This command releases the read modify write mode and gets column address back to the initial address of the mode. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 Return Column address N N+1 N+2 N+3 ••• N+m N End Set read-modify-write mode Fig. 7.3 (23) Built-in Oscillator Circuit ON/OFF This command starts the built-in oscillator circuit operation. It is enabled only in the master operation mode (M/S = HIGH) when built-in oscillator circuit is valid (CLS = HIGH). When the built-in power supply is used, the Oscillator Circuit ON command must be executed before the Power Control Set command. (See the description of “(16) power control command”). If the built-in oscillator circuit is turned off when the built-in power supply is used, display failure may occur. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 0 1 Built-in oscillator circuit OFF ON Rev. 2.1 EPSON 37 S1D15E06 Series (24) Built-in Oscillator Circuit Frequency Select This command sets the built-in oscillator circuit frequency. The frequency can be selected whether the built-in oscillator circuit is turned on or off. A0 0 1 E RD 1 1 R/W WR 0 0 D7 0 * D6 1 * D5 0 * D4 1 * D3 1 P3 D2 1 P2 D1 1 P1 D0 1 P0 fOSC kHz fCL kHz Command Command Oscillation CL frequency frequency Oscillation frequency fOSC kHz 120.0 100.0 88.0 76.0 120.0 100.0 88.0 76.0 120.0 100.0 88.0 76.0 120.0 100.0 88.0 76.0 CL frequency fCL kHz fOSC 120.0 fOSC 100.0 fOSC 88.0 fOSC 76.0 fOSC/2 = 60.0 fOSC/2 = 50.0 fOSC/2 = 44.0 fOSC/2 = 38.0 fOSC/4 = 30.0 fOSC/4 = 25.0 fOSC/4 = 22.0 fOSC/4 = 19.0 fOSC/8 = 15.0 fOSC/8 = 12.5 fOSC/8 = 11.0 fOSC/8 = 9.5 P3 P2 P1 P0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 (D7 to D0: ****0000) is set after resetting. * The above-mentioned value is a Typ. value at 25°C. There is a tolerance of ±12% at 25°C. 38 EPSON Rev. 2.1 S1D15E06 Series (25) Power Control Set This command sets the built-in power supply circuit function. For details, see the description of “6.7 Power supply circuit” in the Function Description. A0 0 1 E RD 1 1 R/W WR 0 0 D7 0 0 D6 0 0 D5 1 0 D4 0 P4 P4 1 1 0 D3 0 P3 P3 1 0 1 D2 1 P2 P2 D1 0 P1 P1 D0 1 P0 P0 Selected state Command Register set Selected state Triple step-up Double step-up VOUT = VDD 0 Step-up: OFF 1 Step-up: ON 0 VC: OFF 1 VC: ON 0 LCD voltage: OFF 1 LCD voltage: ON S1D15E06D00B*: (LCD voltage: V2, V1, MV1) S1D15E06D00B*: (LCD voltage: V3, V2, V1, MV1, MV2) An internal clock is required to operate the built-in power supply circuit. During the operation of the built-in power supply circuit, be sure that the internal clock is present inside. If the built-in oscillator circuit is used, execute the built-in oscillator circuit ON command before the power control set command. If an external oscillator circuit is used, operate the external oscillator circuit before the power control set command. If the internal clock is cut off during the operation of the built-in power supply circuit, display failure may occur. To avoid this, do not cut it off. In the slave operation mode, only the parameters (D7 to D0 : ***00000) can be used with the power control set command. Do not use any other parameter. 100ms or more should be kept from VC regulator circuit ON to LCDV circuit ON. Built-in oscillator ON External oscillator input Power Control Set 1. Step-up circuit ON 2. VC regulator circuit ON 3. LCDV circuit ON* A built-in oscillator used An external oscillator used Fig. 7.4 Rev. 2.1 EPSON 39 S1D15E06 Series (26) Step-up CK Frequency Select This command selects the step-up CK and step-down CK frequencies. E RD 1 1 R/W WR 0 0 A0 0 1 D7 0 * D6 1 P6 D5 0 P5 D4 0 P4 D3 0 * D2 0 P2 D1 0 P1 D0 1 P0 Command Register *: denote invalid bits. (fosc/32) is set after resetting. Step-up CK – – – – Step-down CK * – – – – P6 – – – P5 P4 P2 P1 P0 Step-up CK – – – 0 1 1 fOSC/8 – – – 1 0 0 fOSC/16 – – – 1 0 1 fOSC/32 ↓ 1 1 0 fOSC/64 – – – – 1 1 1 fOSC/128 It should not use the following. (P2, P1, P0) = (0, 0, 0) , (0, 0, 1) , (0, 1, 0) P6 P5 P4 *000 P2 P1 P0 Step-down CK 0 1 1 – – – – fOSC/8 1 0 0 – – – – fOSC/16 1 0 1 – – – – fOSC/32 1 1 0 ↓ fOSC/64 1 1 1 – – – – fOSC/128 It should not use the following. (P6, P5, P4) = (0, 0, 0) , (0, 0, 1) , (0, 1, 0) * For S1D15E06D00B*, the step-down CK register is disabled. (27) Liquid Crystal Drive Voltage Select The liquid crystal drive voltage range issued from the liquid crystal drive voltage regulating circuit is selected from 3 states by this command. E RD 1 1 R/W WR 0 0 VC voltage output range Command Register *: denote invalid bits. VC voltage P1 P0 output range 0 0 1.77 to 3.50 V 1 0 2.53 to 5.00 V 1 1 3.54 to 7.00 V VC voltage output range, 1.77 to 3.50V, (D1, D0) = (0, 0) is set after resetting. A0 0 1 D7 0 * D6 0 * D5 1 * D4 0 * D3 1 * D2 0 * D1 1 P1 D0 1 P0 40 EPSON Rev. 2.1 S1D15E06 Series (28) Electronic Volume This command controls liquid crystal drive voltage VC issued from the built-in liquid crystal power supply voltage regulating circuit, and adjusts the liquid crystal display density. For details, see the description of “6.6.2 Voltage Regulating Circuit” in the Function Description. A0 0 1 E RD 1 1 R/W WR 0 0 D7 1 * D6 0 P6 D5 0 P5 D4 0 P4 D3 0 P3 D2 0 P2 D1 0 P1 D0 1 P0 Command Register *: denote invalid bits. • Electronic Volume Register Set When a 7-bit data to the electronic volume register is set by this command, liquid crystal drive voltage VC assumes one state out of voltage values in 128 states. After this command is input, and the electronic volume register is set, the electronic volume mode is reset. P6 0 0 0 1 1 P5 0 0 0 1 1 P4 0 0 0 ↓ 1 1 1 1 1 1 1 1 0 1 P3 0 0 0 P2 0 0 0 P1 0 0 1 P0 0 1 0 VC Smaller ↓ Larger *: denote invalid bits. • Electronic volume register set sequence Set Electronic Volume Mode Set Electronic Volume Register No Reset Electronic Volume Mode Change Completed? Yes Fig. 7.5 Rev. 2.1 EPSON 41 S1D15E06 Series (29) Discharge ON/OFF This command discharges the capacitors connected to the power supply circuit. This command is used when the system power of this IC (S1D15E06 series) is turned off, and the duty is changed. See the description of (3) Power Supply OFF and (4) Changing the Duty in the Instruction Setup: Reference. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 0 D1 1 D0 0 1 Setting Discharge OFF Discharge ON * If this command is executed when the external power supply is used, a large current may flow to damage the IC. If external power supply is used to drive liquid crystal, be sure to turn off the external power supply before executing this command. (30) Power Saving This command establishes the power save mode, thereby ensuring a substantial reduction of current consumption. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 1 Power save mode OFF ON In the power save mode, display data and operation before power saving are maintained. Access to the display data RAM from the MPU is also possible. The current consumption is reduced to the value close to static current if all operations of the LCD display system are stopped and there is no access from the MPU. In the power save mode, the following occurs: Stop of oscillator circuit Stop of LCD power supply circuit Stop of all liquid crystal drive circuit (VSS level output is issued as the segment and common driver output). The power save OFF command releases the power save mode. The system goes back to the state before the power save mode. * When the external power supply is used, it is recommended to stop the external power supply circuit function when the power save mode is started. For example, when each level of the liquid crystal drive voltage is given from the external resistive divider circuit, it is recommended to add a circuit to cut off the current flowing to the resistive divider circuit when power save function is started. The S1D15E06 series has a liquid crystal display blanking control control pin DOF, and the level goes LOW when power save function is started. You can use the DOF output to stop the external power supply circuit function. 42 EPSON Rev. 2.1 S1D15E06 Series (31) Temperature Gradient Set The 3-bit data of this command is used to set the temperature gradient characteristics of the liquid crystal drive voltage output from the built-in power supply circuit from eight states to one state. The temperature gradient of the liquid crystal drive voltage can be set according to the liquid crystal temperature gradient to be used. This eliminates the need of a temperature characteristics regulating circuit to be installed outside this IC (S1D15E06 series). E RD 1 1 R/W WR 0 0 Temperature gradient [%/°C] Command Register *: denote invalid bits. Temperature P2 P1 P0 gradient [%/°C] 0 0 0 –0.06 0 0 1 –0.08 0 1 0 –0.10 0 1 1 –0.11 1 0 0 –0.13 1 0 1 –0.15 1 1 0 –0.17 1 1 1 –0.18 (D7 to D0: *****000) is set after resetting. *: denote invalid bits. A0 0 1 D7 0 * D6 1 * D5 0 * D4 0 * D3 1 * D2 1 P2 D1 1 P1 D0 0 P0 (32) Status Read This command reads out the temperature gradient select bit set on the register. E RD 1 0 R/W WR 0 1 Temperature gradient [%/°C] Command Register *: denote invalid bits. Temperature gradient [%/°C] –0.06 –0.08 –0.10 –0.11 –0.13 –0.15 –0.17 –0.18 A0 0 1 D7 1 * D6 0 * D5 0 * D4 0 * D3 1 * D2 1 P2 D1 1 P1 D0 0 P0 P2 0 1 0 1 0 1 0 1 P1 0 0 1 1 0 0 1 1 P0 0 0 0 0 1 1 1 1 Rev. 2.1 EPSON 43 S1D15E06 Series (33) Reset This command resets the column address, page address, read modify write mode and test mode without giving adverse effect to the display data RAM. For details, see the description of “6.8 Reset” in Function Description. Resetting is carried out after the reset command has been input. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Initialization upon application of power supply is carried out by the reset signal to the RES pin. The reset command cannot be used for this purpose. (34) MLS drive selection command These are the MLS drive selection commands. These commands changes over between the dispersive drive and nondispersive drive. A0 0 1 E RD 1 1 R/W WR 0 0 D7 1 * D6 0 * D5 0 * D4 1 * D3 1 P3 D2 1 P2 D1 0 P1 D0 0 P0 Temperature gradient [%/˚C] Command Register * indicates the invalid bits. P3 0 1 P2 0 0 P1 0 0 P0 0 0 Temperature gradient [%/˚C] Dispersive drive Nondispersive drive After resetting, nondispersive drive will be preset in 4 gradation indications. In case the B/W indication is selected after resetting, dispersive drive will be preset. Dispersive drive and nondispersive drive are the LCD drive methods characteristic to the MLS drive. The S1D15E06 Series is making 4 line MLS drive and, 4 times higher period selection voltage than that of the period being used for indication of 1 line in an ordinary drive (in case of 132 line indication, the period of 1/132 of 1 frame). In case of the dispersive drive, the selection signals will be output for four times, separately, within the period of 1 frame. With this dispersive drive method, it is possible to reduce the frame frequency as compared with the nondispersive drive method. Therefore, when it becomes necessary to reduce the current consumption, we recommend you to use this dive method. However, in case of the drive method where moving pictures are to be indicated, the indication may become flickered and this dispersive drive method is not suitable for indications of moving pictures. (35) NOP This is a Non-Operation command. E RD 1 R/W WR 0 A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 Note: S1D15E06 series maintains the operation status due to the command. However, when exposed to excessive external noise, internal status may be changed. This makes it necessary to take some measures which reduces noise generation in terms of installation or system configuration, or which protects the system against adverse effect of noise. To cope with sudden noise, it is recommended to refresh the operation status on a periodic basis. 44 EPSON Rev. 2.1 S1D15E06 Series Table 7.1 Table of commands in S1D15E06 series Command code A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 (1) 0 1 01 0101110 1 (2) Display OFF Mode 0 1 01 0111110 Select 1 (3) Display Normal 0 1 01 0100110 /Reverse 1 (4) Display All Lighting 0 1 01 0100100 ON/OFF 1 (5) Common Output 0 1 01 1000100 Status Select 1 (6) Display Start Line Set 0 1 01 0001010 1 1 0 Display start line address 1 1 0* ******↓ (7) Page Address Set 0 1 01 0110001 * * Page address (8) Column Address Set 0 1 00 0010011 1 1 0 Column Address Set (9) Display Data Write 0 1 00 0011101 1 1 0 Writes data (10) Display Data Read 0 1 00 0011100 1 0 1 Reads data (11) Display Data Input 0 1 01 0000100 Direction Select 1 (12) Column Address Set 0 1 01 0100000 Direction 1 (13) N-line inversion Drive Register Set (14) N-line ON/OFF (15) Display Mode (16) Gray-scale Pattern Set (17) Area Scroll Scroll Mode Scroll Start address Scroll End address Display page count (18) Duty Set Command Duty Set Static spot (block) set (19) Partial Display ON/OFF (20) Partial Display Set Display Start line Display Line count (21) Read Modify Write 0 1 0 0 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 1 0 * 0 0 * 10110 Invert line count 00100 1 1100110 * * * * * Mode 0111001 Gray-scale pattern 0010000 * * * * * Mode Start address End address Display page count 1101101 * Duty count * Static spot (block) 0010110 1 0110010 Start line Line count 1100000 0 * 1 1 * 1 Command Display ON/OFF Function LCD display ON/OFF control. 0: OFF, 1: ON Output level when the display is OFF and in the power save mode 0: VSS, 1: VC LCD display normal/reverse 0: Normal, 1: Reverse Display All Lighting 0: Normal display, 1: All ON Selects COM output scan direction. 0: Normal, 1: Reverse Sets display start line. When the display mode is binary, the parameter consists of two bytes. Sets the display RAM page address. Sets the display RAM column address. Writes data to the display RAM. Reads data to the display RAM. Display RAM data input direction 0: Column direction 1: Page direction Compatible with display RAM address SEG output 0: Normal 1: Reverse Line invert drive. Sets the line count. Resets the line invert drive. 0: N-line OFF 1: N-line ON 00: 4 gray-scale, 01: binary Selects the contrast of gray-scale bit (1,0) (0,1). When the display mode is binary, the end address consists of two bytes. 0 0 1 1 0 0 0 * * 1 0 Partial display ON/OFF 0: OFF, 1: ON 0 1 0 1 (22) End (23) Built-in Oscillator Circuit ON/OFF (24) Built-in Oscillator Circuit Frequency Select (25) Power Control Set 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 * 0 * 1 0 1 * 0 * 1 1 0 * 1 0 0 1 * 0 1 1 1 0 1 1 111 Frequency 0101 Selects built-in power supply Operation state operation state. 0 0 1 1 Increments the column address. Increments +1 in the write mode. Does not increment in the read mode. Resets read modify write functions. Built-in oscillator circuit operation 0: OFF, 1: ON Rev. 2.1 EPSON 45 S1D15E06 Series Command code (26) (27) (28) Command Step-up CK Frequency Select Liquid Crystal Drive Voltage Select Electronic Volume Mode Set Electronic Volume Register Set Discharge ON/OFF A0 RD WR D7 0 1 00 1 1 0* 0 1 00 1 1 0* 0 1 01 1 0 1 1 0 0 * 1 D6 D5 D4 D3 1000 Frequency 0101 **** 0000 D2 D1 D0 001 0 * 0 11 VC range 01 VC output voltage is set to the electronic volume register. 128 states Discharges Power supply circuit connection capacitor. 0: OFF (normal), 1: ON Power Save 0: OFF, 1: ON Sets to 8 steps. Function Electronic volume 1 1 0 1 0 1 0 1 (29) (30) Power Save ON/OFF (31) Temperature Gradient Select (32) Stator Read (33) Reset 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 1 0 1 0 * 1 * 1 0 1 * 0 * 1 1 0 * 0 * 1 0 0 * 0 * 0 (34) MLS drive selection (35) NOP 0 1 0 1 1 1 0 0 0 1 * 1 0 * 1 0 * 1 1 * 0 1000 1110 * Temperature gradient 1110 Issues the temperature gradient *Temperature gradient select bit. 0010 Resets the column, page and address registers.Resets the read modify write function. 1100 MLS drive method MLS drive method 0 : Dispersive, 1 : Nondispersive 0 0 1 1 Non-operation command 46 EPSON Rev. 2.1 S1D15E06 Series Instruction Setup Example (Reference) (1) Initial setup VDD - VSS power turns on when RES terminal = LOW. Stable power supply Release the reset state. (RES terminal = HIGH) *1 Function setup by command entry (set by users) (12) Column address set direction (5) Common output status select (3) Display normal/reverse (4) Display all lighting ON/OFF (18) Set the duty (2) Display OFF mode select (27) LCD voltage select (28) Electronic volume (31) Temperature gradient set (When the n-line invert drive is not used) Function setup by command entry (set by users) (13) n-line invert drive register set (14) n-line ON/OFF (When the external oscillator circuit is used) Function setup by command entry (set by users) (24) Built-in oscillator circuit frequency select (23) Built-in oscillator circuit ON/OFF Enter the external clock (When the external LCD power supply circuit is used) Function setup by command entry (set by users) (25) Power control set 1. Step-up circuit ON 2. VC regulator circuit ON 3. LCDV circuit ON*2 External LCD power supply entry Initialization completed Note: *1 Display data RAM contents are not determined even in the initialized state after resetting. See “6.7 Reset Circuit” in the “6. Function Description”. *2 100ms or more should be kept from VC regulator circuit ON to LCDV circuit ON. * Numerals in the command parenthesis correspond to the numerals of the items in Command Description. Rev. 2.1 EPSON 47 S1D15E06 Series (2) Data display End of initialization Function setup by command entry (set by users) (6) Display start line set (7) Page address set (8) Column address set Function setup by command entry (set by users) (9) Display data write Function setup by command entry (set by users) (1) Display ON/OFF command End of data display Note: * Display data RAM contents are not determined after end of initialization. Write data to all the Display data RAM used for display. See “9. Display data write” in the “7. Command Description”. (3) Power OFF A desired state Function setup by command entry (set by users) (30) Power save ON (When an external LCD power supply circuit is used) External LCD power supply OFF (When the built-in power supply circuit is used) Function setup by command entry (set by users) (29) Discharge ON/OFF Reset state (RES terminal = LOW) Set the time (tL) between entry into the reset state and turning off of VDD-VSS power supply liquid crystal drive potential (MV1,VC,V1,V2) so that it is longer than the time (tH) where it is reduced below the threshold value of the LCD panel. VDD - VSS power supply OFF Note: * This IC controls the circuit of the liquid crystal drive power supply system using the VDD-VSS power supply circuit. If the VDD-VSS power supply is cut off with voltage remaining in the liquid crystal drive power supply system, voltage not controlled will be issued from the SEG and COM pins, and this may result in display failure. To avoid this, follow the above-mentioned power off sequence. 48 EPSON Rev. 2.1 S1D15E06 Series (4) How to change the duty A desired state Function setup by command entry (set by users) (1) Displya OFF Function setup by command entry (set by users) (30) Power save ON Function setup by command entry (set by users) (29) Discharge ON Function setup by command entry (set by users) (28) Electronic volume (24) Built-in oscillator circuit frequency select (18) Duty set When the n-line reversing command is used : (13) n-line reverse drive register set Secure an interval of 30ms or more between discharge ON to discharge OFF . Function setup by command entry (set by users) (29) Discharge OFF Function setup by command entry (set by users) (30) Power save OFF End of duty change Note: * Execution of the above sequence causes display to be turned off temporarily (for the time from Power Saving command ON to Power Saving command OFF plus 200 ms (frame frequency 60Hz) upon switching of the duty. Temporary display failure may occur if Duty Change command is executed during liquid crystal display without executing the above-mentioned setup example. Follow the setup example when the duty is changed as discussed above. (5) Refresh It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected noise. Refresh sequence NOP command Set all commands to the ready state (Including default state setting.) Refreshing of DRAM Rev. 2.1 EPSON 49 S1D15E06 Series 8. ABSOLUTE MAXIMUM RATINGS Table 8 Item Power voltage (1) Power voltage (2) Power voltage (3) Input voltage Output voltage Operating temperature Storage temperature Symbol VDD V3, VOUT V2, V1, VC, MV1, MV2 VIN VO TOPR TSTR VSS = 0V unless otherwise specified. Specified value –0.3 to +4.0 –0.3 to +17.0 –0.3 to V3 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –40 to +85 –55 to +100 –55 to +125 Unit V °C TCP bare chip V3 VOUT VC VCC VDD V2, V1,MV1,MV2 GND System (MPU) side VSS S1D15E06 side Fig. 8 Notes: 1. Voltages V 3 , V 2 , V 1 , V C , MV 1 , MV 2 a nd MV 3 ( V SS ) must always meet the conditions of V3≥V2≥V1≥VC≥MV1≥MV2≥MV3 (VSS). 2. Voltage VOUT must always meet the conditions of VOUT≥VDD and VOUT≥VC. 3. If the LSI has been used in excess of the absolute maximum rating, it may be subjected to permanent breakdown. So in the normal operation, the LSI is preferred to be used under the condition of electrical characteristics. If this condition is not met, LSI operation error may occur and LSI reliability may be deteriorated. 50 EPSON Rev. 2.1 S1D15E06 Series 9. DC CHARACTERISTICS VSS = 0V, VDD = 2.7V ± 10% and Ta = –40 to +85°C unless otherwise specified. Table 9.1 Item Working voltage (1) Operation enabled Symbol VDD Conditions Specified value Min. Typ. Max. 1.7 VDD Applicable to S1D15E06D01**** 3.4 1.7 VC VC VSS VSS 3.4 1.7 VC VC VSS VSS 0.8×VDD VSS — — — — — — — — — — — — — — — — — — — — 1.5 3.0 0.2 1.0 20 120 3.6 16.0 14.0 7.0 V3 V3 VC VC 16.0 8.0 V3 V3 VC VC VDD 0.2×VDD VDD 0.2×VDD 1.0 3.0 2.3 4.6 5.0 5.0 25 130 µA kΩ µA pF kHz *8 Unit V Applicable pin VDD *1 VOUT V3 * 2 VC V2 V1 MV1 MV2 V3 * 2 VC V2 V1 MV1 MV2 *3 *3 *4 *4 *5 *6 SEGn COMn *7 VDD V3 Working voltage (2) Operation recommended VOUT Working voltage (3) Operation enabled Operation enabled Operation enabled Operation enabled Operation enabled Operation enabled Working voltage (4) Operation enabled Operation enabled Operation enabled Operation enabled Operation enabled Operation enabled High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leak current Output leak current LCD driver ON resistance Static current consumption Input pin capacity Oscillation frequency Built-in oscillation V3 VC V2 V1 MV1 MV2 V3 VC V2 V1 MV1 MV2 VIHC VILC VOHC VOLC ILI ILO RON IDDQ I3Q CIN fOSC Applicable to S1D15E06D03**** VDD=1.7V to 3.6V VDD=1.7V to 3.6V IOH=–0.25mA 0.8×VDD IOL=0.25mA VSS –1.0 –3.0 — — — — — 110 VIN=VDD or VSS Ta=25°C V3=7.2V V3=4.8V Ta=25°C VDD=3.6V V3=14.0V Ta=25°C, f=1MHz Ta=25°C Max. frequency [* See the description on P.57.] Rev. 2.1 EPSON 51 S1D15E06 Series Table 9.2 Item Symbol VDD VDD VOUT VOUT VC Conditions Double boosting Triple boosting S1D15E06D01**** S1D15E06D03**** Specified value Min. Typ. Max. 1.7 1.7 — — 1.8 — — — — — 3.6 3.6 14.0 16.0 8.0 Unit V Applicable pin VDD VOUT VOUT VC * 9 Built-in power circuit Input voltage Boosted output voltage (1) Boosted output voltage (2) Working voltage for voltage control circuit Dynamic current consumption (1): Built-in power is turned on during display. Ta=25°C This is the current consumed by the entire IC including the built-in power supply. Display mode in 4 gray-scale at fFR = 80Hz Table 9.3 VDD 2.7V 3.6V Display entirely in white 1/132 Typ. 68 81 73 93 Code: ISS (1) DUTY Max. 112 134 121 154 1/100 Typ. 67 71 63 83 DUTY Max. 111 117 104 137 Unit µA Remarks *10 Boosting V3 Voltage Triple Double Triple 10V 12V 10V 12V Display mode in 4 gray-scale at fFR = 80Hz Table 9.4 VDD 2.7V 3.6V Display: Heavy load display 1/132 Typ. 241 373 189 380 Code: ISS (1) 1/100 Typ. 187 313 146 314 DUTY Max. 310 519 242 521 Unit µA Remarks *10 Boosting V3 Voltage Triple Double Triple 10V 12V 10V 12V DUTY Max. 400 619 313 630 Display mode in binary at fFR = 60Hz Table 9.5 VDD 2.7V 3.6V Display entirely in white 1/132 Typ. 65 72 57 82 Code: ISS (1) DUTY Max. 108 120 95 136 1/100 Typ. 50 56 44 63 DUTY Max. 83 93 73 104 Unit µA Remarks *10 Boosting V3 Voltage Triple Double Triple 10V 12V 10V 12V [* See the description on P.57.] 52 EPSON Rev. 2.1 S1D15E06 Series Display mode in binary at fFR = 60Hz Table 9.6 VDD 2.7V 3.6V Display Heavy load display 1/132 Typ. 188 313 150 322 Code: ISS (1) DUTY Max. 312 520 249 534 1/100 Typ. 135 226 108 232 DUTY Max. 224 300 143 308 Unit µA Remarks *10 Boosting V3 Voltage Triple Double Triple 10V 12V 10V 12V Current consumption under power saving mode: VSS = 0V, VDD = 3.3V, Ta = 25°C Table 9.7 Item Sleep state Symbol IDDS1 Condition Specified value Min. Typ. Max. — 0.2 5 Unit µA Remarks [* See the description on P.57.] Rev. 2.1 EPSON 53 S1D15E06 Series [Reference Data 1] • Dynamic current consumption (1) during LCD display when internal power is used 500 V3 = 12V Checker Conditions: V3 = 10V 250 Built-in power supply “ON” 1/132DUTY fFR = 80Hz Triple boosting Display mode : 4 gray-scale Indication pattern: Totally white / Checker Ta = 25°C Remarks: *11 ISS(1) [µA] V3 = 12V V3 = 10V Totally white 0 0 1 1.8 2 3 3.6 4 VDD [V] Fig. 9.1 [Reference Data 2] • Dynamic current consumption (2) during LCD display when internal power is used 500 V3 = 12V Checker 250 V3 = 10V Totally white V3 = 12V VDD = 2.7V Built-in power supply “ON” Triple boosting fFR = 80Hz Display mode : 4 gray-scale Indication pattern : Totally white / Checker Ta = 25°C Remarks: *11 Conditions: ISS(2) [µA] V3 = 10V 0 16 32 64 1/DUTY 132 Fig. 9.2 [* See the description on P.57.] 54 EPSON Rev. 2.1 S1D15E06 Series [Reference Data 3] • Dynamic current consumption (3) during access 10 Indicates the current consumption when the checker pattern is always written by f CYC . When not accessed, only ISS(1) remains. Conditions: Built-in voltage used Triple boosting V3= 12.0V, VDD = 2.7V Ta = 25°C fFR=80Hz 1/132 Duty 1 ISS(3) [mA] 0.1 0.01 0.001 0.01 0.1 1 10 fCYC [MHz] Fig. 9.3 Rev. 2.1 EPSON 55 S1D15E06 Series [Reference Data 4] • Operating voltage range (S1D15E06D01****) 14.0 Remarks: *2 10.5 Operating range 7.0 V3 [V] 3.5 3.4 0 0 1 1.7 2 VDD [V] 3 3.6 4 Fig. 9.4.1 • Operating voltage range (S1D15E06D03****) 16.0 14.0 Remarks: *2 Operating range V3 [V] 3.4 0 0 1 1.7 2 VDD [V] 3 3.6 4 Fig. 9.4.2 [* See the description on P.57.] 56 EPSON Rev. 2.1 S1D15E06 Series • Relationship between oscillation frequency fOSC, display clock frequency fCL and liquid crystal frame fFR Table 9.8 Item Built-in oscillator circuit used Built-in oscillator circuit not used fCL See p. 24 External input (fCL) Display mode Binary display 4 gray-scale Binary display 4 gray-scale fFR (fCL × DUTY)/4 (fCL × DUTY)/8 (fCL × DUTY)/4 (fCL × DUTY)/8 (fFR indicates the cycle of rewriting one screen; it does not indicate FR signal cycle.) [Asterisked references] *1. Does not guarantee if there is an abrupt voltage variation during MPU access. *2. For VDD and V3 system operating voltage range, see Fig. 9.5. Applicable when the external power supply is used. *3. A0, D0 to D5, D6(SCL), D7(SI), RD(E), WR(R/W), CS1, CS2, CLS, CL, FR, F1, F2, CA, M/S, C86, P/S, DOF, RES and TEST pins *4. D0 to D7, FR, DOF, CL, F1, F2 and CA pins *5. A0, RD(E), WR(R/W), CS1, CS2, CLS, M/S, C86, P/S, RES and TEST pins *6. Applicable when D0 to D5, D6(SCL), D7(S1), CL, FR, DOF, F1, F2 and CA pins have a high impedance. *7. Indicates the resistance when 0.1V voltage is applied between the output pin SEGn or COMn and each power supply (V2, V1, VC, MV1, MV2). RON =0.1V/∆I (where ∆I denotes current when 0.1V is applied when power is on). *8. For the relationship between oscillation frequency and frame frequency, see Table 9.8. The standard values of the external input item are recommended ones. *9. The VC voltage regulating circuit should be adjusted within the electronic volume operation range. *10. Indicates the current consumed by a single IC when display is on. Use the electronic volume for voltage regulation. Also use the internal oscillator circuit. The current due to LCD panel capacity and wiring capacity is not included. Applicable when there is access from the MPU. Rev. 2.1 EPSON 57 S1D15E06 Series 10. TIMING CHARACTERISTICS (1) System path read/write characteristics 1 (80 system MPU) A0 tAW8 CS1 (CS2=“1”) *1 WR, RD tAH8 tCYC8 tCCLR, tCCLW tCCHR, tCCHW CS1 (CS2=“1”) *2 WR, RD tf tr tDS8 D0 to D7 (Write) tDH8 tACC8 D0 to D7 (Read) tOH8 Fig. 10.1 Table 10.1.1 [VDD = 3.0V to 3.6V, Ta = –40 to +85°C] Parameter Address hold time Address setup time System write cycle time System read cycle time Control LOW-pulse width (Write) Control LOW-pulse width (Read) Control HIGH-pulse width (Write) Control HIGH-pulse width (Read) Data setup time Data hold time RD access time Output disable time Signal A0 WR RD Symbol Condition Specified value Min. 0 0 200 300 60 100 60 100 20 10 CL=100pF — 10 Max. — — — — — — — — — — 80 80 Unit ns tAH8 tAW8 tWCYC8 tRCYC8 WR tCCLW RD tCCLR WR tCCHW RD tCCHR D0 to D7 tDS8 tDH8 tACC8 tOH8 58 EPSON Rev. 2.1 S1D15E06 Series Table 10.1.2 [VDD = 2.4V to 3.0V, Ta = –40 to +85°C] Parameter Address hold time Address setup time System write cycle time System read cycle time Control LOW-pulse width (Write) Control LOW-pulse width (Read) Control HIGH-pulse width (Write) Control HIGH-pulse width (Read) Data setup time Data hold time RD access time Output disable time Signal A0 WR RD Symbol Condition Specified value Min. 0 0 300 400 80 200 80 200 30 15 CL=100pF — 10 Max. — — — — — — — — — — 120 120 Unit ns tAH8 tAW8 tWCYC8 tRCYC8 WR tCCLW RD tCCLR WR tCCHW RD tCCHR D0 to D7 tDS8 tDH8 tACC8 tOH8 Table 10.1.3 [VDD = 1.7V to 2.4V, Ta = –40 to +85°C] Parameter Signal A0 WR RD Symbol Condition Specified value Min. 0 0 400 600 100 250 140 250 40 20 CL=100pF — 10 Max. — — — — — — — — — — 200 200 Unit ns Address hold time Address setup time System write cycle time System read cycle time Control LOW-pulse width (Write) Control LOW-pulse width (Read) Control HIGH-pulse width (Write) Control HIGH-pulse width (Read) Data setup time Data hold time RD access time Output disable time tAH8 tAW8 tWCYC8 tRCYC8 WR tCCLW RD tCCLR WR tCCHW RD tCCHR D0 to D7 tDS8 tDH8 tACC8 tOH8 *1. This is in case of making the access by WR and RD, setting the CS1 = LOW. *2. This is in case of making the access by CS1, setting the WR, RD = LOW. *3. Input signal rise and fall time (tr, tf) must not exceed 15 ns. When the system cycle time is used at a high speed, it is specified by (tr + tf) ≤ (tCYC8 – tCCLW – tCCHW) or (tr + tf) ≤ (tCYC8 – tCCLR – tCCHR). *4. Timing is entirely specified with reference to 20% or 80% of VDD. *5. tCCLW and tCCLR are specified in terms of the overlapped period when CS1 is at LOW (CS2 = HIGH) level and WR and RD are at LOW level. Rev. 2.1 EPSON 59 S1D15E06 Series (2) System path read/write characteristics 2 (68 system MPU) A0 R/W tAW6 CS1 (CS2=“1”) *1 tAH6 tCYC6 tEWHR, tEWHW E tEWLR, tEWLW CS1 (CS2=“1”) *2 E tf tr tDS6 D0 to D7 (Write) tDH6 tACC6 D0 to D7 (Read) tOH6 Fig. 10.2 Table 10.2.1 [VDD = 3.0V to 3.6V, Ta = –40 to +85°C] Parameter Address hold time Address setup time System write cycle time System read cycle time Data setup time Data hold time Access time Output disable time Enable HIGH-pulse width Read Write Enable LOW-pulse width Read Write Signal A0 E Symbol Condition Specified value Min. 0 0 200 300 20 10 CL=100pF — 10 100 60 100 60 Max. — — — — — — 80 80 — — — — Unit ns tAH6 tAW6 tWCYC6 tRCYC6 D0 to D7 tDS6 tDH6 tACC6 tOH6 E tEWHR tEWHW E tEWLR tEWLW 60 EPSON Rev. 2.1 S1D15E06 Series Table 10.2.2 [VDD = 2.4V to 3.0V, Ta = –40 to +85°C] Parameter Address hold time Address setup time System write cycle time System read cycle time Data setup time Data hold time Access time Output disable time Enable HIGH-pulse width Read Write Enable LOW-pulse width Read Write Signal A0 E Symbol Condition Specified value Min. 0 0 300 400 30 15 CL=100pF — 10 150 80 150 80 Max. — — — — — — 120 120 — — — — Unit ns tAH6 tAW6 tWCYC6 tRCYC6 D0 to D7 tDS6 tDH6 tACC6 tOH6 E tEWHR tEWHW E tEWLR tEWLW Table 10.2.3 [VDD = 1.7V to 2.4V, Ta = –40 to +85°C] Parameter Address hold time Address setup time System write cycle time System read cycle time Data setup time Data hold time Access time Output disable time Enable HIGH-pulse width Read Write Signal A0 E Symbol Condition Specified value Min. 0 0 400 600 40 20 CL=100pF — 10 250 100 Max. — — — — — — 200 200 — — Unit ns tAH6 tAW6 Enable LOW-pulse width Read 250 — Write 140 — *1 This is in case of making the access by E, setting the CS1 = LOW. *2 This is in case of making the access by CS1, setting the E = HIGH. *3 The rise time and the fall time (tr & tf) of the input signals should be set to 15ns or less. When it is necessary to use the system cycle time at high speed, the rise time and the fall time should be so set to conform to (tr+tf) ≤ (tCVC6-tEWLW-tEWHW) or (tr+tf) ≤ (tCYC6-tEWLR-tEWHR). *4 All the timing should basically be set to 20% and 80% of the “VDD”. *5 tEWLW, tEWLR should be set to the overlapping zone where the CS1 is on the LOW level (CS2 = HIGH level) and where the E is on the HIGH level. tWCYC6 tRCYC6 D0 to D7 tDS6 tDH6 tACC6 tOH6 E tEWHR tEWHW E tEWLR tEWLW Rev. 2.1 EPSON 61 S1D15E06 Series (3) Serial interface CS1 (CS2=“1”) tCSS tCSH tSAS A0 tSAH tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH Figure 10.3 Table 10.3.1 [VDD = 3.0V to 3.6V, Ta = –40 to +85°C] Parameter Serial clock period SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal SCL Symbol Condition Specified value Min. 100 40 40 80 80 20 20 80 150 Max. — — — — — — — — — Unit ns A0 SI CS tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH 62 EPSON Rev. 2.1 S1D15E06 Series Table 10.3.2 [VDD = 2.4V to 3.0V, Ta = –40 to +85°C] Parameter Signal SCL Symbol Condition Specified value Min. 125 50 50 100 100 30 30 100 200 Max. — — — — — — — — — Unit ns Serial clock period SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time A0 SI CS tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Table 10.3.3 [VDD = 1.7V to 2.4V, Ta = –40 to +85°C] Parameter Signal SCL Symbol Condition Specified value Min. 154 60 60 120 140 40 40 120 350 Max. — — — — — — — — — Unit ns Serial clock period SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time A0 SI CS tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH *1. Input signal rise and fall time (tr, tf) must not exceed 15 ns. *2. Timing is entirely specified with reference to 20% or 80% of VDD. Rev. 2.1 EPSON 63 S1D15E06 Series (4) Display control output timing CL (OUT) tDFR FR tDF1,F2 F1, F2 tDCA CA Fig. 10.4 Table 10.4.1 [VDD = 3.0V to 3.6V, Ta = –40 to +85°C] Signal FR F1, F2 CA Symbol Condition CL = 50pF Specified value Min. — — — Typ. 125 125 125 Max. 312 312 312 Unit ns ns ns Parameter FR delay time F1, F2 delay time CA delay time tDFR tDF1, tF2 tDCA Table 10.4.2 [VDD = 2.4V to 3.0V, Ta = –40 to +85°C] Signal FR F1, F2 CA Symbol Condition CL = 50pF Specified value Min. — — — Typ. 150 150 150 Max. 360 360 360 Unit ns ns ns Parameter FR delay time F1, F2 delay time CA delay time tDFR tDF1, tF2 tDCA Table 10.4.3 [VDD = 1.7V to 2.4V, Ta = –40 to +85°C] Parameter FR delay time F1, F2 delay time CA delay time Signal FR F1, F2 CA Symbol Condition CL = 50pF Specified value Min. — — — Typ. 225 225 225 Max. 514 514 514 Unit ns ns ns tDFR tDF1, tF2 tDCA *1. Valid only in master operation *2. Timing is entirely specified with reference to 20% or 80% of VDD. 64 EPSON Rev. 2.1 S1D15E06 Series (5) Reset input timing tRW RES tR Internal state During resetting End of resetting Fig. 10.5 Table 10.5.1 [VDD = 3.0V to 3.6V, Ta = –40 to +85°C] Parameter Reset time Reset LOW pulse width RES Signal Symbol Condition Specified value Min. — 0.5 Typ. — — Max. 0.5 — Unit µs tR tRW Table 10.5.2 [VDD = 2.4V to 3.0V, Ta = –40 to +85°C] Parameter Reset time Reset LOW pulse width RES Signal Symbol Condition Specified value Min. — 1.0 Typ. — — Max. 1.0 — Unit µs tR tRW Table 10.5.3 [VDD = 1.7V to 2.4V, Ta = –40 to +85°C] Parameter Reset time Reset LOW pulse width RES Signal Symbol Condition Specified value Min. — 1.5 Typ. — — Max. 1.5 — Unit µs tR tRW *1. Timing is entirely specified with reference to 20% or 80% of VDD. Rev. 2.1 EPSON 65 S1D15E06 Series 11. MPU INTERFACE (Reference Example) The S1D15E06 series can be connected to the 80 series MPU and 68 series MPU. Use of a serial interface allows operation with a smaller number of signal lines. You can expand the display area using the S1D15E06 series as a multi-chip. In this case, the IC to be accesses can be selected individually by the chip select signal. After initialization by the RES pin, each input terminal of the S1D15E06 series must be placed under normal control. (1) 80 series MPU VDD VCC A0 A0 Decoder CS1 CS2 D0 to D7 RD WR RES VSS A1 to A7 IORQ VDD C86 S1D15E06 Series MPU D0 to D7 RD WR RES GND P/S RESET VSS Fig. 11.1 (2) 68 series MPU VDD VCC A0 MPU VDD A0 Decoder CS1 CS2 D0 to D7 E R/W RES VSS C86 S1D15E06 Series A1 to A15 VMA D0 to D7 E R/W RES GND P/S RESET VSS Fig. 11.2 (3) Serial interface VDD VCC A0 A1 to A7 MPU VDD A0 Decoder CS1 CS2 SI SCL RES VSS C86 S1D15E06 Series VDD or VSS Port 1 Port 2 RES GND RESET P/S VSS Fig. 11.3 66 EPSON Rev. 2.1 S1D15E06 Series 12. CONNECTION BETWEEN LCD DRIVERS (Reference example) You can easily expand the liquid crystal display area using the S1D15E06 series as a multi-chip. In this case, use the same model as the master and slave systems. S1D15E06 (Master) VDD VSS M/S CL FR DOF F1 F2 CA CLS V3 V2 V1 VC MV1 MV2 (VSS) MV3 M/S CL FR DOF F1 F2 CA CLS V3 V2 V1 VC MV1 MV2 MV3 (VSS) VDD S1D15E06 (Slave) Fig. 12 Master/slave connection example (S1D15E06) Rev. 2.1 EPSON 67 S1D15E06 Series 13. LCD PANEL WIRING (Reference example) You can easily expand the liquid crystal display area using the S1D15E06 series as a multi-chip. In the case of multichip configuration, use the same models. (1) Single chip configuration example 160 x 132 Dots COM S1D15E06 Master SEG COM Fig. 13.1 Single chip configuration example (S1D15E06) (2) Double chip configuration example 320 x 132 Dots COM SEG S1D15E06 Master SEG S1D15E06 Slave COM Fig. 13.2 Double chip configuration example (S1D15E06) 68 EPSON Rev. 2.1 S1D15E06 Series 14. S1D15E06T00A*** TCP PIN LAYOUT Note: This does not specify the TCP outside shape. Reference COM131 VSS FR CL DOF F1 F2 CA TEST CS1 RES A0 WR, R/W RD, E CS2 M/S CLS C86 P/S D0 D1 D2 D3 D4 D5 D6, SCL D7, SI VSS VDD VOUT CAP1+ CAP1– CAP2– CAP2+ CAP3+ CAP3– CAP4– CAP4+ V3 V2 V1 VC MV1 MV2 (VSS)MV3 CPP+ CPP– CPM+ CPM– COM130 COM129 COM128 • • • • • COM 67 COM 66 SEG 159 SEG 158 CHIP TOP VIEW • • • • • • SEG 1 SEG 0 COM 0 COM 1 COM 2 COM 3 • • • • • COM 64 COM 65 Rev. 2.1 EPSON 69 S1D15E06 Series 15. TCP DIMENSIONS (Reference example) 70 EPSON Rev. 2.1 S1D15E06 Series 16. CAUTIONS Cautions must be exercised on the following points when using this Development Specification: 1. This Development Specification is subject to change for engineering improvement. 2. This Development Specification does not guarantee execution of the industrial proprietary rights or other rights, or grant a license. Examples of applications described in This Development Specification are intended for your understanding of the Product. We are not responsible for any circuit problem or the like arising from the use of them. 3. Reproduction or copy of any part or whole of this Development Specification without permission of our company, or use thereof for other business purposes is strictly prohibited. For the use of the semi-conductor,cautions must be exercised on the following points: [Cautions against Light] The semiconductor will be subject to changes in characteristics when light is applied. If this IC is exposed to light, operation error may occur. To protect the IC against light, the following points should be noted regarding the substrate or product where this IC is mounted: (1) Designing and mounting must be provided to get a structure which ensures a sufficient resistance of the IC to light in practical use. (2) In the inspection process, environmental configuration must be provided to ensure a sufficient resistance of the IC to light. (3) Means must be taken to ensure resistance to light on all the surfaces, backs and sides of the IC Rev. 2.1 EPSON 71