S1D13742F01A200

S1D13742 Mobile Graphics Engine Hardware Functional Specification Document Number: X63A-A-001-06.6 Rev. 6.6 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. When exporting the products or technology described in this material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes. All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ©SEIKO EPSON CORPORATION 2004-2018. All rights reserved. 2 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Features . . . . . . . . . . 2.1 Integrated Frame Buffer 2.2 CPU Interface . . . . 2.3 Input Data Formats . . 2.4 Display Support . . . . 2.5 Display Modes . . . . 2.6 Display Features . . . 2.7 Clock Source . . . . . 2.8 Miscellaneous . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Pinout Diagram . . . . . . . . . . . 4.1 Pin-Out . . . . . . . . . . . 4.2 Pin Descriptions . . . . . . . 4.2.1 Intel 80 Host Interface . . . . 4.2.2 LCD Interface . . . . . . . . 4.2.3 Clocks . . . . . . . . . . . . 4.2.4 Miscellaneous . . . . . . . . 4.2.5 Power And Ground . . . . . 4.3 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 13 14 14 15 16 17 5 Pin Mapping . . . . . . . . . . . 5.1 Intel 80 Data Pins . . . . . 5.2 LCD Interface Pin Mapping . 5.3 LCD Interface Data Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 19 20 6 D.C. Characteristics . . . . . . . . . 6.1 Absolute Maximum Ratings . . . . 6.2 Recommended Operating Conditions 6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 22 7 A.C. Characteristics . . 7.1 Clock Timing . . . 7.1.1 Input Clocks . . 7.1.2 PLL Clock . . . 7.2 RESET# Timing . . 7.3 Host interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 26 28 29 S1D13742 Hardware Functional Specification Rev. 6.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Seiko Epson Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 .8 .8 .8 .8 .8 .9 .9 .9 3 7.3.1 Intel 80 Interface Timing - 1.8 Volt . . . . . . . 7.3.2 Intel 80 Interface Timing - 3.3 Volt . . . . . . . 7.3.3 Definition of Transition Time to Hi-Z State . . . 7.4 Display Interface . . . . . . . . . . . . . . . 7.4.1 TFT Power-On Sequence . . . . . . . . . . . . 7.4.2 TFT Power-Off Sequence . . . . . . . . . . . . 7.4.3 18/36-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Clocks . . . . . . . . . . . . . 8.1 Clock Descriptions . . . . 8.2 PLL Block Diagram . . . 8.3 Clocks versus Functions . . 8.4 Setting SYSCLK and PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Registers . . . . . . . . . . . . . . . . . 9.1 Register Mapping . . . . . . . . . 9.2 Register Set . . . . . . . . . . . . 9.3 Register Descriptions . . . . . . . . 9.3.1 Read-Only Configuration Registers 9.3.2 Clock Configuration Registers . . 9.3.3 Panel Configuration Registers . . . 9.3.4 Input Mode Register . . . . . . . . 9.3.5 Display Mode Registers . . . . . . 9.3.6 Window Settings . . . . . . . . . . 9.3.7 Memory Access . . . . . . . . . . 9.3.8 Gamma Correction Registers . . . 9.3.9 Miscellaneous Registers . . . . . . 9.3.10 General Purpose IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 . . . . .43 . . . . .44 . . . . .45 . . . . . . 45 . . . . . . 46 . . . . . . 51 . . . . . . 54 . . . . . . 59 . . . . . . 63 . . . . . . 65 . . . . . . 67 . . . . . . 69 . . . . . . 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 . . 31 . . 33 . .34 . . 35 . . 36 . . 37 . . . . . .39 .39 .40 .41 .42 10 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11 Intel 80, 8-bit Interface Color Formats . . . . . . . 11.1 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors 11.2 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 11.3 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 .74 .75 .76 12 Intel 80, 16-bit Interface Color Formats . . . . . . . . . . . 12.1 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors . . . . . . 12.2 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 12.3 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 12.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors 12.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 .77 .78 .79 .80 .81 13 YUV Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 13.1 YUV 4:2:2 with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . . . . . . .83 4 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 13.2 13.3 13.4 13.5 13.6 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface . . YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface . YUV 4:2:2 with Intel 80, 16-bit Interface . . . . . . YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface . YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 84 85 86 87 14 Gamma Correction Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . 88 14.1 Gamma Correction Example Programming . . . . . . . . . . . . . . . . . . . 89 15 Display Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16 SwivelView™ . . . . . . . . . . . . 16.1 Concept . . . . . . . . . . . 16.2 90° SwivelView™ . . . . . . 16.2.1 Register Programming . . . 16.3 180° SwivelView™ . . . . . . 16.3.1 Register Programming . . . 16.4 270° SwivelView™ . . . . . . 16.4.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 94 94 94 95 95 96 96 17 Host Interface . . . . . . . . . . . . . . . . . . . . 17.1 Using the Intel 80 Interface . . . . . . . . . . 17.1.1 Register write procedure . . . . . . . . . . . 17.1.2 Register read procedure . . . . . . . . . . . . 17.1.3 New Window Aperture Write procedure . . . 17.1.4 Opening Multiple Windows . . . . . . . . . . 17.1.5 Individual Memory Location Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 . . . . . . 97 . . . . . . . . 97 . . . . . . . . 98 . . . . . . . . 99 . . . . . . . . 101 . . . . . . . . 101 18 Double Buffer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 18.1 Double Buffer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19 Interfacing the S1D13742 and a TFT Panel . . . . . . . 19.1 Overview . . . . . . . . . . . . . . . . . . . 19.1.1 Electrical Interface . . . . . . . . . . . . . . . . . 19.1.2 S1D13742 Register Settings for 352x416 TFT Panel 19.1.3 S1D13742 Register Settings for 800x480 TFT Panel 19.2 Host Bus Timing . . . . . . . . . . . . . . . . 19.2.1 Host Bus Timing for 352x416 TFT Panel . . . . . . 19.2.2 Host Bus Timing for 800x480 TFT Panel . . . . . . 19.3 Panel Timing . . . . . . . . . . . . . . . . . . 19.3.1 Panel Timing for 352x416 Panel . . . . . . . . . . 19.3.2 Panel Timing for 800x480 Panel . . . . . . . . . . 19.4 Example Play.exe Scripts . . . . . . . . . . . . . 19.5 References . . . . . . . . . . . . . . . . . . . 19.5.1 Documents . . . . . . . . . . . . . . . . . . . . . . S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 . . . . . . 105 . . . . . . . . 105 . . . . . . . . 106 . . . . . . . . 108 . . . . . . 110 . . . . . . . . 111 . . . . . . . . 112 . . . . . . 113 . . . . . . . . 114 . . . . . . . . 114 . . . . . . 115 . . . . . . 121 . . . . . . . . 121 5 20 PLL Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 122 20.1 Guidelines for PLL Power Layout . . . . . . . . . . . . . . . . . . . . . . 122 21 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 22 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 23 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Introduction 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13742 Embedded Memory LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check the Epson Research and Development Website at vdc.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at vdc-documentation@ea.epson.com. 1.2 Overview Description The S1D13742 is a color LCD graphics controller with an embedded 768K byte display buffer. The S1D13742 supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into display memory allowing for fast screen updates. Products requiring a rotated display image can take advantage of the SwivelView™ feature which provides hardware rotation of the display memory transparent to the software application. Resolutions supported include 800x480 single buffered and 352x416 double buffered. The S1D13742 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates. S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 7 Features 2 Features 2.1 Integrated Frame Buffer • Embedded 768K byte SRAM display buffer. 2.2 CPU Interface • 8/16-bit Intel 80 interface (used for display or register data). • Chip select is used to select device. When inactive, any input data/command will be ignored. 2.3 Input Data Formats • RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). • YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as 16 or 18 bpp). Note All input data must be internally converted to the same format before being stored in the display buffer. Different data types can not be mixed within a common display buffer. 2.4 Display Support • Active Matrix TFT interface. • 18/36-bit interface. • Supports resolutions up to 800x480. 2.5 Display Modes • 16/18 bit-per-pixel (bpp) color depths. • 16 bpp to 18 bpp conversion: Input data can be converted from 16 bpp to 18 bpp in one of three ways. 1. RGB (5:6:5) msb copying to create new lsb for the Red and Blue components. This conversion is done prior to storing in memory, as this allows for 16 bpp and 18 bpp input data to be mixed. 2. Gamma Correction Look-Up-Tables: there are three, 64 position, 8-bit wide LUT’s. The data stored in memory can be used as an index into these tables. The LUT’s are placed on the display side and therefore do not affect the data stored in memory. 3. RGB (5:6:5) stored in memory: LUT is by-passed. Copy msb to lsb for red and blue during the display read from memory. 8 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Features 2.6 Display Features • All display writes will be handled by window apertures/position for complete or partial display updates. All window coordinates are referenced to top left corner of the displayed image (even in a rotated display, the top-left corner is maintained and no host side translation need take place). • SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image. All displayed windows can have independent rotation. No additional programming necessary when enabling these modes. • Double-Buffer available to prevent image tearing during streaming input. Resolutions supported must fit inside 384K bytes (½ of total available display buffer). Typical resolution of 352x416. • Pixel Doubling: Horizontal and Vertical averaging for smooth doubling of a single window. • Pixel Halving: no limitation on number of windows. 2.7 Clock Source • Internal programmable PLL. • Single MHz clock input: CLKI. • CLKI available as CLKOUT (separate CLKOUTEN pin associated with output). • output state = 0 when disabled. 2.8 Miscellaneous • Hardware / Software Power Save mode. • Input pin to Enable/Disable Power Save Mode. • General Purpose Input/Output pins are available (GPIO[7:0]). • INT pin associated with selectable GPIO inputs. • Package: S1D13742 Hardware Functional Specification Rev. 6.6 QFP20 144-pin package Seiko Epson Corporation 9 Block Diagram 3 Block Diagram MClk Data Control Intel 80 8/16 IF MClk YUV Converter MClk YUV to RGB MClk Rotation (Pixel Halving) MClk Memory Controller MClk PClk LCD Disp Pipe PClk PClk Gamma Correction LCD IF Registers RegWrClk MClk Clocks Test Mux Double Buffer Controller PClk LCD Ctc Figure 3-1: Block Diagram 10 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Pinout Diagram 4 Pinout Diagram NC NC NC VSS COREVDD VSS IOVDD MD0 MD11 GPIO_INT TE RESET# TESTEN SCANEN TEST2 TEST1 TEST0 CNF0 VSS COREVDD GPIO0 GPIO1 CNF1 CNF2 GPIO3 GPIO2 GPIO4 GPIO5 PWRSVE GPIO6 VSS IOVDD NC NC NC NC 4.1 Pin-Out 73 108 MD2 MD1 MD12 VSS IOVDD CLKOUT CLKOUTEN VSS COREVDD CLKI VSS IOVDD PLLVDD VCP PLLVSS MD13 MD3 MD4 MD14 IOVDD VSS CS# MD15 MD5 MD6 COREVDD VSS MD8 WE# RD# MD9 MD7 MD10 D/C# IOVDD VSS 109 108 107 106 105 104 103 102 101 100 99 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 144 72 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 INDEX 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 NC GPIO7 VSS PIOVDD VSS COREVDD VD6 VD5 VD13 VD21 VD4 VD12 VD20 VD3 VD11 VD19 VSS PIOVDD VD2 VSS PIOVDD VD10 VD18 VD1 VD9 VD17 VD25 VD0 VD8 VD16 VD7 VSS COREVDD VSS PIOVDD NC NC NC NC PIOVDD VSS COREVDD VSS DE HS VS PCLK VD34 VD35 VD33 VD32 VD31 PIOVDD VSS VD30 PIOVDD VSS VD26 VD27 VD28 VD29 VD24 VD23 VD22 VD15 VD14 COREVDD VSS PIOVDD VSS NC NC 36 Figure 4-1: S1D13742 QFP20 Pinout (Top View) S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 11 Pinout Diagram 4.2 Pin Descriptions Key: Pin Types I O IO P = = = = Input Output Bi-Directional (Input/Output) Power pin RESET# / Power Save Status H = High level output L = Low level output Hi-Z = High Impedance Table 4-1: Cell Description Item HI Description 1 H System LVCMOS3 Input Buffer HIS H System LVCMOS Schmitt Input Buffer HID H System LVCMOS Input Buffer with pull-down resistor HO H System LVCOMOS Output buffer HB H System LVCMOS Bidirectional Buffer HBD H System LVCMOS Bidirectional Buffer with pull-down resistor HB_DSEL H System LVCMOS Bidirectional Buffer with Drive Selector LIDS L System2 LVCMOS Schmitt Input Buffer with pull-down resistor LITR L System Transparent Input Buffer 1 H System is IOVDD and PIOVDD (see Section 6, “D.C. Characteristics”). L System is COREVDD (see Section 6, “D.C. Characteristics”). 3 LVCMOS is Low Voltage CMOS (see Section 6, “D.C. Characteristics”). 2 12 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Pinout Diagram 4.2.1 Intel 80 Host Interface Table 4-2: Host Interface Pin Descriptions Pin Name Type QFP Pin # Cell IO RESET# Voltage State Power Save Status Description Intel 80 Data lines. MD[15:0] IO 131,127, 124,111, 100,141, 139,136, 140,133, 132,126, 125,109, 110,101 HB IOVDD Hi-Z Hi-Z • For the S1D13742B00, when the 8-bit bus interface is selected by CNF1, MD[15:8] are pulled low by internal resistors. • For the S1D13742B01, when the 8-bit bus interface is selected by CNF1, MD[15:8] should be connected to VSS. Note: The Host Data lines can be swapped (i.e. MD15 = MD0) using the CNF0 pin. For details, see Section 4.3, “Summary of Configuration Options” on page 17. WE# I 137 HI IOVDD Input Input This input pin is the Write Enable signal. RD# I 138 HI IOVDD Input Input This input pin is the Read Enable signal. CS# I 130 HI IOVDD Input Input This input pin is the Chip Select signal. D/C# I 142 HI IOVDD Input Input This input pin is used to select between Intel 80 address and data TE O 98 HO IOVDD L L GPIO_INT O 99 HO IOVDD L RESET# I 97 HI IOVDD Input S1D13742 Hardware Functional Specification Rev. 6.6 Tearing Effect: this pin will reflect the VSYNC, HSYNC or the OR’d combination status of the display. This interrupt pin is associated with selected GPIO pins when configured as inputs or outputs. Interrupt Output functionality is not affected by Power Save. See Section 9.3.10, “General Purpose IO Pins Registers” on page 71 for operational description. Input Active low input to set all internal registers to the default state and to force all signals to their inactive states. Seiko Epson Corporation 13 Pinout Diagram 4.2.2 LCD Interface Table 4-3: LCD Interface Pin Descriptions Pin Name VD[35:0] IO RESET# Voltage State Type QFP Pin # IO 13,12,14,15, 16,19,25,24, 23,22,46,26, 27,28,63,60, 57,50,47,43, 29,30,64,61, 58,51,48,44, 42,66,65,62, 59,54,49,45 HB_ DSEL 10 HO PIOVDD VS O Cell Power Save Status Description Panel Data bits 35-0. VD[35:0] are used for all modes. In 2 pixels/clock mode, VD[17:0] represent the 1st pixel sent in a 2 pixel/clock operation. PIOVDD L L Note: The Panel Data Lines can be swapped (i.e. VD23 = VD0) using the VD Data Swap bit, REG[14h] bit 7. Note: The VD output drive is selectable between 2.5mA and 6.5mA using the CNF2 pin. For details, see Section 4.3, “Summary of Configuration Options” on page 17. H L This output pin is the Vertical Sync pulse HS O 9 HO PIOVDD H L This output is the Horizontal Sync pulse PCLK O 11 HO PIOVDD CLKI L This output pin is the Data Clock DE O 8 HO PIOVDD L L This output pin is the Data Enable Note The LCD interface requires a separate power rail (PIOVDD) to support the configurable IO drive. For details, see the CNF2 description in Section 4.3, “Summary of Configuration Options” on page 17. Note Input of VD[35:0] is used for production test only. 4.2.3 Clocks Table 4-4: Clock Input Pin Descriptions Pin Name Type QFP Pin # Cell IO RESET# Voltage State CLKI I 118 HIS IOVDD Input Power Save Status Input Description MHz input for PLL operation or MHz input if PLL is bypassed Input frequency range: 1MHz ~ 33MHz CLKOUT O 114 HO IOVDD L CLKI CLKOUTEN I 115 HI IOVDD Input Input 14 This output pin represents the CLKI pin if enabled by CLKOUTEN. When disabled the output is low. Note: this output is not affected by the various power save modes This pin enables/disables the CLKOUT pin. Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Pinout Diagram 4.2.4 Miscellaneous Table 4-5: Miscellaneous Pin Descriptions Pin Name CNF[2:0] Type I QFP Pin # 85,86,91 Cell HI IO RESET# Voltage State IOVDD Input Power Save Status Input Description These inputs are used for power-up configuration. For details, see Section 4.3, “Summary of Configuration Options” on page 17. Note: These pins must be connected directly to IOVDD or VSS. Test Enable input used for production test only This pin should be left unconnected for normal use. TESTEN I 96 LIDS IOVDD — — GPIO[7:0] IO 71,79,81, 82,84,83, 87,88 HBD IOVDD L Pull Down Active These pins are general purpose input/output pins. These pins have internal pull-down resistors which can be controlled using REG[64h]. PWRSVE I 80 HI IOVDD Input Input This pin enables/disables the Standby Power Save Mode When unused this pin must be connected to VSS. TEST[2:0] SCANEN VCP NC I I 94,93,92 95 HID HID IOVDD IOVDD — — — These are Test Function pins and are used for production test only. These pins should be left unconnected for normal operation. — This is the Test Scan Enable input and is used for production test only. This pin should be left unconnected for normal operation. I 122 LITR PLLVDD — — This is the PLL VCP Test pin and is used for production test only. This pin should be left unconnected for normal operation. — 1,2,3, 35,36, 37,72, 73,74, 75,76, 106,107, 108 — — — — These pins are not connected. S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 15 Pinout Diagram 4.2.5 Power And Ground Table 4-6: Power And Ground Pin Descriptions Pin Name Type QFP Pin # Cell COREVDD P 6,31,40,67,89, 104,117,134 P Core power supply IOVDD P 77,102,113, 120,128,143 P IO power supply for the host interface PIOVDD P 4,17,20,33,38, 52,55,69 P IO power supply for the panel interface Description PLLVDD P 121 P PLL power supply PLLVSS P 123 P GND for PLL P 5,7,18,21,32, 34,39,41,53, 56,68,70,78, 90,103,105, 112,116,119, 129, 135,144 P GND VSS 16 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Pinout Diagram 4.3 Summary of Configuration Options These pins are used for power-up configuration and must be connected directly to IOVDD or VSS. The state of CNF[2:0] may be changed at any time. Table 4-7: Summary of Power-On/Reset Options Configuration Input Power-On/Reset State 1 (connected to IOVDD) 0 (Connected to VSS) CNF0 Host Data Lines are normal: If CNF1 = 1, then D15 = D15, etc. If CNF1 = 0, then D7 = D7, etc. Host Data Lines are swapped: If CNF1 = 1, then D15 = D0, etc. If CNF1 = 0, then D7 = D0, etc. CNF1 Host Data is 16-bit Host Data is 8-bit CNF2 PIOVDD output current (IOL2) = 6.5mA PIOVDD output current (IOL2) = 2.5mA Note When CNF1=0, all Register access is 8-bit only. When CNF1 =1 (16-bit): All Register access is 8-bit ONLY (the most significant byte on the data bus is ignored) except the Memory Data Port. Access to the Memory Data Port is 16-bit. S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 17 Pin Mapping 5 Pin Mapping 5.1 Intel 80 Data Pins This function is controlled by CNF [1:0] Table 5-1: S1D13742B00 Intel 80 Data Pin Mapping Pin Name 8-Bit Data 8-Bit Data 16-Bit Data 16-Bit Data Swapped No Swap Swapped No Swap (CNF1=1, CNF0=1) (CNF1=1, CNF0=0) (CNF1=0, CNF0=1) (CNF1=0, CNF0=0) MD15 MD15 MD0 Pulled Low by Internal Resistor Pulled Low by Internal Resistor • • • • • • • • • • • • • • • MD8 MD8 MD7 Pulled Low by Internal Resistor Pulled Low by Internal Resistor MD7 MD7 MD8 MD7 MD0 • • • • • • • • • • • • • • • MD0 MD0 MD15 MD0 MD7 Table 5-2: S1D13742B01 Intel 80 Data Pin Mapping Pin Name 18 8-Bit Data 8-Bit Data 16-Bit Data 16-Bit Data Swapped No Swap Swapped No Swap (CNF1=1, CNF0=1) (CNF1=1, CNF0=0) (CNF1=0, CNF0=1) (CNF1=0, CNF0=0) MD15 MD15 MD0 Hi-Z Hi-Z • • • • • • • • • • • • • • • MD8 MD8 MD7 Hi-Z Hi-Z MD7 MD7 MD8 MD7 MD0 • • • • • • • • • • • • • • • MD0 MD0 MD15 MD0 MD7 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Pin Mapping 5.2 LCD Interface Pin Mapping Table 5-3: LCD Interface Pin Mapping for Mode 1 and Mode 2 Pin Name VS HS PCLK DE VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD16 VD17 VD18 VD19 VD20 VD21 VD22 VD23 VD24 VD25 VD26 VD27 VD28 VD29 VD30 VD31 VD32 VD33 VD34 VD35 16bpp 18bpp Single (18-bit) Double (36-bit) Single (18-bit) Double (36-bit) Normal Swap Normal Swap Normal Swap Normal Swap Vertical Sync Horizontal Sync Pixel Clock Data Enable B4 R4 B4 R4 B0 R5 B0 R5 B0 R3 B0 R3 B1 R4 B1 R4 B1 R2 B1 R2 B2 R3 B2 R3 B2 R1 B2 R1 B3 R2 B3 R2 B3 R0 B3 R0 B4 R1 B4 R1 B4 R4 B4 R4 B5 R0 B5 R0 G0 G5 G0 G5 G0 G5 G0 G5 G1 G4 G1 G4 G1 G4 G1 G4 G2 G3 G2 G3 G2 G3 G2 G3 G3 G2 G3 G2 G3 G2 G3 G2 G4 G1 G4 G1 G4 G1 G4 G1 G5 G0 G5 G0 G5 G0 G5 G0 R4 B4 R4 B4 R0 B5 R0 B5 R0 B3 R0 B3 R1 B4 R1 B4 R1 B2 R1 B2 R2 B3 R2 B3 R2 B1 R2 B1 R3 B2 R3 B2 R3 B0 R3 B0 R4 B1 R4 B1 R4 B4 R4 B4 R5 B0 R5 B0 driven 0 driven 0 B4 R4 driven 0 driven 0 B0 R5 driven 0 driven 0 B0 R3 driven 0 driven 0 B1 R4 driven 0 driven 0 B1 R2 driven 0 driven 0 B2 R3 driven 0 driven 0 B2 R1 driven 0 driven 0 B3 R2 driven 0 driven 0 B3 R0 driven 0 driven 0 B4 R1 driven 0 driven 0 B4 R4 driven 0 driven 0 B5 R0 driven 0 driven 0 G0 G5 driven 0 driven 0 G0 G5 driven 0 driven 0 G1 G4 driven 0 driven 0 G1 G4 driven 0 driven 0 G2 G3 driven 0 driven 0 G2 G3 driven 0 driven 0 G3 G2 driven 0 driven 0 G3 G2 driven 0 driven 0 G4 G1 driven 0 driven 0 G4 G1 driven 0 driven 0 G5 G0 driven 0 driven 0 G5 G0 driven 0 driven 0 R4 B4 driven 0 driven 0 R0 B5 driven 0 driven 0 R0 B3 driven 0 driven 0 R1 B4 driven 0 driven 0 R1 B2 driven 0 driven 0 R2 B3 driven 0 driven 0 R2 B1 driven 0 driven 0 R3 B2 driven 0 driven 0 R3 B0 driven 0 driven 0 R4 B1 driven 0 driven 0 R4 B4 driven 0 driven 0 R5 B0 S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 19 Pin Mapping 5.3 LCD Interface Data Pins This function is controlled by REG[14h] bit 7. Table 5-4: LCD Interface Data Pin Mapping 20 Pin Name 36-Bit Data No Swap REG[14] b7=0 36-Bit Data Swapped REG[14] b7=1 18-Bit Data No Swap REG[14] b7=0 18-Bit Data Swapped REG[14] b7=1 VD35 VD35 VD0 Driven Low Driven Low • • • • • • • • • • • • • • • VD18 VD18 VD17 Driven Low Driven Low VD17 VD17 VD18 VD17 VD0 • • • • • • • • • • • • • • • VD0 VD0 VD35 VD0 VD17 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 D.C. Characteristics 6 D.C. Characteristics 6.1 Absolute Maximum Ratings Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Core VDD Core Supply Voltage VSS - 0.3 ~ 2.0 V PLL VDD PLL Supply Voltage VSS - 0.3 ~ 2.0 V IO VDD Host IO Supply Voltage COREVDD ~ 4.0 V PIO VDD Panel IO Supply Voltage COREVDD ~ 4.0 V VIN Input Signal Voltage VSS - 0.3 ~ IOVDD + 0.3 V VOUT Output Signal Voltage VSS - 0.3 ~ IOVDD + 0.3 V IOUT Output Signal Current ±10 mA 6.2 Recommended Operating Conditions Table 6-2: Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Core VDD Core Supply Voltage VSS = 0 V 1.40 1.50 1.60 V PLL VDD PLL Supply Voltage VSS = 0 V 1.40 1.50 1.60 V IO VDD Host IO Supply Voltage VSS = 0 V 1.65 — 3.6 V PIO VDD Panel IO Supply Voltage VSS = 0 V 1.65 — 3.6 V VIN Input Voltage — VSS — IOVDD V TOPR Operating Temperature — -40 +25 +85 C Tstg Storage Temperature — -65 +150 C Note There are no special Power On/Off requirements with respect to sequencing the various VDD pins. There are also no special requirements for the IO signals, however Inputs should not be floating. If the input signals were to power up in a valid cycle, the S1D13742 would decode the cycle. S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 21 D.C. Characteristics 6.3 Electrical Characteristics The following characteristics are for: IOVDD. VSS = 0V, TOPR = -40 to +85C. Table 6-3: Electrical Characteristics for IOVDD or PIOVDD = 1.8V ± 0.15V Symbol Parameter Condition Min Typ Max Units CLKI stopped (grounded), Sleep Mode enabled, all power supplies active — 100 — A IQALL Quiescent Current IPLL PLL Current fPLL = 54MHz — 500 1000 A ICORE Operation Peak Current COREVDD Power Pin — — 62 mA PCORE Core Typical Operating Power — 9.15 — mW PPLL PLL Typical Operating Power — 0.7 — mW PPIO PIO Typical Operating Power — 2.8 — mW see Note 1 PHIO HIO Typical Operating Power — 0.018 — mW PCORE Core Typical Operating Power — 10.9 — mW PPLL PLL Typical Operating Power — 0.77 — mW PPIO PIO Typical Operating Power — 2.124 — mW see Note 2 PHIO HIO Typical Operating Power — 0.001 — mW IIZ Input Leakage Current — -5 — 5 A IOZ Output Leakage Current — -5 — 5 A IOVOH2 High Level Output Voltage IOVDD = min IOH2 = -2.5mA IOVDD - 0.40 — IOVDD V PIOVOH2 High Level Output Voltage PIOVDD = min IOH2 = -2.5mA PIOVDD - 0.40 — PIOVDD V PIOVOH4 High Level Output Voltage PIOVDD = min IOH2 = -6.5mA PIOVDD - 0.40 — PIOVDD V IOVOL2 Low Level Output Voltage IOVDD = min IOL2 = 2.5mA VSS — 0.40 V PIOVOL2 Low Level Output Voltage PIOVDD = min IOL2 = 2.5mA VSS — 0.40 V PIOVOL4 Low Level Output Voltage PIOVDD = min IOL2 = 6.5mA VSS — 0.40 V IOVIH High Level Input Voltage CMOS Input 1.27 — — V PIOVIH High Level Input Voltage CMOS Input 1.27 — — V IOVIL Low Level Input Voltage CMOS Input — — 0.57 V PIOVIL Low Level Input Voltage CMOS Input — — 0.57 V IOVT+ Positive Trigger Voltage CMOS Schmitt 0.57 — 1.56 V IOVT- Negative Trigger Voltage CMOS Schmitt 0.33 — 1.27 V IO VH Hysteresis Voltage CMOS Schmitt 0.24 — — V RPU1 Pull-Up Resistance Type1 VI = VSS 40 100 240 k RPD1 Pull-Down Resistance Type1 VI = VDD 40 100 240 k RPU2 Pull-Up Resistance Type2 VI = VSS 80 200 480 k RPD2 Pull-Down Resistance Type2 VI = VDD 80 200 480 k CIO Pin Capacitance f = 1MHz, VDD = 0V — — 8 pF Note 1. Typical Operating Current Environment: 352x416 K2 TFT panel with PCLK divide by 4. SYSCLK=48.5MHz from PLL, PLL Source from 19.2MHz CLKI input. 18bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 1.8V 2. Typical Operating Current Environment: 800 x 480 TFT panel with PCLK divide by 3. SYSCLK= 59MHz from PLL, PLL Source from 12MHz CLKI input. 16bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 1.8V 22 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 D.C. Characteristics The following characteristics are for: IOVDD. VSS = 0V, TOPR = -40 to +85C. Table 6-4: Electrical Characteristics for IOVDD or PIOVDD = 2.8V ± 0.14V Symbol Parameter Condition Min Typ Max Units — 120 — A IQALL Quiescent Current CLKI stopped (grounded), Sleep Mode enabled, all power supplies active IPLL PLL Current fPLL = 54MHz — 500 1000 A ICORE Operation Peak Current COREVDD Power Pin — — 62 mA IIZ Input Leakage Current — -5 — 5 A IOZ Output Leakage Current — -5 — 5 A IOVOH2 High Level Output Voltage IOVDD = min IOH2 = -3.6mA IOVDD - 0.40 — IOVDD V PIOVOH2 High Level Output Voltage PIOVDD = min IOH2 = -3.6mA PIOVDD 0.40 — PIOVDD V PIOVOH4 High Level Output Voltage PIOVDD = min IOH2 = -10.8mA PIOVDD 0.40 — PIOVDD V IOVOL2 Low Level Output Voltage IOVDD = min IOL2 = 3.6mA VSS — 0.40 V PIOVOL2 Low Level Output Voltage PIOVDD = min IOL2 = 3.6mA VSS — 0.40 V PIOVOL4 Low Level Output Voltage PIOVDD = min IOL2 = 10.8mA VSS — 0.40 V IOVIH High Level Input Voltage CMOS Input 1.75 — — V PIOVIH High Level Input Voltage CMOS Input 1.75 — — V IOVIL Low Level Input Voltage CMOS Input — — 0.70 V PIOVIL Low Level Input Voltage CMOS Input — — 0.70 V IOVT+ Positive Trigger Voltage CMOS Schmitt 0.93 — 2.36 V IOVT- Negative Trigger Voltage CMOS Schmitt 0.53 — 1.92 V IO VH Hysteresis Voltage CMOS Schmitt 0.40 — — V RPU1 Pull-Up Resistance Type1 VI = VSS 24 60 144 k RPD1 Pull-Down Resistance Type1 VI = VDD 24 60 144 k RPU2 Pull-Up Resistance Type2 VI = VSS 48 120 288 k RPD2 Pull-Down Resistance Type2 VI = VDD 48 120 288 k CIO Pin Capacitance — — 8 pF f = 1MHz, VDD = 0V Note 1. Typical Operating Current Environment: 352x416 K2 TFT panel with PCLK divide by 4. SYSCLK=48.5MHz from PLL, PLL Source from 19.2MHz CLKI input. 18bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 2.8V 2. Typical Operating Current Environment: 800 x 480 TFT panel with PCLK divide by 3. SYSCLK= 59MHz from PLL, PLL Source from 12MHz CLKI input. 16bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 2.8V S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 23 D.C. Characteristics The following characteristics are for: IOVDD, VSS = 0V, TOPR = -40 to +85C. Table 6-5: Electrical Characteristics for IOVDD or PIOVDD = 3.3V ± 0.3V Min Typ Max Units IQALL Symbol Quiescent Current Quiescent Conditions — 160 — A IPLL PLL Current fPLL = 54MHz — 500 1000 A ICORE Operation Peak Current COREVDD Power Pin — — 62 mA IIZ Input Leakage Current — -5 — 5 A IOZ Output Leakage Current — -5 — 5 A IOVOH2 High Level Output Voltage IOVDD = min IOH2 = -4.0mA IOVDD - 0.40 — IOVDD V PIOVOH2 High Level Output Voltage PIOVDD = min IOH2 = -4.0mA PIOVDD 0.40 — PIOVDD V PIOVOH4 High Level Output Voltage PIOVDD = min IOH2 = -12.0mA PIOVDD 0.40 — PIOVDD V IOVOL2 Low Level Output Voltage IOVDD = min IOL2 = 4.0mA VSS — 0.40 V PIOVOL2 Low Level Output Voltage PIOVDD = min IOL2 = 4.0mA VSS — 0.40 V PIOVOL4 Low Level Output Voltage PIOVDD = min IOL2 = 12.0mA VSS — 0.40 V IOVIH High Level Input Voltage CMOS Input 2.20 — — V PIOVIH High Level Input Voltage CMOS Input 2.20 — — V IOVIL Low Level Input Voltage CMOS Input — — 0.80 V PIOVIL Low Level Input Voltage CMOS Input — — 0.80 V IOVT+ Positive Trigger Voltage CMOS Schmitt 1.40 — 2.70 V IOVT- Negative Trigger Voltage CMOS Schmitt 0.60 — 1.80 V IO VH Hysteresis Voltage CMOS Schmitt 0.45 — — V RPU1 Pull-Up Resistance Type1 VI = VSS 20 50 120 k RPD1 Pull-Down Resistance Type1 VI = VDD 20 50 120 k RPU2 Pull-Up Resistance Type2 VI = VSS 40 100 240 k RPD2 Pull-Down Resistance Type2 VI = VDD 40 100 240 k CIO Pin Capacitance f = 1MHz, VDD = 0V — — 8 pF 24 Parameter Condition Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 A.C. Characteristics 7 A.C. Characteristics Conditions: IOVDD = PIOVDD = 1.8V ± 0.15V or 2.8V ± 0.14V TA = -40 C to 85 C Trise and Tfall for all inputs except Schmitt and CLKI must be < 50 ns (10% ~ 90%) Trise and Tfall for all Schmitt must be < 5 ms (10% ~ 90%) CL = 8pF ~ 30pF (MD[15:0]) CL = 15pF (TE, GPIO_INT, CLKOUT) CL = 30pF (LCD Panel/GPIO Interface) 7.1 Clock Timing 7.1.1 Input Clocks t1 CLKI t2 90% VIH VIL 10% t4 t3 tOSC t5 tOSC tOSC CLKI Figure 7-1 Clock Input Required (CLKI) S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 25 A.C. Characteristics Table 7-1 Clock Input Requirements (CLKI) Symbol Parameter Input clock frequency - PLL used for System Clock fOSC (see note 6) Input clock frequency - CLKI used for System Clock Input clock period tOSC t1 Input clock pulse width high t2 Input clock pulse width low t3 Input clock rise time (10% - 90%) t4 Input clock fall time (90% - 10%) t5 Input clock period jitter (see notes 2 and 4) t6 Input clock cycle jitter (see notes 3 and 4) (see note 1) Min 1 0 — 0.4tOSC 0.4tOSC — — -300 -300 Typ — — 1/fOSC — — — — Max 66 68.90 — 0.6tOSC 0.6tOSC 5.0 5.0 300 Units MHz MHz s s s ns ns ps 300 ps 1. t6 = 2*tOSC 2. The input clock period jitter is the displacement relative to the center period (reciprocal of the center frequency). 3. The input clock cycle jitter is the difference in period between adjacent cycles. 4. The jitter characteristics must satisfy both the t5 and t6 characteristics 5. Input Duty cycle is not critical and can be 40/60 6. The minimum System Clock frequency required for correct operation depends on the cycle length of the Intel 80 interface. See Section 8.4, “Setting SYSCLK and PCLK” on page 42 for more details. 7.1.2 PLL Clock The PLL circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The jitter of the input clock waveform should be as small as possible. 26 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 A.C. Characteristics PLL Enable 10 ms Lock In Time PLL Stable MHz Reference Clock PLL xxMHz Output (xx = 44.26~66.95MHz) Jitter (ns) Lock in time 10 ms Time (ms) The PLL frequency will ramp between the OFF state and the programmed frequency. To guarantee the lowest possible clock jitter, 10ms is required for stabilization. Note: PLL minimum frequency = 44.26MHz (Based on Intel 80 cycle length. Refer to Section 8.4 for more information) PLL maximum frequency = 66.95MHz Figure 7-2: PLL Start-Up Time Table 7-2: PLL Clock Requirements Symbol 1 Parameter fPLL PLL output clock frequency Min Max Units 44.261 66.95 MHz tPJref PLL output clock period jitter -3 3 % tPDuty PLL output clock duty cycle 40 60 % tPStal PLL output stable time  10 ms Refer to Section 8.4, “Setting SYSCLK and PCLK” on page 42. S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 27 A.C. Characteristics 7.2 RESET# Timing t1 RESET# tCLKI CLKI Figure 7-3 S1D13742 RESET# Timing Table 7-3 S1D13742 RESET# Timing Symbol t1 28 Parameter Active Reset Pulse Width Seiko Epson Corporation Min Max Units 1 — CLKI S1D13742 Hardware Functional Specification Rev. 6.6 A.C. Characteristics 7.3 Host interface Timing 7.3.1 Intel 80 Interface Timing - 1.8 Volt D/C# (Note 1) twcs twah tast tcsf tch CS# (Note 2) tcsf twl twh tch twc WE# tr2w tw2r tdst MD[15:0] write (Note 3) tdht trcs trah trc trl RD# trh trdd MD[15:0] read (Note 3) trdv trodh trrdz tcodh tcrdz Note 1: The D/C# input pin is used to distinguish between Address and Data. Note 2: The CS# pin can be kept low between write and read pulses as the register addresses will auto-increment. The register address will auto-increment in word increments for all register access except the Memory Data Port. Writes to the Memory Data Port will not increment the register address to support burst data writes to memory. Note 3: When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 29 A.C. Characteristics Table 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt Signal D/C# CS# Symbol Min Max Unit tast Address setup time (read/write) 1 — ns twah Address hold time (write) 5 — ns trah Address hold time (read) 29 — ns twcs Chip Select setup time (write) twl — ns trcs Chip Select setup time (read) trl — ns tch Chip Select hold time (read/write) 0 — ns tcsf Chip Select Wait time (read/write) 1 — ns Register Write cycle 12 — ns LUT write cycle 2SYSCLK + 1 — ns Memory write cycle 2SYSCLK + 1 — ns twl Pulse low duration 5 — ns twc WE# RD# Parameter Description twh Pulse high duration twc - twl — ns tw2r WR# rising edge to RD# falling edge 11 — ns Note 1 tr2w RD# rising edge to WR# falling edge 26 — ns Note 2 trc Read cycle trl + trh — ns trl Pulse low duration trdv — ns Pulse high duration for Registers 35 — ns trh 1SYSCLK + 26 — ns tdst Write data setup time 4 — ns tdht Write data hold time 5 — ns trodh Read data hold time from RD# rising edge 11 — ns trrdz RD# rising edge to MD Hi-Z — 31 ns tcodh Read data hold time from CS# rising edge 1 — ns tcrdz CS# rising edge to MD Hi-Z — 8 ns RD# falling edge to MD valid for Registers — 16 ns RD# falling edge to MD valid for LUT — 4SYSCLK + 26 ns RD# falling edge to MD valid for Memory — 5SYSCLK + 19 ns RD# falling edge to MD valid for Registers — 11 ns RD# falling edge to MD valid for LUT — 4SYSCLK + 21 ns RD# falling edge to MD valid for Memory — 5SYSCLK + 14 ns RD# falling edge to MD driven 4 — ns CL=30pF RD# falling edge to MD driven 3 — ns CL = 8pF MD[15:0] (Note 3) trdv trdd Pulse high duration for Memory and LUT CL=30pF CL = 8pF Note 1. For a read cycle after a write cycle, MD[15:0] must be driven Hi-Z a maximum of trdd after the falling edge of RD#. 2. For a write cycle after a read cycle, MD[15:0] should not be driven by the host until trrdz after the rising edge of RD#. 3. When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[7:0] are used for all accesses except for the Memory Data Port when MD[15:0] are used. 30 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 A.C. Characteristics 7.3.2 Intel 80 Interface Timing - 3.3 Volt D/C# (Note 1) twcs twah tast tcsf tch CS# (Note 2) tcsf twl twh tch twc WE# tr2w tw2r tdst MD[15:0] write (Note 3) tdht trcs trah trc trl RD# trh trdd MD[15:0] read (Note 3) trdv trodh trrdz tcodh tcrdz Note 1: The D/C# input pin is used to distinguish between Address and Data. Note 2: The CS# pin can be kept low between write and read pulses as the register addresses will auto-increment. The register address will auto-increment in word increments for all register access except the Memory Data Port. Writes to the Memory Data Port will not increment the register address to support burst data writes to memory. Note 3: When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 31 A.C. Characteristics Table 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt Signal D/C# CS# Symbol Min Max Unit tast Address setup time (read/write) 1 — ns twah Address hold time (write) 5 — ns trah Address hold time (read) 29 — ns twcs Chip Select setup time (write) twl — ns trcs Chip Select setup time (read) trl — ns tch Chip Select hold time (read/write) 0 — ns tcsf Chip Select Wait time (read/write) 1 — ns Register Write cycle 12 — ns LUT write cycle 2SYSCLK + 1 — ns Memory write cycle 2SYSCLK + 1 — ns twl Pulse low duration 5 — ns twc WE# RD# Parameter Description twh Pulse high duration twc - twl — ns tw2r WR# rising edge to RD# falling edge 16 — ns Note 1 tr2w RD# rising edge to WR# falling edge 26 — ns Note 2 trc Read cycle trl + trh — ns trl Pulse low duration trdv — ns Pulse high duration for Registers 36 — ns trh 1SYSCLK + 26 — ns tdst Write data setup time 4 — ns tdht Write data hold time 5 — ns trodh Read data hold time from RD# rising edge 11 — ns trrdz RD# rising edge to MD Hi-Z — 31 ns tcodh Read data hold time from CS# rising edge 1 — ns tcrdz CS# rising edge to MD Hi-Z — 8 ns RD# falling edge to MD valid for Registers — 11 ns RD# falling edge to MD valid for LUT — 4SYSCLK + 21 ns RD# falling edge to MD valid for Memory — 5SYSCLK + 14 ns RD# falling edge to MD valid for Registers — 9 ns RD# falling edge to MD valid for LUT — 4SYSCLK + 18 ns RD# falling edge to MD valid for Memory — 5SYSCLK + 11 ns RD# falling edge to MD driven 3 — ns CL=30pF RD# falling edge to MD driven 2 — ns CL = 8pF MD[15:0] (Note 3) trdv trdd Pulse high duration for Memory and LUT CL=30pF CL = 8pF Note 1. For a read cycle after a write cycle, MD[15:0] must be driven Hi-Z a maximum of trdd after the falling edge of RD#. 2. For a write cycle after a read cycle, MD[15:0] should not be driven by the host until trrdz after the rising edge of RD#. 3. When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[7:0] are used for all accesses except for the Memory Data Port when MD[15:0] are used. 32 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 A.C. Characteristics 7.3.3 Definition of Transition Time to Hi-Z State Due to the difficulty of Hi-Z impedance measurement for high speed signals, transition time from High/Low to Hi-Z specified as follows. • High to Hi-Z delay time: tpHZ, delay time when a gate voltage of final stage of the Pch-MOSFET turns to 0.8 x IOVDD (Pch-MOSFET is off). Total delay time to Hi-Z is calculated as follows: Internal logic delay + tpHZ (from High to Hi-Z) • Low to Hi-Z delay time: tpLZ, delay time when a gate voltage of final stage of the NchMOSFET turns to 0.2 x IOVDD (Nch-MOSFET is off). Total delay time to Hi-Z is calculated as follows: Internal logic delay + tpHZ (from High to Hi-Z) The functional model of a final stage of the Tri state Output Cell is shown in Figure 7-6: “Definition of transition time to Hi-Z state”. to measure tpHZ Tri state Output Cell P IOVDD EN X A VSS N to measure tpLZ Volt Volt IOVDD 0.8 IOVDD EN P ½IOVDD IOVDD 0.2 IOVDD tpHZ Time N EN ½IOVDD tpLZ Time Figure 7-6: Definition of Transition Time to Hi-Z State S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 33 A.C. Characteristics 7.4 Display Interface The timing parameters required to drive a flat panel display are shown below. Timing details for each supported panel type are provided in the remainder of this section. Note All timing measurements are taken to/from the ½PIOVDD level in the following Display Interface timing diagrams. HT TE HNDP DE HDISP DE TE HPS HSW VDISP VDISP HDISP VPS VNDP VSW Figure 7-7: Panel Timing Parameters Table 7-6: Panel Timing Parameter Definition and Register Summary Symbol Description Derived From HDISP Horizontal Display Width (REG[16h] bits 6-0) x 8 HNDP Horizontal Non-Display Period (REG[18h] bits 6-0) HPS HS Pulse Start Position REG[22h] bits 6-0 HSW HS Pulse Width (REG[20h] bits 6-0) VDISP Vertical Display Height (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0) VNDP Vertical Non-Display Period REG[1Eh] bits 7-0 VPS VS Pulse Start Position REG[26h] bits 7-0 VSW VS Pulse Width REG[24h] bits 6-0 Units Ts Lines (HT) Note TS = 1/PCLK 34 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 A.C. Characteristics 7.4.1 TFT Power-On Sequence t1 Power Save Mode Enable** (REG[56h] bits 1-0) LCD Signals*** **The LCD power-on sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit 0 to 0. ***LCD Signals include: VD[35:0], PCLK, HS, VS, and DE. Figure 7-8: TFT Power-On Sequence Timing Table 7-7: TFT Power-On Sequence Timing Symbol t1 Parameter Power Save Mode disabled to LCD signals active S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation Min Max Units 0 20 ns 35 A.C. Characteristics 7.4.2 TFT Power-Off Sequence Power Save Mode Enable** (REG[56h] bits 1-0) t1 LCD Signals*** **The LCD power-off sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit 0 to 1. ***LCD Signals include: VD[35:0], PCLK, HS, VS, and DE. Figure 7-9: TFT Power-Off Sequence Timing Table 7-8: TFT Power-Off Sequence Timing Symbol t1 36 Parameter Power Save Mode enabled to LCD signals low Seiko Epson Corporation Min Max Units 0 20 ns S1D13742 Hardware Functional Specification Rev. 6.6 A.C. Characteristics 7.4.3 18/36-Bit TFT Panel Timing t1 t2 VS t3 HS t17 t18 DE t4 HS t5 t8 t7 t6 DE t9 t12 t10 t11 t13 t14 t13 t14 PCLK REG[28h] b7=1 t9 t12 t10 t11 PCLK REG[28h] b7=0 t15 t16 invalid VD[17:0] 2 320 invalid 3-4 n+1 invalid 1 Note: 1 pixel/clock Mode invalid VD[35:0] 1-2 Note: 2 pixels/clock Mode Figure 7-10: 18/36-Bit TFT A.C. Timing Note HS, VS, PCLK all have Polarity Select bits via registers S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 37 A.C. Characteristics Table 7-9: 18/36-Bit TFT A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 1. Ts Parameter VS cycle time VS pulse width low VS falling edge to HS falling edge phase difference HS cycle time HS pulse width low HS Falling edge to DE active DE pulse width DE falling edge to HS falling edge PCLK period PCLK pulse width low PCLK pulse width high HS setup to PCLK active edge DE to PCLK rising edge setup time DE hold from PCLK active edge Data setup to PCLK active edge Data hold from PCLK active edge DE Stop setup to VS start Vertical Non-Display Period Min — — — — — — — — 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 — — Typ VDISP + VNDP VSW HPS HDISP + HNDP HSW HNDP-HPS HDISP HPS — — — — — — — — VPS VNDP Max — — — — — — — — — — — — — — — — — — Units Lines Lines Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts = pixel clock period Note In 36-bit mode, the data is always guaranteed to be launched on the correct edge of PCLK. In this mode, the frequency of PCLK is ½ the programmed internal value. If it is desired that HS and VS are always launched on the same edge of PCLK as the data, then HNDP, HSW, and HSS should be programmed with even values. 38 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Clocks 8 Clocks 8.1 Clock Descriptions Internal PLL Enable Clock Source Select (REG[12h] bit 0) Glitch Free PLL 1 MHz 0 SYSCLK CLKI External Clock Source Divider 1 2 3 Internal PCLK •• • 32 CLKOUTEN 2 PCLK Divide Select (REG[12h] bits 7-3) CLKOUT 1 0 External PCLK Panel Data Width Select (REG[14h] bit 0) Figure 8-1: S1D13742 Clock Block Diagram S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 39 Clocks 8.2 PLL Block Diagram REG[04h] VCP VC REG[0Ah] CP REG[08h] AMON CLKI M-Divider PLLCLK PFD VCO CP RS REG[0Ah] CS REG[0Ch] Loop Filter MUX TCK REG[08h] REG[0Eh] V-Divider L-Counter N-Counter MUX Where: PFD = Phase Frequency Detector CP = Charge Pump VCO = Voltage Controlled Oscillator Loop Filter = Low Pass Filter TEST Control = Internal Control Logic SYSCLK REFCK MUX 1/32 TOUT Figure 8-2: PLL Block Diagram 40 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Clocks 8.3 Clocks versus Functions This table lists the internal clocks required for the following S1D13742 functions. Internal Clock Requirements Function Internal SYSCLK Internal PCLK Register Read/Write No No Memory Read/Write Yes No Look-Up Table Register Read/Write Yes No Power Save No No LCD Output Yes Yes Note Register access does not require an internal clock as the S1D13742 creates a clock from the bus cycle alone. S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 41 Clocks 8.4 Setting SYSCLK and PCLK The period of the system clock, TSYSCLK, must be set such that it falls within the following range: For PLL: For CLKI: 14.94ns < TSYSCLK < (TBBC - 0.914) x 0.485 ns 14.50ns < TSYSCLK < (TBBC - 0.914) x 0.5ns where TBBC is the minimum back-to-back cycle time of the Intel 80 Interface. For example, if the minimum back-to-back cycle time of the Intel 80 Interface is 5 x 9.5 = 47.5ns, then: For PLL: For CLKI: 14.94ns < TSYSCLK < 22.594ns 14.50ns < TSYSCLK < 23.293ns Therefore, For PLL: For CLKI: 44.26MHz < fSYSCLK < 66.95MHz 42.94MHz < fSYSCLK < 68.96MHz SYSCLK Frequency (MHz) Care should be taken when setting TSYSCLK so that the desired PCLK frequency, fPCLK, can be achieved. PCLK is an integer divided version of SYSCLK. The following graph shows the suggested setting for SYSCLK for a given value of PCLK for TBBC = 47.5ns. 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 SysClk/3 SysClk/4 SysClk/5 SysClk/6 SysClk/7 SysClk/2 6 8 10 12 14 16 18 20 22 24 26 PCLK Frequency (MHz) Figure 8-3: Setting of SYSCLK For a Desired PCLK 42 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Registers 9 Registers This section discusses how and where to access the S1D13742 registers. It also provides detailed information about the layout and usage of each register. Burst data writes to the register space is supported. This applies to all register write access except the Memory Data Port (REG[48h - 49h]) and the Gamma Correction Table Data Register [REG[54h]). All writes to these two registers will auto-increment the internal memory address only. 9.1 Register Mapping All registers and memory are accessed via the Intel 80 interface. All access is 8-bit only except for the Memory Data Port (REG[48h - 49h]) which is accessed as 16-bit (if CNF1=1) or 8-bit (if CNF1=0). S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 43 Registers 9.2 Register Set The S1D13742 registers are listed in the following table. Table 9-1: S1D13742 Register Set Register Pg Read-Only Configuration Registers REG[00h] Revision Code Register 45 Register REG[02h] Configuration Readback Register Pg 45 Clock Configuration Registers REG[04h] PLL M-Divider Register 46 REG[06h] PLL Setting Register 0 47 REG[08h] PLL Setting Register 1 47 REG[0Ah] PLL Setting Register 2 47 REG[0Ch] PLL Setting Register 3 48 REG[0Eh] PLL Setting Register 4 48 REG[10h] 48 REG[12h] Clock Source Select Register 49 Panel Configuration Registers REG[14h] Panel Type Register 51 REG[16h] Horizontal Display Width Register (HDISP) 51 REG[18h] Horizontal Non-Display Period Register (HNDP) 51 REG[1Ah] Vertical Display Height Register 0 (VDISP) 52 REG[1Ch] Vertical Display Height Register 1 (VDISP) 52 REG[1Eh] Vertical Non-Display Period Register (VNDP) 52 REG[20h] HS Pulse Width Register (HSW) 52 REG[22h] HS Pulse Start Position Register 0 (HPS) 53 REG[24h] VS Pulse Width Register (VSW) 53 REG[26h] VS Pulse Start Position Register 0 (VPS) 53 REG[28h] PCLK Polarity Register 53 Input Mode Register REG[2Ah] Input Mode Register 54 REG[2Ch] Input YUV/RGB Translate Mode Register 0 56 REG[2Eh] YUV/RGB Translate Mode Register 1 56 REG[30h] U Data Fix Register 58 REG[32h] V Data Fix Register 58 Display Mode Registers REG[34h] Display Mode Register 59 REG[36h] Special Effects Register 60 Window Settings REG[38h] Window X Start Position Register 0 63 REG[3Ah] Window X Start Position Register 1 REG[3Ch] Window Y Start Position Register 0 63 REG[3Eh] Window Y Start Position Register 1 63 REG[40h] Window X End Position Register 0 64 REG[42h] Window X End Position Register 1 64 64 REG[46h] Window Y End Position Register 1 64 REG[44h] Window Y End Position Register 0 63 Memory Access REG[48h] Memory Data Port Register 0 65 REG[49h] Memory Data Port Register 1 65 REG[4Ah] Memory Read Address Register 0 66 REG[4Ch] Memory Read Address Register 1 66 REG[4Eh] Memory Read Address Register 2 66 Gamma Correction Registers REG[50h] Gamma Correction Enable Register 67 REG[54h] Gamma Correction Table Data Register 68 REG[52h] Gamma Correction Table Index Register 68 Miscellaneous Registers REG[56h] Power Save Register 69 REG[58h] Non-Display Period Control / Status Register 69 General Purpose IO Pins Registers REG[5Ah] General Purpose IO Pins Configuration Register 0 71 REG[5Ch] General Purpose IO Pins Status/Control Register 0 71 REG[5Eh] GPIO Positive Edge Interrupt Trigger Register 71 REG[60h] GPIO Negative Edge Interrupt Trigger Register 72 REG[62h] GPIO Interrupt Status Register 72 REG[64h] GPIO Pull Down Control Register 0 72 44 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Registers 9.3 Register Descriptions All reserved bits must be set to the default value. Writing a non-default value to a reserved bit may produce undefined results. Bits marked as n/a have no hardware effect. Unless specified otherwise, all register bits are set to 0 during power-on reset. 9.3.1 Read-Only Configuration Registers REG[00h] Revision Code Register Default = 80h for S1D13742B00 or 81h for S1D13742B01 Read Only Product Code bits 5-0 7 6 5 4 Revision Code bits 1-0 3 2 1 0 bits 7-2 Product Code bits [5:0] These are read-only bits that indicates the product code. The product code is 100000b. bits 1-0 Revision Code bits [1:0] These are read-only bits that indicates the revision code. The revision code for the S1D13742B00 is 00b, and for the S1D13742B01 is 01b. REG[02h] Configuration Readback Register Default = xxh Read Only n/a 7 bits 2-0 6 5 4 3 CNF2 Status CNF1 Status CNF0 Status 2 1 0 CNF[2:0] Status These read-only status bits return the status of the configuration pins CNF[2:0]. S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 45 Registers 9.3.2 Clock Configuration Registers REG[04h] PLL M-Divider Register Default = 00h PLL Lock Bit (RO) n/a 7 6 Read/Write M-Divider bits 5-0 5 4 3 2 1 0 bit 7 PLL Lock Bit (read only) When this bit = 0, the PLL output is not stable. In this state R/W access to the display buffer is prohibited. When this bit = 1, the PLL output is stable. bits 5-0 M-Divider bits [5:0] These bits determine the divide ratio between CLKI and the actual input clock to the PLL Note The internal input clock to the PLL (PLLCLK) must be between 1 MHz and 2 MHz. Depending on CLKI, these bits will have to be set accordingly. Note Values higher then 20h are not allowed. Table 9-2: PLL M-Divide Selection 46 REG[04h] bits 5-0 M-Divide Ratio 0h 1:1 01h 2:1 02h 3:1 03h 4:1 • • • • • • 20h 33:1 21h to 3Fh Reserved Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Registers REG[06h] PLL Setting Register 0 Default = 00h Read/Write PLL Setting Register 0 bits 7-0 7 6 5 4 3 2 1 0 This register must be programmed with the value F8h. REG[08h] PLL Setting Register 1 Default = 00h Read/Write PLL Setting Register 1 bits 7-0 7 6 5 4 3 2 1 0 This register must be programmed with the value 80h. REG[0Ah] PLL Setting Register 2 Default = 00h Read/Write PLL Setting Register 2 bits 7-0 7 6 5 4 3 2 1 0 This register must be programmed with the value 28h. S1D13742 Hardware Functional Specification Rev. 6.6 Seiko Epson Corporation 47 Registers REG[0Ch] PLL Setting Register 3 Default = 00h Read/Write PLL Setting Register 3 bits 7-0 7 6 5 4 3 2 1 0 This register must be programmed with the value 00h. REG[0Eh] PLL Setting Register 4 Default = 00h Read/Write n/a L-Counter bits 6-0 7 6 bits 6-0 5 4 3 2 1 0 L-Counter bits [6:0] These bits are used to configure the PLL Output (in MHz) and must be set according to the following formula. PLL Output = (L-Counter +1) x PLLCLK = LL x PLLCLK Where: PLL Output is the desired PLL output frequency (in MHz). L-Counter is the value of this register (in decimal). PLLCLK is the internal input clock to the PLL (in MHz). Please refer to Section 8.4, “Setting SYSCLK and PCLK” on page 42 for restrictions on PLL Output frequencies. Table 9-3 PLL Setting Example Target Frequency (MHz) LL CLKI Input Clock (MHz) M-Divider REG[04] bits 5-0 M-Divide Ratio PLLCLK (MHz) POUT (MHz) 53 53 12 0Bh 12:1 1.0 53 60 60 12 0Bh 12:1 1.0 60 • • • • • • • 53 53 19.2 12h 19:1 1.0105 53.53 60 60 19.2 12h 19:1 1.0105 60.63 REG[10h] Default = 00h Read/Write n/a 7 6 5 4 3 2 1 0 Writes to this register have no effect on hardware. During Auto Increment, a dummy write needs to be performed to this register. 48 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Registers REG[12h] Clock Source Select Register Default = 00h Read/Write PCLK Divide Select bits 4-0 7 bits 7-3 6 5 SYSCLK Source Select n/a 4 3 2 1 0 PCLK Divide Select bits [5:0] These bits specify the divide ratio for the panel clock (PCLK). The clock source for PCLK is SYSCLK. All resulting clock frequencies will maintain a 50/50 duty cycle regardless of divide ratio. Table 9-4 PCLK Divide Ratio Selection REG[0012h] bits 7-3 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h • • • 1Fh S1D13742 Hardware Functional Specification Rev. 6.6 PCLK Divide Ratio Reserved 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10:1 11:1 12:1 13:1 14:1 15:1 16:1 17:1 18:1 • • • 32:1 Seiko Epson Corporation 49 Registers bit 0 SYSCLK Source Select This bit selects the system clock (SYSCLK) source for the controller. When this bit = 0, the SYSCLK source is the external CLKI input. When this bit = 1, the SYSCLK source is the internal PLL. If the PLL is selected as the SYSCLK source (bit 0 = 1), the PLL must be configured using REG[06h], REG[08h], REG[0Ah], REG[0Ch], REG[0Eh] and REG[10h] before setting this bit. Note To use PLL as system clock source (SYSCLK), Sleep Mode needs to be first enabled, REG[56h] bit 1 = 1. Once in Sleep Mode, REG[04h] and REG[0Eh] can be changed to set the desired PLL frequency. Once REG[04h] and REG[0Eh] have been set, REG[12h] bit 0 can be set to 1b to select PLL as the system clock source. The PLL output will only be active after exiting the Sleep Mode (REG[56h] bit 1 = 0). The PLL output will become stable after 10msec. The display memory or the Gamma Correction Table must not be accessed before this time. REG[04h] bit 7, the PLL Lock Bit, can be used to determine if the PLL output is stable. 50 Seiko Epson Corporation S1D13742 Hardware Functional Specification Rev. 6.6 Registers 9.3.3 Panel Configuration Registers REG[14h] Panel Type Register Default = 00h Read/Write VD Data Swap 7 n/a 6 bit 7 5 4 Panel Data Width 3 2 1 0 VD Data Swap When this bit = 0, data lines are normal (i.e.: output pin VD35 = VD35, etc.) When this bit = 1, data lines are swapped (i.e.: output pin VD35 = VD0, etc.) Note The Data swap will always go from the msb to the lsb on the active output pins. See “LCD Interface Data Pins” on page 20. bit 0 Panel Data Width When this bit = 0, the LCD interface is configured as 18-bit. When this bit = 1, the LCD interface is configured as 36-bit. REG[16h] Horizontal Display Width Register (HDISP) Default = 01h n/a 7 Read/Write Horizontal Display Period bits 6-0 6 bits 6-0 5 4 3 2 1 0 Horizontal Display Width bits [6:0] These bits specify the LCD panel Horizontal Display Width (HDISP), in 8 pixel resolution. Horizontal Display Width in number of pixels = ((REG[16h] bits 6-0)  8 Note Minimum value of 8 pixels (register programmed to 1). REG[18h] Horizontal Non-Display Period Register (HNDP) Default = 00h n/a 7 bits 6-0 Read/Write Horizontal Non-Display Period bits 6-0 6 5 4 3 2 1 0 Horizontal Non-Display Period bits [6:0] These bits specify the horizontal non-display period in pixels. For 36-bit wide panels, there are 2 pixels per external PCLK. HNDP is calculated using the following formula. HNDP = (REG[18h] bits 6-0) Note The minimum Horizontal Non-Display Period is 3 Pixels (REG[18h] bits 6-0 = 03h). HS Start + HS Width