S1F75510M0A010B

PF1233-01 S1F75510 S1F75510 y ar n i m Charge-pump DC/DC Converter & Voltage Regulator i l e r P ■ DESCRIPTION The S1F75510 is a power IC designed for use with medium or small capacity TFT–LCD panel modules. A single chip of this IC is capable of generating three different levels of positive and negative output voltages simultaneously, which are necessary to drive the LCD, by use of a single input power of +2.7 through +3.6V. Since the S1F75510 does not require external transistors nor diodes as its voltage conversion circuit, its builtin CMOS transistors constituting a complete charge pump type DC/DC converter, it is most suitable for the purpose of reducing the current consumption levels of the LCD modules. Moreover, the charge pump type DC/DC converter of the S1F75510 can be operated upon the frequencies, which are to be switched over by the mode changing signals, using either of the built-in clock signals or external clock signals optimal to respective cases. This function can drastically suppress the current consumption of this IC while under light load state, thus exhibiting very high power conversion efficiencies. ■ FEATURES ● Supply voltage ································································ 2.7V to 3.6V single power input ● Self consumption current (normal mode/blank mode) ···· 300µA / 30µA (TBD) Normal mode: Boosting by use of the internal clock Blank mode: Selectable between boosting by use of the internal clock or by use of the external clock. ● Conversion efficiency of the charge pump ······················ 90% or more respectively ● Built-in voltage conversion circuits constituted by charge pump type DC/DC converter, • ✕2 boosting circuit in the positive direction • ✕3 boosting circuit in the positive direction • ✕3 boosting circuit in the negative direction ● Built-in voltage stabilizing circuit ● Capable of outputting the positive supply voltage VOUT2 for the source driver • ✕2 boosting circuit in the positive direction + voltage stabilizing circuit Output voltage: +5.0V ±3% (TBD) ● Capable of outputting the positive supply voltage VOUT3 for the gate driver • ✕3 boosting circuit in the positive direction Output voltage: +15V V OUT3 = V OUT2 ✕ 3 ● Capable of outputting the negative supply voltage VOUT4 for the gate driver • ✕3 boosting circuit in the negative direction Output voltage: –10V V OUT4 = V OUT2 ✕ –2 ● Built-in electric charge discharging circuit ● Built-in shut down function ● Shipping state ································································· SSOP3–24pin ● This IC is not of the radiation resistant design nor of the light resistance design. Rev. 1.0 1 S1F75510 ■ BLOCK DIAGRAM VDD VSS POFFX (8) Discharging circuit OSC1 ROSC OSC2 C1P (4) ×2 boosting circuit in the positive direction + C1 C1N C2P + C2 C2N (1) CR oscillation circuit CVOUT1 + VOUT1 CL MODE (2) Mode changeover circuit (5) Voltage stabilizing circuit CVOUT2 + VOUT2 OSCSEL C3P + C3 C3N (3) Timing signal forming circuit (6) ×3 boosting circuit in the positive direction C4P + C4 C4N + VOUT3 CVOUT3 C5P (7) ×3 boosting circuit in the negative direction + C5 C5N C6P + C6N C6 + VOUT4 CVOUT4 Fig. 1 Block diagram 2 Rev. 1.0 S1F75510 ■ DESCRIPTIONS FOR THE BLOCK DIAGRAM (1) CR oscillation circuit The oscillation circuit is constituted by connecting a resistor between the OSC1 pin and the OSC2 pin. The clock signals being generated by this oscillation circuit will become effective as boosting clock signals while the mode changeover signal MODE is on the VDD level (normal mode) or while the mode changeover signal MODE is on the VSS level and, at the same time, when the internal/external clock selection signal OSCSEL is on the VDD level (blank mode · internal clock). When the MODE is set to the VSS level and, at the same time, when the OSCSEL is set to the VSS level (blank mode · external clock), the oscillation will be interrupted. (2) Mode changeover circuit The operation modes of the boosting circuit and voltage stabilizing circuit are being switched over by the mode changeover signal MODE. Also, it selects the clock signals to feed to the timing signal forming circuit from either of the external clock signals or internal clock signals. (3) Timing signal forming circuit This circuit generates the charge pump boosting clock signals. This circuit outputs timing signals of the clock type (internal clock or external clock) having been selected by the mode changeover circuit to drive respective boosting circuits. When the shut down signal POFFX is set to the VSS level, the timing signal stops to interrupt the boosting operation. (4) ✕2 boosting circuit in the positive direction This circuit makes ✕2 boosting in the positive direction by charge pump boosting upon the inputted supply voltage VDD – VSS using the VSS potential as the reference voltage. The ✕2 boosted output will enter into the voltage stabilizing circuit. (5) Voltage stabilizing circuit This circuit generates the positive supply voltage VOUT2 for the source driver. ON the basis of the built-in reference, this circuit stabilizes the output from the above "(4) ✕2 boosting circuit in the positive direction" by use of the series regulator. (6) ✕3 boosting circuit in the positive direction This circuit generates the positive supply voltage VOUT3 for the gate driver. This circuit effects ✕3 boosting in the positive direction by charge pump boosting upon the voltage VOUT2 – V SS using the VSS potential as the reference voltage. (7) ✕3 boosting circuit in the negative direction This circuit generates the negative supply voltage VOUT4 for the gate driver. This circuit effects ✕3 boosting in the negative direction by charge pump boosting upon the voltage VOUT2 – VSS using the VOUT2 potential as the reference voltage. (8) Electric charge discharging circuit This circuit discharges the electric charge remaining in the VOUT3 pin and VOUT4 pin to the VSS level. This circuit will work when the POFFX pin is set to the VSS level. Rev. 1.0 3 S1F75510 ■ PIN ASSIGNMENT SSOP3–24pin S1F75510M0A0 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 4 24 13 1 12 Pin name C3N C3P C4P C4N VOUT3 VDD C1N C1P VOUT1 C2P C2N V SS Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 Pin name MODE CL POFFX OSC1 OSC2 OSCSEL VOUT2 VOUT4 C6P C6N C5N C5P Rev. 1.0 S1F75510 ■ PIN DESCRIPTION (1) CR oscillation circuit · Mode changeover circuit · Timing signal forming circuit · Electric charge discharging circuit Pin name POFFX I/O I Pin No. 15 OSC1 I 16 OSC2 O 17 CL I 14 MODE OSCSEL I I 13 18 Function This is the shut down pin. Set it to the VDD level while the IC is in operation. When this signal is set to the VSS level, operations of all the circuits will be interrupted bringing the IC into the shut down state. The electric charge discharging circuit discharges the electric charge remaining in the VOUT3 pin and VOUT4 pin to the VSS level. This is the CR oscillation circuit gate input pin. This is the pin to connect the oscillation resistor. Fix it to the VSS level in case the built-in oscillation circuit will not be used. This is the CR oscillation circuit drain input pin. Connect the oscillation resistor between this pin and the OSC1 pin. This is the boosting external clock signal input pin. Input the charge pump clock signals under the blank mode into this pin. This is the mode changeover pin. This is the pin for selection between the internal clock and external clock signals. MODE OSCSEL Function HIGH(VDD) HIGH(VDD) Normal mode LOW(VSS) The boosting clock signals are being generated through the internal oscillation. The built-in oscillation circuit will operate and the voltage stabilizing circuit will operate. LOW(VSS ) HIGH(VDD) Blank mode (internal oscillation) The boosting clock signals are being generated through the internal oscillation. The built-in oscillation circuit will operate and the voltage stabilizing circuit will operate under low current consumption state. LOW(VSS) Blank mode (external oscillation) The boosting clock signals are being generated by the external clock. The built-in oscillation circuit will be interrupted and the voltage stabilizing circuit will operate under low current consumption state. Rev. 1.0 5 S1F75510 (2) ✕2 boosting circuit in the positive direction Pin name VOUT1 I/O O Pin No. 9 C1P (O) 8 C1N (O) 7 C2P (O) 10 C2N (O) 11 Function This is the output pin of the ✕2 boosting circuit in the positive direction. This is the pin to connect the positive side of the VOUT1 output voltage generating flying capacitor C1. This is the pin to connect the negative side of the VOUT1 output voltage generating flying capacitor C1. This is the pin to connect the positive side of the VOUT1 output voltage generating flying capacitor C2. This is the pin to connect the negative side of the VOUT1 output voltage generating flying capacitor C2. (3) Voltage stabilizing circuit Pin name V OUT1 V OUT2 I/O I O Pin No. 9 19 Function This is the input power pin (+) for the voltage stabilizing circuit. This pin is being connected to the output pin of the ✕2 boosting circuit in the positive direction internally, inside this IC. This is the output pin of the voltage stabilizing circuit. (4) ✕3 boosting circuit in the positive direction Pin name VOUT3 I/O O Pin No. 5 C3P (O) 2 C3N (O) 1 C4P (O) 3 C4N (O) 4 6 Function This is the output pin of the ✕3 boosting circuit in the positive direction. This is the pin to connect the positive side of the VOUT3 output voltage generating flying capacitor C3. This is the pin to connect the negative side of the VOUT3 output voltage generating flying capacitor C3. This is the pin to connect the positive side of the VOUT3 output voltage generating flying capacitor C4. This is the pin to connect the negative side of the VOUT3 output voltage generating flying capacitor C4. Rev. 1.0 S1F75510 (5) ✕3 boosting circuit in the negative direction Pin name V OUT4 I/O O Pin No. 20 C5P (O) 24 C5N (O) 23 C6P (O) 21 C6N (O) 22 I/O I I Pin No. 6 12 Function This is the output pin of the ✕3 boosting circuit in the negative direction. This is the pin to connect the positive side of the VOUT4 output voltage generating flying capacitor C5. This is the pin to connect the negative side of the VOUT4 output voltage generating flying capacitor C5. This is the pin to connect the positive side of the VOUT4 output voltage generating flying capacitor C6. This is the pin to connect the negative side of the VOUT4 output voltage generating flying capacitor C6. (6) Power pins Pin name VDD VSS Rev. 1.0 Function This is the input power pin (+). This is the input power pin (–). 7 S1F75510 ■ FUNCTIONAL DESCRIPTION ● Operational description Generating voltage levels are: · Positive boosting supply voltage necessary for the voltage stabilizing circuit (VOUT1) · Positive stabilized supply voltage necessary for the source driver (VOUT2) · Positive and negative boosting supply voltages necessary for the gate driver (VOUT3 and VOUT4) The VOUT1 supply voltage is being generated by the charge pump type DC/DC converter (✕2 boosting circuit in the positive direction). It makes ✕2 boosting in the positive direction of the potential difference occurring between the VDD – VSS using the VSS potential as the reference voltage. The VOUT2 supply voltages is being generated by the series regulator stabilizing the potential difference occurring between the VOUT1 – VSS using the VSS potential as the reference voltage. The VOUT3 supply voltage is being generated by the charge pump type DC/DC converter (✕3 boosting circuit in the positive direction). It makes ✕3 boosting in the positive direction of the potential difference occurring between the VOUT2 – VSS using the VSS potential as the reference voltage. The VOUT4 supply voltage is being generated by the charge pump type DC/DC converter (✕3 boosting circuit in the negative direction). It makes ✕3 boosting in the negative direction of the potential difference occurring between the VOUT2 – VSS using the VOUT2 potential as the reference voltage. Indicated below is the system configuration diagram for the power circuit. Gate driver LCD panel VOUT3, VOUT4 VDD S1F75510 VOUT2 Source driver VSS Fig. 2 System configuration diagram 8 Rev. 1.0 S1F75510 Indicated below is the potential correlation diagram inside the system as is shown in Fig. 2. ×3 boosting in the positive direction ×2 boosting in the positive direction VOUT3 VOUT1 VOUT2 Voltage stabilizing VDD Source driver Gate driver VSS VOUT4 ×3 boosting in the negative direction Power Supply IC (S1F75510) Fig. 3 Potential correlation diagram inside the system ● CR oscillation circuit The S1F75510 incorporates a CR oscillation circuit as the oscillation circuit for the boosting clock signals. This circuit is to be used connecting the external oscillation resistor ROSC between the OSC1 pin and the OSC2 pin. The CR oscillation circuit will stop operation under the blank mode and when using the external clock (MODE = VSS level and OSCSEL = VSS level) or under the shut down state (POFFX = VSS level). Also, the oscillation will be interrupted by setting the OSC1 pin to the VSS level and, at the same time, setting the OSC2 pin into open state. As the external oscillation resistance, we recommend use of ROSC = 1 MΩ. Rev. 1.0 9 S1F75510 ● Mode changeover circuit By external settings of the mode changeover signal MODE and the internal/external clock selection signal OSCSEL, the charge pump boosting can be driven under optimum frequencies. Since the current consumption of the IC can be suppressed drastically under the blank mode, it is possible to achieve high power conversion efficiency even under light load operations. MODE pin OSCSEL pin HIGH(VDD) HIGH(VDD) LOW(VSS ) HIGH(VDD) Mode name Normal mode Blank mode LOW(VSS) LOW(VSS ) Blank mode Max. output current VOUT2:(10mA) (TBD) VOUT3:(100µA) (TBD) VOUT4:(100µA) (TBD) VOUT2:(200µA) (TBD) VOUT3:(10µA) (TBD) VOUT4:(10µA) (TBD) VOUT2:(200µA) (TBD) VOUT3:(10µA) (TBD) VOUT4:(10µA) (TBD) Built-in CR Built in voltage oscillation circuit stabilizing circuit In operation In normal operation In operation In standstill In low current consumption operation In low current consumption operation ● Timing signal forming circuit This circuit generates the clock signals necessary for charge pump boosting using the internal oscillation or using external clock signals. Two different types of capacitors are being used as the charge pump capacitors, one being the flying capacitor which shifts between the charging state and the discharging state and the other being the smoothing capacitor which preserves the electric charge. The operating frequency of the flying capacitor should equal to the frequency of the charge pump clock being generated by this timing signal forming circuit. Under the shut down state (POFFX = VSS level), the charge pump clock stops operation and all the boosting operations of this IC will be interrupted. The operating frequencies of the flying capacitor are as follows. MODE pin HIGH(VDD) OSCSEL pin HIGH(VDD) LOW(VSS) HIGH(VDD) LOW(VSS ) Mode name Normal mode Blank mode Blank mode LOW(VSS) CL=(TBD) Hz (Min.300 Hz) 10 Operating frequencies of the flying capacitor ✕2 boosting in ✕3 boosting in ✕3 boosting in the positive direction the positive direction the negative direction (TBD) kHz (TBD) kHz (TBD) kHz (Typ.10 kHz) (Typ.10 kHz) (Typ.10 kHz) (TBD) kHz (TBD) kHz (TBD) kHz (Typ.625 Hz) (Typ.625 Hz) (Typ.625 Hz) (TBD) Hz (Min.150 Hz) (TBD) Hz (Min.150 Hz) (TBD) Hz (Min.150 Hz) Rev. 1.0 S1F75510 ● ✕2 boosting circuit in the positive direction The ✕2 boosting circuit in the positive direction generates the voltages necessary to input into the voltage stabilizing circuit. It makes ✕2 boosting in the positive direction of the potential difference occurring between the VDD – VSS using the VSS potential as the reference voltage to output through the VOUT1 pin. Under the blank mode, since the boosting operation is being carried out with the flying capacitor C2 stopping its operation, the current consumption can be suppressed accordingly. The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT1 becomes as follows: VOUT1 = (VDD – VSS) ✕ 2 Actually, when a load is connected to the VOUT1, the output voltage will drop to the value represented by the equation indicated below. VOUT1 = (VDD – VSS) ✕ 2 – RVOUT1 ✕ IVOUT1 RVOUT1 : Output impedance of the x2 boosting circuit in the positive direction IVOUT1 : Load current ● Voltage stabilizing circuit The voltage stabilizing circuit stabilizes the voltage being output through the VOUT1 pin by the series regulator to output the positive supply voltage for the source driver through the VOUT2 pin. The output voltage setting for the VOUT2 pin should be Typ. +5.0V (TBD). Since it is necessary to let the VOUT1 satisfy the correlation of "VOUT1 > VOUT2 + 0.1V" in order to obtain normal output voltage value through the VOUT2 pin, use the IC within the range of the max. load current (7.3). The circuit configuration · connection diagram for the voltage stabilizing circuit is as follows: [Internal structure of the S1F75510] CVOUT1 + VOUT1 ×2 boosting circuit in the positive direction VOUT1 = (VDD–VSS) × 2 + To the source driver VOUT2 – Voltage stabilizing circuit + CVOUT2 Reference voltage circuit VDD VSS ×3 boosting circuit in the positive direction ×3 boosting circuit in the negative direction Fig. 4 Configuration diagram of the voltage stabilizing circuit Rev. 1.0 11 S1F75510 ● ✕3 boosting circuit in the positive direction The ✕3 boosting circuit in the positive direction generates the VOUT3 output voltage, means the positive supply voltage for the gate driver. It makes ✕3 boosting in the positive direction of the potential difference occurring between the VOUT2 – VSS using the VSS potential as the reference voltage, by charge pump boosting, to output through the VOUT3 pin. The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT3 becomes as follows: VOUT3 = (VOUT2 – VSS) ✕ 3 Actually, when a load is connected to the VOUT3, the output voltage will drop to the value represented by the equation indicated below. VOUT3 = (VOUT2 – VSS) ✕ 3 – (RVOUT3 ✕ IVOUT3) RVOUT3 : Output impedance of the ✕3 boosting circuit in the positive direction IVOUT3 : Load current It means that the VOUT3 voltage will drop by the load. To acquire desired output voltage, use the IC within the range of the specified load (7.3). ● ✕3 boosting circuit in the negative direction The ✕3 boosting circuit in the negative direction generates the V OUT3 output voltage, means the negative supply voltage for the gate driver. It makes ✕3 boosting in the negative direction of the potential difference occurring between the VOUT2 – V SS using the VOUT2 potential as the reference voltage, by charge pump boosting, to output through the VOUT4 pin. The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT4 becomes as follows: VOUT4 = (VOUT2 – VSS) ✕ (–2) (The voltage value using the VSS potential as the reference voltage) Actually, when a load is connected to the VOUT4, the output voltage will drop to the value represented by the equation indicated below. VOUT4 = (VOUT2 – VSS) ✕ (–2) – (RVOUT4 ✕ IVOUT4) RVOUT4 : Output impedance of the ✕3 boosting circuit in the negative direction IVOUT4 : Load current It means that the VOUT4 voltage will drop by the load. To acquire desired output voltage, use the IC within the range of the specified load (7.3). ● Electric charge discharging circuit The electric charge discharging circuit discharges the electric charge remaining in the VOUT3 pin and VOUT4 pin to the VSS level. This circuit starts operation when the POFFX pin is set to the VSS level. The discharging sequence and the discharging impedance are according to the (TBD). 12 Rev. 1.0 S1F75510 ■ ABSOLUTE MAXIMUM RATINGS Item Input supply voltage Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Input pin voltage 1 Input current Output current 1 Output current 2 Output current 3 Output current 4 Allowable dissipation Operating temperature Storage temperature Soldering temperature and time Symbol VDD VOUT1 VOUT2 VOUT3 VOUT4 V IN IVDD IVOUT1 IVOUT2 IVOUT3 IVOUT4 PD Topr Tstg Tsol Rating Min. – 0.3 – 0.3 – 0.3 – 0.3 – 15.0 – 0.3 — — — — — — – 30 – 55 — Max. 4.0 7.5 7.5 22.5 0.3 VDD + 0.3 (TBD) (TBD) (TBD) (TBD) (TBD) (TBD) 85 150 260·10 Unit V V V V V V mA mA mA mA mA mW ˚C ˚C ˚C·s Applicable pin VDD VOUT1 VOUT2 VOUT3 VOUT4 VDD VOUT1 VOUT2 VOUT3 VOUT4 — — — — Remarks — — — — — — — — — — Ta ≤ 55˚C — — At leads The applicable pins are POFFX, OSC1, CL, MODE and OSCSEL. Do not apply external voltage to the output pins and the pin connecting to the capacitor. Use of the IC under any conditions exceeding the above absolute maximum ratings may cause malfunctioning or permanent breakdown. Or, even if the IC may operate normally temporarily, the reliability may greatly drop. Rev. 1.0 13 S1F75510 ■ ELECTRICAL CHARACTERISTICS ● DC characteristics In case particular designations are not made (Note 1): Ta = –10 to +70˚C Item Symbol Conditions Input supply voltage High level input voltage Low level input voltage Input leak current 1 VDD V IH VIL ILKI1 Current consumption 1 IOPR1 Current consumption 2 IOPR2 Power conversion efficiency 1 (Overall efficiency including the stabilized outputs) Power conversion efficiency 2 (Overall efficiency including the stabilized outputs) Resting current Peff1 Applicable pin: VDD — — VSS ≤ VI ≤ VDD, VDD = (TBD) to 3.6V VDD = 3.0V, no load Under the normal mode VDD = 3.0V, no load Under the blank mode CL = (TBD) kHz VDD = 3.0V Under the normal mode Peff2 IQ VDD = 3.0V Under the blank mode CL = (TBD) kHz VDD = 3.6V POFFX = LOW Min. (TBD) 0.8VDD 0 – 0.5 Rating Typ. 3.0 — — — Max. 3.6 VDD 0.2VDD 0.5 Unit Remarks V V V µA — 2 2 2 (TBD) (300) (TBD) (30) (TBD) µA — (TBD) µA — (TBD) (TBD) (TBD) % 3 (TBD) (TBD) (TBD) % 4 — — (TBD) µA — — — (1.0) Conditions on the operation mode, external parts constant, pins, etc. in case particular designations are not made are as follows. Connection and parts constant : Standard connection 1, 10.1 MODE pin : MODE = HIGH (Normal mode) CL pin : CL = LOW (Fixed voltage) The applicable pins are XDIS, SSLP, PCK1 and CNT Load conditions: IVOUT2 = (TBD)mA, IVOUT3 = (TBD)µA, IVOUT4 = (TBD)µA Conversion efficiency = [(VOUT2 ✕ IVOUT2) + (VOUT3 ✕ IVOUT3) + (VOUT4 ✕ IVOUT4)] / (VDD* ✕ IVDD*) ✕ 100 Load conditions: IVOUT2 = (TBD)µA, IVOUT3 = (TBD)µA, IV OUT4 = (TBD)µA Conversion efficiency = [(VOUT2 ✕ IVOUT2) + (VOUT3 ✕ IVOUT3) + (VOUT4 ✕ IVOUT4)] / (VDD* ✕ IVDD*) ✕ 100 14 Rev. 1.0 S1F75510 ● Characteristics of ✕2 boosting in the positive direction + stabilized output Ta = –10 to +70˚C Item Symbol VOUT1 output impedance RVOUT1-1 (Normal mode) VOUT1 output impedance RVOUT1-2 (Blank mode) VOUT2 VOUT2 Stabilized output voltage VOUT2 Stabilized output RVOUT2 saturated resistance VDD VDD VDD VDD Conditions Applicable pin: VOUT1 Applicable pin: VOUT1 Applicable pin: VOUT2 Applicable pin: VOUT2 Min. — Rating Typ. (TBD) Max. (TBD) — (TBD) (TBD) (4.90) — (TBD) (5.00) — Unit Remarks Ω 5 (TBD) Ω 6 (TBD) (5.20) 10 V 7 Ω 8 = (TBD)V to 3.6V, Load condition: IVOUT1 = (TBD)mA = (TBD)V to 3.6V, Load condition: IVOUT1 = (TBD)mA = (TBD)V to 3.6V, Load condition: IVOUT2 = (TBD)mA = (TBD)V to 3.6V, Load condition: IVOUT2 = (TBD)mA ● Characteristics of ✕3 boosting in the positive direction and ✕3 boosting in he negativet direction Ta = –10 to +70˚C Item Symbol VOUT3 output impedance (Normal mode) VOUT3 output impedance (Blank mode) VOUT4 output impedance (Normal mode) VOUT4 output impedance (Blank mode) RVOUT3-1 Rev. 1.0 RVOUT3-2 RVOUT4-1 RVOUT4-2 Conditions Applicable pin: VOUT3 Applicable pin: VOUT3 Applicable pin: VOUT4 Applicable pin: VOUT4 Min. — Rating Typ. (TBD) Max. (TBD) — (TBD) — — Unit Remarks Ω 9 (TBD) Ω 10 (TBD) (TBD) Ω 11 (TBD) (TBD) Ω 12 VDD = (TBD)V to 3.6V, Load condition: IVOUT3 = (TBD)µA VDD = (TBD)V to 3.6V, Load condition: IVOUT3 = (TBD)µA VDD = (TBD)V to 3.6V, Load condition: IVOUT4 = (TBD)µA VDD = (TBD)V to 3.6V, Load condition: IVOUT4 = (TBD)µA 15 S1F75510 ● AC characteristics Measurement conditions for the AC characteristics · Input signal level V IH = 0.8 VDD (V) V IL = 0.2 VDD (V) · Input signal rise time Tr = Max. 100ns · Input signal fall time Tf = Max. 100ns V DD = (TBD) to 3.6V, VSS = 0V Ta = –10 to +70˚C CL inputting timing tWHCK CL VIH VIH VIH VIL VIL tWLCK tCCK Item Symbol CL cycle CL High pulse duration CL Low pulse duration tCCK 16 tWHCK tWICK Min. (TBD) (TBD) (TBD) Rating Typ. (TBD) — — Max. (TBD) — — Unit Applicable pin Remarks µs ns ns CL — Rev. 1.0 S1F75510 ■ REFERENCE EXTERNAL CONNECTION (AN EXAMPLE) ● Standard connection 1 VDD VSS VDD VSS C1P POFFX POFFX ROSC VOUT1 MODE CL VOUT2 C2 CVOUT1 + VOUT1 VOUT2 CVOUT2 + MODE C3P OSCSEL + C2N OSC2 CL C1 C1N C2P OSC1 + OSCSEL + C3 C3N C4P + C4 C4N VOUT3 C5P CVOUT3 + VOUT3 + C5 C5N Rev. 1.0 C6P Reference values for the external parts C6N ROSC=1MΩ C1=C2=CVOUT1=4.7µF CVOUT2=4.7µF C3=C4=CVOUT3=1.0µF C5=C6=CVOUT4=1.0µF VOUT4 + C6 CVOUT4 + VOUT4 17 S1F75510 ■ DIMENSIONAL OUTLINE DRAWING 7.6±0.2 5.6±0.2 SSOP3–24pin 0 ~ 10° 0.375 Typ. 0.65 0.5±0.2 0.22 +0.1 –0.05 0.12 0.15 +0.1 –0.05 0.10±0.05 1.15±0.1 7.9±0.2 M 0.10 Unit : mm NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 2001, All rights reserved. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ELECTRONIC DEVICES MARKETING DIVISION IC Marketing & Engineering Group ■ EPSON Electronic Devices Website http://www.epson.co.jp/device/ ED International Marketing Department Europe & U.S.A 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042–587–5812 FAX: 042–587–5564 ED International Marketing Department Asia 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042–587–5814 FAX: 042–587–5110 First issue July, 2001 Printed in Japan H 18 Rev. 1.0