S1R72U16
Data Sheet
Rev.2.00
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material is
applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any
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party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license
from the Ministry of Economy, Trade and Industry or other approval from another government agency.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
©SEIKO EPSON CORPORATION 2008, All rights reserved.
Scope
This document applies to the S1R72U16 IDE device - USB 2.0 host bridge LSI.
Notice
Before using the S1R72U16, carefully read the sections “Special use case for S1R72U16” and
“S1R72U16 Errata.”
Table of Contents
1. Overview............................................................................................................................................ 1
2. Features............................................................................................................................................. 2
3. Block Diagram................................................................................................................................... 4
4. Functions........................................................................................................................................... 5
4.1
Main CPU I/F .............................................................................................................................. 5
4.1.1
IDE Device Controller ........................................................................................................ 5
4.1.2
CPUIF................................................................................................................................ 5
4.2
USB Host.................................................................................................................................... 5
4.3
GPI ............................................................................................................................................. 5
4.4
GPO ........................................................................................................................................... 5
4.5
SIO ............................................................................................................................................. 6
4.6
OSC............................................................................................................................................ 6
5. Pin Layout Diagram .......................................................................................................................... 7
6. Pin Functions .................................................................................................................................... 8
6.1
IDE Mode.................................................................................................................................... 8
6.2
CPU Mode ................................................................................................................................ 11
7. Register ........................................................................................................................................... 12
7.1
Register Map ............................................................................................................................ 12
7.1.1
IDE Mode Register Map .................................................................................................. 12
7.1.2
CPU Mode Register Map................................................................................................. 12
7.2
Registers .................................................................................................................................. 13
7.2.1
Data Register .................................................................................................................. 13
7.2.2
Error Register .................................................................................................................. 13
7.2.3
Feature Register.............................................................................................................. 13
7.2.4
Sector Count Register ..................................................................................................... 13
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
i
7.2.5
LBA Low Register............................................................................................................ 13
7.2.6
LBA Mid Register............................................................................................................. 14
7.2.7
LBA High Register ........................................................................................................... 14
7.2.8
Device Register ............................................................................................................... 14
7.2.9
Status Register ................................................................................................................ 14
7.2.10
Command Register ......................................................................................................... 14
7.2.11
Alternate Status Register................................................................................................. 15
7.2.12
Device Control Register................................................................................................... 15
8. Electrical Characteristics ............................................................................................................... 16
8.1
Absolute Maximum Ratings ...................................................................................................... 16
8.2
Recommended Operating Conditions....................................................................................... 16
8.3
DC Characteristics.................................................................................................................... 17
8.3.1
Current Consumption ...................................................................................................... 17
8.3.2
Input Characteristics........................................................................................................ 18
8.3.3
Output Characteristics ..................................................................................................... 19
8.3.4
Pin Capacitance .............................................................................................................. 20
8.4
AC Characteristics.................................................................................................................... 21
8.4.1
Reset Timing ................................................................................................................... 21
8.4.2
Clock Timing.................................................................................................................... 21
8.4.3
USB I/F Timing ................................................................................................................ 22
8.4.4
IDE Device I/F Timing...................................................................................................... 22
8.4.5
CPUIF Timing (PIO) ........................................................................................................ 23
8.4.6
CPUIF Timing (DMA)....................................................................................................... 24
8.4.7
Serial I/F Timing .............................................................................................................. 25
9. Connection Examples .................................................................................................................... 26
10. External Dimensions Diagram ..................................................................................................... 27
10.1 PFBGA8UX81 .......................................................................................................................... 27
ii
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
10.2 QFP14-80 ................................................................................................................................. 28
11. Product Codes .............................................................................................................................. 29
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
iii
1. Overview
1. Overview
The S1R72U16 is an IDE device - USB 2.0 host bridge LSI that supports USB2.0-compliant high-speed
mode. The main CPU is capable of controlling USB storage devices connected to this LSI as IDE devices.
No USB driver is required. USB devices that can be connected to this LSI are bulk-only transport mass
storage class devices (e.g., USB memory) and HUB devices.
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
1
2. Features
2. Features
Easy use/connect (IDE bus connection)
Allows USB devices to be controlled as IDE devices
The main CPU is capable of controlling USB storage devices connected to this LSI as IDE devices.
This LSI handles connection processing for the USB hub, no USB driver is required at the main CPU.
An ATA/ATAPI driver should be installed at the main CPU.
A main CPU with an installed ATA/ATAPI driver is capable of controlling USB storage devices via
this LSI.
Easy use/connect (CPU bus connection)
Also permits CPU bus connections (interface voltage: 1.8 V to 3.3 V)
The LSI can also be connected to a memory bus to connect to the main CPU without an IDE bus. An
ATA/ATAPI driver should be installed in the main CPU. The registers used to control this LSI are
ATA task file registers.
High-speed transfer
Transfer rate 31 MB/s (Seiko Epson figures)
Transfer rates of up to 31 MB/s can be achieved with ATA100 and USB High-Speed connection.
Embedded Host silicon authentication
High-quality USB signal
This LSI includes an Embedded Host function (including authentication software) for silicon
authentication. The S1R72U16 USB 2.0 PCB Design Guide and S1R72U16 Embedded Host
Compliance Manual are also provided to help the user obtain USB logo certification.
Product (system) development support functions
History display
LSI internal processing history can be displayed using the serial (asynchronous) interface. The
S1R72U16 Development Support Manual provides detailed information on this function. This
function and the manual provide support for product (system) development.
Manuals and tools
Development manuals and tools (bridge board)
The following manuals are provided in addition to this data sheet:
• S1R72U16 Technical Manual
• S1R72U16 Application Note
• S1R72U16 Development Support Manual
• S1R72U16 USB 2.0 PCB Design Guide
• S1R72U16 Embedded Host Compliance Manual
2
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
2. Features
• S1R72U16 Evaluation Board Manual
An IDE device - USB 2.0 host bridge board is also provided for system evaluations in the early
stages of product (system) development. *
* Please contact your nearest Seiko Epson sales office to obtain the IDE device - USB 2.0 host
bridge board.
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
3
3. Block Diagram
3. Block Diagram
XCD0
XChgInt
XCD1
PLL_Locked
ComplianceError[3:0]
CSEL_T / CSEL
XHDASP_T /-
XHPDIAG_T / -
HINTRQ_T / XINT
XHRESET_T / XHRESET
HIORDY_T / -
HDA_T[2:0] / CA[2:0]
XHCS_T[1:0] / XCS, CA[3]
XHIOR_T / XRD
XHIOW_T / XWR
HDMARQ_T / XDREQ
XHDMACK_T / XDACK
HDD_T[15:0] / CD[15:0]
Main CPU I/F Selector
IDE Device
CPUIF
Controller
GPO
ATAxATAPI
GPI
2x1
CPUxIIDE
Bridge
Sequencer
FIFO
SCLK0
SIO
debug i/f*
SIN0
SOUT0
DBGDCLK, DBGDT,
DBGST
XRESET
USB Host SIE
Transceiver Macro
OSC
TSTEN, ATPGEN,
BURNIN
XO
XI
CLKSEL
VBUSEN
VBUSFLG
DP
R1
DM
Figure 3.1
test circuit*
Block diagram
* Fix the debug I/F and test circuit pins strictly as described in “6. Pin Functions”. They are not intended for
use by users.
4
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
4. Functions
4. Functions
4.1
Main CPU I/F
This LSI can be used as either of the following connections to the main CPU.
• IDE bus connection (interface voltage: 3.3 V)
• CPU bus connection (interface voltage: 1.8 V to 3.3 V)
Bus connection is selected by using the mode setting pin CPUxIDE (PORT02).
4.1.1
IDE Device Controller
This block operates when IDE bus connection is selected. It supports ATA/ATAPI-6.
• PIO transfer modes 0 to 4
• Multi Word DMA transfer modes 0 to 2
• Ultra DMA transfer modes 0 to 5
4.1.2
CPUIF
This block operates when CPU bus connection is selected. The registers used to control
this LSI are ATA task file registers. It supports PIO and DMA (*) transfer.
* For DMA transfer, the main CPU must provide a DMA master function that complies
with the DMA specifications of this LSI.
4.2
USB Host
The USB host function complies with the USB 2.0 (Universal Serial Bus Specification Revision 2.0)
standards. It supports HS (480 Mbps) and FS (12 Mbps) speed modes. USB host function is
controlled by the Bridge Sequencer block inside the LSI. USB devices that can be connected to this
LSI are bulk-only transport mass storage class devices (e.g., USB memory) and HUB devices.
4.3
GPI
These are the mode setting pins for selecting the command system, number of connected devices, and
interface to the main CPU.
For detailed information, see the S1R72U16 Technical Manual.
4.4
GPO
These pins are used to issue notification of USB storage device connections, internal PLL operation
status, and NSF (No Silent Failure).
For detailed information, see the S1R72U16 Technical Manual.
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
5
4. Functions
4.5
SIO
This block is used to display the product (system) development support function history.
For detailed information, see the S1R72U16 Development Support Manual.
4.6
OSC
This oscillator circuit supports a 12 MHz/24 MHz crystal oscillator. The 12 MHz or 24 MHz clock is
selected using the CLKSEL pin.
6
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
5. Pin Layout Diagram
5. Pin Layout Diagram
S1R72U16/PFBGA8UX81
Top View
1
2
3
4
5
6
7
8
9
TSTEN
ATPGEN
XO
XI
HDD3_T
IOVDD
HDD8_T
HDD10_T
NC
A
A
LVDD
VSS
LVDD
HDD0_T
HDD4_T
HDD6_T
HDD9_T
HDD11_T
LVDD
B
B
R1
VSS
CLKSEL
HDD1_T
HDD5_T
HDD7_T
HDD12_T
HDD13_T
HDD14_T
C
C
HVDD
BURNIN
VSS
HDD2_T
HDA0_T
HDA1_T
HDD15_T
HDA2_T
VSS
D
D
DM
VSS
VSS
PORT00
PORT01
XHCS1_T
XHCS0_T
XHDASP_T
XHRESET_T
E
E
DP
HVDD
VBUSFLG
PORT02
HINTRQ_T
PORT11
XHPDIAG_T
PORT17
CSEL_T
F
F
LVDD
VSS
VBUSEN
XRESET
XHIOW_T
PORT10
PORT13
PORT15
PORT16
DBGDCLK
DBGDT
DBGST
SIN0
HDMARQ_T
HIORDY_T
PORT12
PORT14
IOVDD
G
G
H
H
NC
HVDD
SOUT0
SCLK0
XHDMACK_T
XHIOR_T
VSS
LVDD
NC
1
2
3
4
5
6
7
8
9
J
J
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
LVDD
HDD11_T
HDD12_T
HDD13_T
HDD14_T
HDD15_T
HDA2_T
VSS
HDA1_T
HDA0_T
XHCS1_T
XHCS0_T
XHRESET_T
XHDASP_T
XHPDIAG_T
CSEL_T
PORT17
PORT16
PORT15
IOVDD
Figure 5.1 PFBGA8UX81 package pin layout diagram (*)
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
S1R72U16/QFP14-80
40
LVDD
39
PORT14
38
PORT13
37
PORT12
36
PORT11
35
PORT10
34
VSS
33
XHIOR_T
32 HIORDY_T
31
XHIOW_T
30 HDMARQ_T
29 XHDMACK_T
28 HINTRQ_T
27
PORT01
26
PORT00
25
PORT02
24
XRESET
23
SCLK0
22
SOUT0
21
HVDD
LVDD
VSS
R1
VSS
HVDD
DM
VSS
DP
HVDD
LVDD
VSS
NC
NC
VSS
VBUSFLG
VBUSEN
DBGDCLK
DBGDT
DBGST
SIN0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
HDD10_T
HDD9_T
HDD8_T
HDD7_T
HDD6_T
IOVDD
HDD5_T
HDD4_T
HDD3_T
HDD2_T
HDD1_T
HDD0_T
VSS
XI
XO
LVDD
CLKSEL
BURNIN
ATPGEN
TSTEN
Figure 5.2 QFP14-80 package pin layout diagram (*)
* Shown here with pin names for IDE mode connection.
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
7
6. Pin Functions
6. Pin Functions
6.1
IDE Mode
GENERAL (IOVDD system)
BGA
QFP
Name
I/O
G4
24
XRESET
IN
C3
77
CLKSEL
IN
RESET
-
Details
Reset signal
XI clock input selection
1: 24MHz 0: 12MHz
OSC (LVDD system)
BGA
QFP
Name
I/O
RESET
Details
A4
74
XI
IN
-
Internal oscillator circuit input
12MHz/24MHz
A3
75
XO
OUT
-
Internal oscillator circuit output
TEST (LVDD system)
BGA
QFP
Name
I/O
RESET
Details
A1
80
TSTEN
IN(PD)
-
Test pin (*)
A2
79
ATPGEN
IN(PD)
-
Test pin (*)
D2
78
BURNIN
IN(PD)
-
Test pin (*)
PD: Using pull-down I/O
* The LSI features internal pull-down, but low fixing is recommended on the circuit board.
USB
BGA
QFP
Name
I/O
RESET
Details
C1
3
R1
IN
-
Reference voltage setting pin
Connect 6.2 kΩ ±1% resistor between VSS.
F1
8
DP
BI
Hi-Z
USB data line
Data+
E1
6
DM
BI
Hi-Z
USB data line
Data-
F3
15
VBUSFLG
IN(PU)
-
USB power switch fault detection signal
1: Normal, 0: Error
CMOS Schmitt input
G3
16
VBUSEN
OUT
Low
USB power switch control signal
PU: Using pull-up I/O
8
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
6. Pin Functions
IDE device I/F (IOVDD system)
BGA
QFP
D8
54
D6
52
Name
I/O
RESET
HDA2_T
IN
-
HDA1_T
IN
-
Details
IDE register address
D5
51
HDA0_T
IN
-
E6
50
XHCS1_T
IN
-
Control register access chip selection
E7
49
XHCS0_T
IN
-
Command block register access chip selection
J6
33
XHIOR_T
IN
-
IDE read strobe
G5
31
XHIOW_T
IDE write strobe
H5
30
HDMARQ_T
J5
29
XHDMACK_T
IN
-
OUT
Low
DMA transfer request
IN
-
DMA transfer acknowledge
Hi-z
IDE register ready signal (*)
Low
IDE interrupt request
H6
32
HIORDY_T
OUT
(PU)
F5
28
HINTRQ_T
OUT
E9
48
XHRESET_T
IN
-
E8
47
XHDASP_T
BI(PU)
Hi-z
Drive enable/slave drive present (*)
IDE bus reset
F7
46
XHPDIAG_T
BI(PU)
Hi-z
Diagnosis sequence end signal (*)
F9
45
CSEL_T
IN
-
D7
55
HDD15_T
BI
Hi-Z
C9
56
HDD14_T
BI
Hi-Z
C8
57
HDD13_T
BI
Hi-Z
C7
58
HDD12_T
BI
Hi-Z
B8
59
HDD11_T
BI
Hi-Z
A8
61
HDD10_T
BI
Hi-Z
B7
62
HDD9_T
BI
Hi-Z
A7
63
HDD8_T
BI
Hi-Z
C6
64
HDD7_T
BI
Hi-Z
B6
65
HDD6_T
BI
Hi-Z
C5
67
HDD5_T
BI
Hi-Z
B5
68
HDD4_T
BI
Hi-Z
A5
69
HDD3_T
BI
Hi-Z
D4
70
HDD2_T
BI
Hi-Z
C4
71
HDD1_T
BI
Hi-Z
B4
72
HDD0_T
BI
Hi-Z
Drive selection
IDE data bus
PU: Using pull-up I/O
* LSI internal pull-up is disabled in IDE mode.
Serial I/F (HVDD system)
BGA
QFP
Name
I/O
RESET
J4
23
SCLK0
I(PU)
H4
20
SIN0
I(PU)
-
J3
22
SOUT0
O
High
Details
Not used (*)
Asynchronous serial data in
Asynchronous serial data out
PU: Using pull-up I/O
* Set to open or pull-up.
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
9
6. Pin Functions
DEBUG I/F (HVDD system)
BGA
QFP
H1
17
Name
I/O
RESET
Details
DBGDCLK
O
High
Not used (*1)
H2
18
DBGDT
BI(PU)
-
Not used (*2)
H3
19
DBGST
O
Low
Not used (*1)
PU: Using pull-up I/O
*1: Set to open or pull-up.
*2: The LSI features internal pull-up, but an external pull-up of approximately 10 kΩ is recommended.
GPIO (IOVDD system)
BGA
QFP
E4
26
E5
Name
I/O
RESET
Details
PORT00
(ATAxATAPI)
I
-
Setting pin
1: ATA mode, 0: ATAPI mode
27
PORT01
(2x1)
I
-
Setting pin
1: two-device mode, 0: one-device mode
F4
25
PORT02
(CPUxIDE)
I
-
Setting pin
1: CPU mode, 0: IDE mode
G6
35
PORT10
(XChgInt)
O
-
Storage device connection detection interrupt
1: -, 0: Connection detection
F6
36
PORT11
(XCD0)
O
-
Storage device 0 detection
1: -, 0: Detect
H7
37
PORT12
(XCD1)
O
-
Storage device 1 detection
1: -, 0: Detect
G7
38
PORT13
(PLL_Locked)
O
-
PLL oscillation start
1: Oscillation start, 0: No oscillation
H8
39
PORT14
(ComplianceErr0)
O
-
Unsupported Device
1: Error, 0: -
G8
42
PORT15
(ComplianceErr1)
O
-
Too Many Devices
1: Error, 0: -
G9
43
PORT16
(ComplianceErr2)
O
-
Too Many Hubs
1: Error, 0: -
F8
44
PORT17
(ComplianceErr3)
O
-
VBUS Over Current
1: Error, 0: -
POWER
BGA
QFP
Name
Voltage
D1, F2, J2
5, 9, 21
HVDD
3.3V
A6, H9
41, 66
IOVDD
3.3V to 1.8V
B1, G1, B3,
J8, B9
1, 10, 40,
60, 76
LVDD
1.8V
B2, C2, E2,
G2, D3, E3,
J7, D9
2, 4, 7, 11,
14, 34, 53,
73
VSS
0V
10
EPSON
Details
USB, UART, DEBUG I/F power supply
IDE I/F and GPIO power supply
Internal power supply, TEST power supply, OSC
power supply
GND
S1R72U16 Data Sheet (Rev. 2.00)
6. Pin Functions
6.2
CPU Mode
CPU memory bus I/F (IOVDD system)
BGA
QFP
D8
54
D6
52
Name
I/O
RESET
CA2
IN
-
CA1
IN
-
Details
Address
D5
51
CA0
IN
-
E6
50
XCS
IN
-
Chip selection
E7
49
CA3
IN
-
Address
J6
33
XRD
IN
-
Read strobe
G5
31
XWR
IN
-
Write strobe
H5
30
XDREQ
OUT
High
J5
29
XDACK
H6
32
-
F5
28
XINT
E9
48
XHRESET
E8
47
F7
DMA transfer request
IN
-
OUT(PU)
Hi-z
OUT
High
IN
-
-
BI(PU)
Hi-z
Not used (*)
46
-
BI(PU)
Hi-z
Not used (*)
F9
45
CSEL
IN
-
D7
55
CD15
BI
Hi-Z
C9
56
CD14
BI
Hi-Z
C8
57
CD13
BI
Hi-Z
C7
58
CD12
BI
Hi-Z
B8
59
CD11
BI
Hi-Z
A8
61
CD10
BI
Hi-Z
B7
62
CD9
BI
Hi-Z
A7
63
CD8
BI
Hi-Z
C6
64
CD7
BI
Hi-Z
B6
65
CD6
BI
Hi-Z
C5
67
CD5
BI
Hi-Z
B5
68
CD4
BI
Hi-Z
A5
69
CD3
BI
Hi-Z
D4
70
CD2
BI
Hi-Z
C4
71
CD1
BI
Hi-Z
B4
72
CD0
BI
Hi-Z
DMA transfer acknowledge
Not used (*)
Interrupt request
Bus reset
Drive selection
Data bus
PU: Using pull-up I/O
* Set to open or pull-up. LSI internal pull-up resistor is enabled in CPU mode.
For detailed information on pins other than those described above, see “6.1 IDE Mode”.
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
11
7. Register
7. Register
7.1
Register Map
7.1.1
IDE Mode Register Map
Pin
Register
XHCS1_T
XHCS0_T
HDA2_T
HDA1_T
HDA0_T
H
L
L
L
L
H
L
L
L
H
H
L
L
H
L
Sector Count
H
L
L
H
H
LBA Low
H
L
H
L
L
LBA Mid
H
L
H
L
H
LBA High
H
L
H
H
L
H
L
H
H
H
L
H
L
L
L
none
L
H
L
L
H
none
L
H
L
H
L
none
L
H
L
H
H
none
L
H
H
L
L
none
L
H
H
L
H
none
L
H
H
H
L
L
H
H
H
H
Figure 7.1
7.1.2
Read
Write
Data (16bit)
Error
Feature
Device
Status
Command
Alternate Status
IDE mode register map
CPU Mode Register Map
Pin
Register
XCS
CA3
CA2
CA1
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
Sector Count
L
L
L
H
H
LBA Low
L
L
H
L
L
LBA Mid
L
L
H
L
H
LBA High
L
L
H
H
L
L
L
H
H
H
L
H
L
L
L
none
L
H
L
L
H
none
L
H
L
H
L
none
L
H
L
H
H
none
L
H
H
L
L
none
L
H
H
L
H
L
H
H
H
L
L
H
H
H
H
Figure 7.2
12
Device Control
none
CA0
Read
Write
Data (16bit)
Error
Feature
Device
Status
Command
none
Alternate Status
Device Control
none
CPU mode register map
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
7. Register
7.2
Registers
These are ATA task file registers. For detailed information, see AT Attachment with Packet Interface
– 6 (ATA/ATAPI-6).
7.2.1
Data Register
This register permits reads/writes. It is used for data transfers. It supports 16-bit access
only.
bit15
bit14
Bit13
bit12
bit11
bit10
bit9
bit8
bit2
bit1
bit0
Data[15:8]
bit7
bit6
bit5
bit4
bit3
Data[7:0]
7.2.2
Error Register
This is a read-only register. The register value is enabled when the Status register ERR bit
is “1”. Bit assignments and values vary, depending on the ATA/ATAPI command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
#
#
#
#
#
ABRT
#
#
7.2.3
Feature Register
This is a write-only register. Writing to this register depends on the ATA/ATAPI command.
Bit assignments and values are defined for each command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Features Byte
7.2.4
Sector Count Register
This register permits reads/writes and sets the number of sectors for data transfers.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit1
bit0
Sector Count Byte
7.2.5
LBA Low Register
This register permits reads/writes and sets LBA [7:0].
bit7
bit6
bit5
bit4
bit3
bit2
LBA Low Byte
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
13
7. Register
7.2.6
LBA Mid Register
This register permits reads/writes and sets LBA [15:8].
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit1
bit0
LBA Mid Byte
7.2.7
LBA High Register
This register permits reads/writes and sets LBA [23:16].
bit7
bit6
bit5
bit4
bit3
bit2
LBA High Byte
7.2.8
Device Register
This register permits reads/writes. Bit assignments and values vary, depending on the
ATA/ATAPI command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Obsolute
#
Obsolute
DEV
#
#
#
#
7.2.9
Status Register
This read-only register is updated to indicate status when a command is executed. Reading this
register when the HINTRQ_T signal is asserted cause to nagate the HINTRQ_T signal.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BSY
DRDY
DF
#
DRQ
Obsolute
ChgInt
ERR
Bit 1 ChgInt
This bit, unique to this LSI, indicates whether a USB storage device is connected (using the
bit dropped as of AT Attachment with Packet Interface – 6 (ATA/ATAPI-6)). The XChgInt
signal status can be read off inverted. For detailed information, see the S1R72U16
Technical Manual.
7.2.10
Command Register
This is a write-only register. The register command is executed immediately on being
written. Issuing the command (writing to this register) when the HINTRQ_T signal is
asserted cause to nagate the HINTRQ_T signal.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Command Code
14
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
7. Register
7.2.11
Alternate Status Register
This read-only register is the same as the Status Register except when the HINTRQ_T
signal is not altered.
7.2.12
Device Control Register
This write-only register is used to reset the HINTRQ_T signal control and software and to
support Big Drive.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
HOB
#
#
#
#
SRST
nIEN
#
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
15
8. Electrical Characteristics
8. Electrical Characteristics
8.1
Absolute Maximum Ratings
(VSS=0V)
Item
Code
Power supply voltage
Rating
Units
HVDD
VSS-0.3 to 4.0
V
IOVDD
VSS-0.3 to 4.0
V
LVDD
Input voltage (*)
Output voltage (*)
VSS-0.3 to 2.5
V
HVI
VSS-0.3 to HVDD+0.5
V
IOVI
VSS-0.3 to IOVDD+0.5
V
LVI
VSS-0.3 to LVDD+0.5
V
HVO
VSS-0.3 to HVDD+0.5
V
IOVO
VSS-0.3 to IOVDD+0.5
V
Output current/pin
IOUT
±10
mA
Storage temperature
Tstg
-65 to 150
°C
* Check the power supply system information in “6. Pin Functions” for the corresponding pins.
8.2
Recommended Operating Conditions
Item
Code
MIN
TYP
MAX
Units
3.00
3.30
3.60
V
IOVDD (*1)
1.65
1.80 to
3.30
3.60
V
LVDD
1.65
1.80
1.95
V
HVI
-0.3
-
HVDD+0.3
V
HVDD
Power supply voltage
Input voltage (*2)
Ambient temperature
IOVI
-0.3
-
IOVDD+0.3
V
LVI
-0.3
-
LVDD+0.3
V
Ta
-40
25
85
°C
*1: Use with 3.3 V (typ) in IDE mode.
*2: Check the power supply system information in “6. Pin Functions” for the corresponding pins.
[Precautions for power-on sequence]
Power to the HVDD and IOVDD should be turned on/off with LVDD confirmed. (*)
• Power-on: LVDD → (HVDD, IOVDD)
• Power-off: (HVDD, IOVDD) → LVDD
* Reliability issues may arise if LVDD is cut off and HVDD or IOVDD or both are on continuously
for 1 second or longer.
16
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
8. Electrical Characteristics
8.3
DC Characteristics
8.3.1
Current Consumption
Item
Code
Conditions
MIN
TYP
MAX
Units
Power supply current (*)
Power current
IDDH
HVDD = 3.6V
-
17.0
mA
IDDCH
IOVDD = 3.6V
-
2.0
mA
IDDCL
IOVDD = 1.95V
-
1.5
mA
IDDL
LVDD = 1.95V
-
65.0
mA
IDDS
VIN = HVDD,IOVDD,LVDD or
VSS
-
-
70
μA
-5
-
5
μA
Static current
Power current
HVDD = 3.6V
IOVDD = 3.6V
LVDD = 1.95V
Input leak
Input leak current
IL
HVDD = 3.6V
IOVDD = 3.6V
LVDD = 1.95V
HVIH = HVDD
IOVIH = IOVDD
LVIH = LVDD
* Mean operating current at recommended operating conditions (Ta = 25°C)
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
17
8. Electrical Characteristics
8.3.2
Input Characteristics
Item
Code
Input characteristics
MIN
TYP
MAX
Units
TSTEN, ATPGEN, BURNIN, XI
“H” level input voltage
VIH1
LVDD = 1.95V
1.27
-
-
V
“L” level input voltage
VIL1
LVDD = 1.65V
-
-
0.57
V
Pin:
HDD_T[15:0], HAD_T[2:0], XHCS_T[1:0], XHIOR_T, XHIOW_T,
XHDMACK_T, XHRESET_T, XHDASP_T, XHPDIAG_T, CSEL_T
Input characteristics
“H” level input voltage
VIH2
IOVDD = 3.6V
IOVDD = 1.95V
2.0
1.27
-
-
“L” level input voltage
VIL2
IOVDD = 3.0V
IOVDD = 1.65V
-
-
0.8
0.57
Pin:
XRESET, CLKSEL, PORT00, PORT01, PORT02
“H” level input voltage
VIH3
IOVDD = 3.6V
IOVDD = 1.95V
2.2
1.20
-
-
“L” level input voltage
VIL3
IOVDD = 3.0V
IOVDD = 1.65V
-
-
0.8
0.50
V
Pin:
SCLK0, SIN0, DBGDT, VBUSFLG
“H” level trigger
voltage
VT1+
HVDD = 3.6V
1.4
-
2.7
V
“L” level trigger
voltage
VT1-
HVDD = 3.0V
0.6
-
1.8
V
Hysteresis voltage
ΔV1
HVDD = 3.0V
0.3
-
-
V
Pin:
DP, DM
VTU+
HVDD = 3.6V
1.1
-
1.8
V
Input characteristics
Input characteristics
(Schmitt)
Schmitt input
characteristics (USB: FS)
“H” level trigger
voltage
V
V
V
“L” level trigger
voltage
VTU-
HVDD = 3.0V
1.0
-
1.5
V
Hysteresis voltage
ΔVU
HVDD = 3.0V
0.1
-
-
V
Pin:
DP, DM pair
VDSU
HVDD = 3.0V
Differential input voltage
0.8V to 2.5V
-
-
0.2
V
Pin:
SCLK0, SIN0, DBGDT
RPLU1H
VI = HVDD
25
50
120
kΩ
Pin:
HINTRQ_T, XHDASP_T, XHPDIAG_T, VBUSFLG
RPLU2H
VI = HVDD or IOVDD
Pin:
ATPGEN, BURNIN
Input characteristics
(USB:FS differential input)
Differential input
sensitivity
Input characteristics
Pull-up resistance
Input characteristics
Pull-up resistance
Input characteristics
Pull-down resistance
Input characteristics
Pull-down resistance
Input characteristics
Pull-down resistance
18
Pin:
Conditions
RPLD1L
VI = LVDD
Pin:
TSTEN
RPLD2L
VI = LVDD
Pin:
VBUS
RPLDB
VI = 5.0V
EPSON
50
100
240
kΩ
24
60
150
kΩ
48
120
300
kΩ
110
125
150
kΩ
S1R72U16 Data Sheet (Rev. 2.00)
8. Electrical Characteristics
8.3.3
Output Characteristics
(VSS=0V)
Item
Code
Conditions
MIN
TYP
MAX
Units
Pin:
HDD_T[15:0], HDMARQ_T, HIORDY_T, HINTRQ_T, XHDASP_T,
XHPDIAG_T
VOH1
IOVDD = 3.0V
IOH = -4.0mA
IOVDD = 1.65V
IOH = -2.0mA
IOVDD - 0.4
-
-
V
VOL1
IOVDD = 3.0V
IOL = 4.0mA
IOVDD = 1.65V
IOL = 2.0mA
-
-
0.4
V
Pin:
PORT10, PORT11, PORT12, PORT13, PORT14, PORT15, PORT16,
PORT17
VOH2
IOVDD = 3.0V
IOH = -2.0mA
IOVDD = 1.65V
IOH = -1.0mA
IOVDD - 0.4
-
-
V
VOL2
IOVDD = 3.0V
IOL = 2.0mA
IOVDD = 1.65V
IOL = 1.0mA
-
-
0.4
V
Pin:
SOUT0, DBGDCLK, DBGDT, DBGST
“H” level output voltage
VOH3
HVDD = 3.0V
IOH = -4.0mA
HVDD - 0.4
-
-
V
“L” level output voltage
VOL3
HVDD = 3.0V
IOL = 4.0mA
-
-
0.4
V
Pin:
VBUSEN
“H” level output voltage
VOH4
HVDD = 3.0V
IOH = -2.0mA
HVDD - 0.4
-
-
V
“L” level output voltage
VOL4
HVDD = 3.0V
IOL = 2.0mA
-
-
0.4
V
Pin:
DP, DM
“H” level output voltage
VOHUF
HVDD = 3.0V
2.8
-
-
V
“L” level output voltage
VOLUF
HVDD = 3.6V
-
-
0.3
V
Pin:
DP, DM
“H” level output voltage
VOHUH
HVDD = 3.0V
360
-
-
mV
“L” level output voltage
VOLUH
HVDD = 3.6V
-
-
10.0
mV
Pin:
HDD_T[15:0], HDMARQ_T, HIORDY_T, HINTRQ_T, XHDASP_T,
XHPDIAG_T, SCLK0, SIN0, DBGDT
Output characteristics
“H” level output voltage
“L” level output voltage
Output characteristics
“H” level output voltage
“L” level output voltage
Output characteristics
Output characteristics
Output characteristics
(USB:FS)
Output characteristics
(USB:HS)
Output characteristics
OFF-STATE leakage
IOZ
S1R72U16 Data Sheet (Rev. 2.00)
HVDD, IOVDD = 3.6V
VOH = HVDD or IOVDD
VOL = VSS
EPSON
-5
-
5
μA
19
8. Electrical Characteristics
8.3.4
Pin Capacitance
Item
Pin capacitance
Input pin
capacitance
Pin capacitance
Output pin
capacitance
Pin capacitance
Input/output pin
capacitance
Pin capacitance
Input/output pin
capacitance (USB)
20
Code
Conditions
Pin:
All input pins
CI
f = 1MHz
HVDD = IOVDD = LVDD = VSS
Pin:
All output pins
CO
f = 1MHz
HVDD = IOVDD = LVDD = VSS
Pin:
Input/output pins except DP and DM
CB
f = 1MHz
HVDD = IOVDD = LVDD = VSS
Pin:
DP and DM
CBU
f = 1MHz
HVDD = IOVDD = LVDD = VSS
EPSON
MIN
TYP
MAX
Units
-
-
8
pF
-
-
8
pF
-
-
8
pF
-
-
11
pF
S1R72U16 Data Sheet (Rev. 2.00)
8. Electrical Characteristics
8.4
AC Characteristics
8.4.1
Reset Timing
tRESET
XRESET
Code
tRESET
8.4.2
Details
Min
Typ
Max
Units
Reset pulse width
40
-
-
ns
Min
Typ
Max
Units
Clock Timing
tCYC
tCYCL
tCYCH
XI
Code
Details
tCYC
Clock cycle (CLKSEL = "L")
11.9988
12.000
12.0012
MHz
tCYC
Clock cycle (CLKSEL = "H")
23.9976
24.000
24.0024
MHz
45
50
55
%
tCYCL
tCYCH
Clock duty
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
21
8. Electrical Characteristics
8.4.3
USB I/F Timing
Complies with USB 2.0 Universal Serial Bus Specification Revision 2.0 tandards.
8.4.4
IDE Device I/F Timing
Complies with AT Attachment with Packet Interface – 6 (ATA/ATAPI-6) standards.
22
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
8. Electrical Characteristics
8.4.5
CPUIF Timing (PIO)
PIO read/write
tcy
tasu
tahd
XCS, CA[3:0]
tspw
tsrc
XRD, XWR
trds
CD[15:0](read)
twds
trbf
trdh
twd
h
CD[15:0](write)
XDREQ
"High"
XDACK
"High"
Code
tcy
tasu
tspw
tsrc
trds
trdh
trbf
twds
twdh
tahd
Details
Cycle
Address setup
XRD/XWR pulse width
XRD/XWR recovery
Read data setup
Read data hold
Bus release
Write data setup
Write data set hold
Address hold
Min
120/130
25/30
70/75
25/30
20/15
5/5
20/25
10/10
10/10
Typ
-
Max
30/30
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
-
Units
ns
ns
* When using IOVDD = 3.0 V to 3.6 V / When using IOVDD = 1.8 V to 3.0 V (wide range)
S1R72U16***E200 AC characteristics
Code
Details
trdh
Read data hold time
tahd
Address hold time
Min
5/5 *1
0/0
Typ
-
* When using IOVDD = 3.0 V to 3.6 V / When using IOVDD = 1.8 V to 3.0 V (wide range)
*1: The read data hold time will be 0 ns for address changes if the address hold time is less than 5 ns.
Note: The definition of AC shown above uses the description format specified in ATA standards. Consider the valid data
output start time in a read operation as follows:
70 (XRD pulse width: min) -20 (read data setup: min) = 50 ns (when IOVDD = 3.0 to 3.6 V)
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
23
8. Electrical Characteristics
8.4.6
CPUIF Timing (DMA)
DMA read/write
tcy
tasu
tahd
XCS, CA[3:0]
tspw
tnpw
XRD, XWR
trds
CD[15:0](read)
twds
trbf
trdh
twd
h
CD[15:0](write)
trdl
XDREQ
tacs
tach
XDACK
Code
tcy
tasu
tspw
tspw
trds
trdh
trbf
twds
twdh
tahd
trdl
tacs
tach
Details
Cycle
Address setup
XRD/XWR pulse width
XRD/XWR negate pulse width
Read data setup
Read data hold
Bus release
Write data setup
Write data set hold
Address hold
XDREQ delay
XDACK setup
XDACK hold
Min
120/130
25/25
70/75
25/30
20/15
5/5
20/25
10/10
10/10
0/0
5/5
Typ
-
Max
30/30
35/45
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
-
Units
ns
ns
* When using IOVDD = 3.0 V to 3.6 V / When using IOVDD = 1.8 V to 3.0 V (wide range)
S1R72U16***E200 AC characteristics
Code
Details
trdh
Read data hold time
tahd
Address hold time
Min
5/5 *1
0/0
Typ
-
* When using IOVDD = 3.0 V to 3.6 V / When using IOVDD = 1.8 V to 3.0 V (wide range)
*1: The read data hold time will be 0 ns for address changes if the address hold time is less than 5 ns.
Note: The definition of AC shown above uses the description format specified in ATA standards. Consider the valid data
output start time in a read operation as follows:
70 (XRD pulse width: min) -20 (read data setup: min) = 50 ns (when IOVDD = 3.0 to 3.6 V)
24
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
8. Electrical Characteristics
8.4.7
Serial I/F Timing
tBR
tBR
SIN0/SOUT0
Code
tBR
Detail
Min
Typ
Max
Unit
-
19200
-
bps
Baud rate
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
25
9. Connection Examples
9. Connection Examples
Refer to the S1R72U16 Evaluation Board Manual for USB I/F, IDE I/F, CPU I/F (in CPU mode), and Serial
I/F connection examples.
26
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
10. External Dimensions Diagram
10. External Dimensions Diagram
10.1 PFBGA8UX81
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
27
10. External Dimensions Diagram
10.2 QFP14-80
28
EPSON
S1R72U16 Data Sheet (Rev. 2.00)
11. Product Codes
11. Product Codes
Table 11.1
Product codes
Product code
Details
S1R72U16B08E100
S1R72U16B08E200
PFBGA8UX81 package
S1R72U16F14E100
S1R72U16F14E200
QFP14-80 package
S1R72U16 Data Sheet (Rev. 2.00)
EPSON
29
Revision History
Revision History
Rev.
Page
05/14/2007
0.79
All pages
New
Newly established
07/01/2007
1.00
8.3.1
8.3.2
8.3.3
8.4.5
8.4.6
8.4.7
Addition
Addition
Addition
Addition
Addition
Addition
Spec. added
Spec. added(IOVDD=1.8V)
Spec. added(IOVDD=1.8V)
Spec. added
Spec. added
Serial I/F Timing added
10/15/2007
1.10
Scope
Add
Added “notice.”
2
Correct
Changed “IDE driver” to “ATA/ATAPI driver.”
6.1 and
6.2
Correct
Changed setting of unused terminal from “open” to “open or pull-up.”
8.4.2
Correct
Spec. corrected as follows:
“11.999” to “11.9988”
“12.001” to “12.0012
“23.998” to “23.9976”
“24.002” to “24.0024”
8.4.5
and
8.4.6
Add
Added note regarding valid data output start time.
8.4.5
8.4.6
Addition
Added S1R72U16***E200 timing.
11
Addition
Added S1R72U16***E200 product code.
04/21/2008
2.00
Type
Details
International Sales Operations
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
HEADQUARTERS
EPSON (CHINA) CO., LTD.
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Phone: +1-800-228-3964
FAX: +1-408-922-0238
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HEADQUARTERS
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FAX: +49-89-14005-110
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Telex: 65542 EPSCO HX
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Phone: +86-755-2699-3828
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Phone: +886-2-8786-6688
FAX: +886-2-8786-6660
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Phone: +65-6586-5500
FAX: +65-6271-3182
SEIKO EPSON CORPORATION
KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: +82-2-784-6027
FAX: +82-2-767-3677
GUMI OFFICE
2F, Grand B/D, 457-4 Songjeong-dong,
Gumi-City, KOREA
Phone: +82-54-454-6027
FAX: +82-54-454-6093
SEIKO EPSON CORPORATION
SEMICONDUCTOR OPERATIONS DIVISION
IC Sales Dept.
IC International Sales Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814
FAX: +81-42-587-5117
Document Code: 411135202
First Issue May 2007
Revised April 2008, JAPAN ○
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