S1V30120F01A100

S1V30120 Hardware Specification Rev.1.2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ©SEIKO EPSON CORPORATION 2008, All rights reserved. Fonix DECtalk(R) and Fonix Logo are registered trademarks of Fonix Corporation. The ARM Powered Logo is a registered trademark of ARM Limited. All other trademarks are the property of their respective owners. Table of Contents 1. Outline .......................................................................................................................................... 1 2. Features .......................................................................................................................................... 1 3. Pinout Diagram (Top View)............................................................................................................... 2 4. Pin Description ................................................................................................................................. 3 5. Function Description ........................................................................................................................ 5 5.1 Typical Application System ......................................................................................................... 5 6. Electrical Characteristics ................................................................................................................. 6 6.1 Absolute Maximum Rating.......................................................................................................... 6 6.2 Recommended Operating Conditions......................................................................................... 6 6.3 DC Characteristics...................................................................................................................... 8 6.4 AC Characteristics.................................................................................................................... 11 6.4.1 Clock Timing.................................................................................................................... 11 6.4.2 Initialization Timing .......................................................................................................... 12 6.4.2.1 Power-on/Reset Timing ................................................................................................ 12 6.4.2.2 Power-off Sequence ..................................................................................................... 13 6.4.3 6.5 Clock Synchronous Serial Interface (SPI) ....................................................................... 14 Full-Digital Audio Amplifier ........................................................................................................ 15 7. External Connection Example ....................................................................................................... 16 7.1 Connection Example: Clock Synchronous Serial Interface....................................................... 16 8. Package Dimensions ...................................................................................................................... 17 S1V30120 Hardware Specification (Rev. 1.2) EPSON i 1. Outline 1. Outline The S1V30120 is a Speech Synthesis IC that provides a cost effective solution for adding Text-To-Speech (TTS) and ADPCM speech processing applications to a range of portable devices. The highly integrated design reduces overall system cost and time-to-market. The S1V30120 contains all the required analogue codecs, memory, and EPSON-supplied embedded algorithms. All applications are controlled over a single serial interface (SPI) allowing control from a wide range of hosts and rapid integration into existing products. 2. Features • Text To Speech Synthesis (TTS) • Fonix DECtalk® v5, fully parametric speech synthesis • Languages: US English, Castilian Spanish, Latin American Spanish • Nine pre-defined voices • Sampling rate: 11.025kHz • Audio reproduction (ADPCM) • ADPCM decoding (in Epson’s original format) • Bit rate: 80kbps, 64kbps, 48kbps, 40kbps, 32kbps and 24kbps • Sampling rate: 16, 8 kHz • Host interface • Synchronous serial interface (SPI interface is supported) • Command control • 16-bit full-digital amplifier • Sampling rate (fs): 16, 11.025 and 8 kHz • Digital Input: 16 bits • Operating voltage: 3.3/1.8V • Clock • 32.768KHz • Package • 64-pin TQFP (10mm x 10mm) with 0.5mm-pitch pins • Supply voltage • 3.3V (I/O power supply) • 1.8V (Core power supply) S1V30120 Hardware Specification (Rev. 1.2) EPSON 1 3. Pinout Diagram (Top View) GPIOA8 GPIOA9 GPIOA0 LVDD TSTMODE2 TSTMODE1 TSTMODE0 VSS TESTEN LVDD EXCKM HVDD CLKI PLLVSS VCP PLLVDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 3. Pinout Diagram (Top View) HVDD 49 32 LVDD 50 31 SPPDN VSS 51 30 SPHMT GPIOA1 52 29 LVDD GPIOA2 53 28 HVDD GPIOA3 54 27 AVDD GPIOA4 55 26 HPO HVDD 56 S1V30120F00A*** [TQFP13-64] 25 AVSS 24 LVDD LVDD 57 GPIOA5 58 23 VSS GPIOA6 59 22 AUDCLK GPIOA7 60 21 HPOP VSS 61 20 LVDD NRESET 62 19 TDO 10 11 12 13 14 15 16 SFRM2 LVDD TCK TMS TDI NTRST VSS 7 SFRM1 9 6 VSS SOUT 5 SIN 8 4 SCLK HVDD 3 HPON LVDD 17 2 64 GPIOA11 18 HVDD 1 63 HVDD GPIOA10 SCANEN Fig. 3-1 2 VSS TQFP13-64 Package Pinout EPSON S1V30120 Hardware Specification (Rev. 1.2) 4. Pin Description 4. Pin Description • Symbols I = Input pin O = Output pin IO = Bi-directional pin P = Power pin Z = High impedance I/O cells Symbol Function IC LVCMOS input IH LVCMOS Schmitt-level input ICP1 LVCMOS input with pull-up resistor （50kΩ when 3.3V (typ)） ICD2 LVCMOS input with pull-down resistor (100kΩ when 3.3V (typ)) O1 Output buffer (2mA/-2mA output current when 3.3V (typ)) O3 Output buffer (8mA/-8mA output current when 3.3V (typ)) T1 3-state output buffer (2mA/-2mA output current when 3.3V (typ)) BC1 Bi-directional IO buffer (2mA/-2mA output current when 3.3V (typ)） BC1P2 Bi-directional IO buffer with pull-up resistor (100kΩ when 3.3V (typ)) (2mA/-2mA output current when 3.3V(typ)) BC1D2 Bi-directional IO buffer with pull-down resistor (100kΩ when 3.3V (typ)) (2mA/-2mA output current when 3.3V (typ)) BC3D2 Bi-directional IO buffer with pull-down resistor (100kΩ when 3.3V (typ)) (8mA/-8mA output current when 3.3V(typ)) LOT Transparent Output ITST1 Test input with pull-down resistor (120kΩ when 1.8V (typ)) Clock synchronous serial interface Pin Name Pin I/O I/O Cell Type RESET# State Power Pin Description SIN 5 IO BC1 Z HVDD Serial data input SCLK 4 IO BC1 Z HVDD Serial clock input SFRM1 7 IO BC3P2 Z HVDD Slave device select input SOUT 9 IO BC3P2 Pull-up HVDD Serial data output SFRM2 10 IO O3 L HVDD Master device select output GPIO Pin Name Pin I/O I/O Cell Type RESET# State Power GPIOA[11:0] 2,1,47,48,60,59,58, 55,54,53,52,46 IO BC1D2 Pull-down HVDD S1V30120 Hardware Specification (Rev. 1.2) EPSON Pin Description General-purpose IO port 3 4. Pin Description Full-digital audio amplifier Pin Name Pin I/O I/O Cell Type RESET# State Power Pin Description HPO 26 O LOT L AVDD Audio output HPON 17 O O1 L HVDD Inverted, unbuffered –digital- version of HPO AUDCLK 22 O O1 L HVDD Audio PWM clock HPOP 21 O O1 H HVDD Unbuffered –digital- version of HPO SPPDN 31 O O1 L HVDD Open in normal operation SPHMT 30 O O1 L HVDD Audio output in output period (Low active) I/O I/O Cell Type RESET# State Power Clock/Reset Pin Name Pin Pin Description CLKI 36 I IC Z HVDD Reference clock input (32.768kHz） NRESET 62 I IH Z HVDD Reset input (Low active) Pin I/O I/O Cell Type TSTMODE[2:0] 44, 43, 42 I IC Z HVDD Test pin (Set to low in normal operation) TESTEN 40 I ITST1 Pull-down LVDD Test pin (Set to low in normal operation) SCANEN 63 I IBD2 Pull-down HVDD Test pin (Set to low in normal operation) EXCKM 38 I IC Z HVDD Test pin (Set to low in normal operation) Test Pin Name RESET# State Power Pin Description NTRST 15 I IH Z HVDD Test pin (Set to low in normal operation) TDI 14 I ICP1 Pull-up HVDD Test pin (Set to high in normal operation) TMS 13 I ICP1 Pull-up HVDD Test pin (Set to high in normal operation) TCK 12 I ICP1 Pull-up HVDD Test pin (Set to high in normal operation) TDO 19 O T1 Z HVDD Test pin (Open in normal operation) VCP 34 O LOT Z PLLVDD Test pin (Open in normal operation) Power supply Pin Name 4 Pin I/O Pin Description HVDD 8,18,28,37,49,56,64 P Power supply for I/O buffers (3.3V) LVDD 3,11,20,24,29,39,45,50,57 P Power supply for the internal circuit (1.8V) PLLVDD 33 P Power supply for PLL (1.8V) AVDD 27 P Power supply for full-digital amplifier (1.8V / 3.3V) VSS 6,16,23,32,41,51,61 P GND (I/O, internal circuit) PLLVSS 35 P GND (PLL) AVSS 25 P GND (Full-digital amplifier) EPSON S1V30120 Hardware Specification (Rev. 1.2) 5. Function Description 5. Function Description 5.1 Typical Application System Host Message I/F (Serial interface) HOST FLASH (SRAM_VECTORS) Mono S1V30120 32.768 KHz 3.3V / 1.8V Fig. 5-1 Standard Application system Fig. 5-1 illustrates a typical application system using the S1V30120. The host processor communicates with the S1V30120 over the serial interface, using commands (message protocol) to control the embedded algorithms. For more information on commands, see “S1V30120 Message Protocol Specification.” On reset the S1V30120 runs the bootstrap loader firmware. The host must then use bootstrap loader messages to load the SRAM firmware contents and ROM firmware updates (SRAM_VECTORS) into the S1V30120 device’s SRAM and to switch to running the main mode. These SRAM_VECTORS are stored in FLASH in the typical application system shown in Fig. 5-1 above. Refer to section 4 of the S1V30120 message protocol specification for details of the bootstrap loader messages and section 5 for details of the the main mode messages. S1V30120 Hardware Specification (Rev. 1.2) EPSON 5 6. Electrical Characteristics 6. Electrical Characteristics 6.1 Absolute Maximum Rating (VSS=0[V]) Parameter Supply voltage 6.2 Symbol Rated Value Unit HVDD VSS-0.3 ~+4.0 V LVDD VSS-0.3~+2.5 V PLLVDD VSS-0.3 ~ +2.5 V AVDD VSS-0.3 ~ +4.0 V Input voltage HVI VSS-0.3 ~ HVDD+0.5 V LVI VSS-0.3 ~ LVDD+0.5 V Output voltage HVO VSS-0.3 ~ HVDD+0.5 V AVO VSS-0.3 ~ HVDD+0.5 V Output current/pin (Except HPO) IOUT ±10 mA Storage temperature Tstg -65 ~ +150 °C Recommended Operating Conditions (VSS=0[V]) Parameter Supply voltage Input voltage Ambient temperature Symbols Min. Typ. Max. Unit HVDD 3.00 3.30 3.60 V LVDD 1.65 1.80 1.95 V PLLVDD 1.65 1.80 1.95 V AVDD 1.65 1.80 1.95 V 3.00 3.30 3.60 HVI VSS - HVDD V LVI VSS - LVDD V Ta -40 25 85 °C Take the following sequences for powering on or off the IC: (When AVDD=1.8V) Power on: LVDD/PLLVDD/AVDD => HVDD Power off: HVDD => LVDD/PLLVDD/AVDD (When AVDD=3.3V) Power on: LVDD/PLLVDD => HVDD/AVDD Power off: HVDD/AVDD => LVDD/PLLVDD Notes: − Do not apply voltage only to HVDD longer than a second with LVDD, PLLVDD and AVDD turned off, or the product reliability may be harmed. 6 EPSON S1V30120 Hardware Specification (Rev. 1.2) 6. Electrical Characteristics − When returning HVDD from the off-state to the on-state, the state of the internal circuit is not guaranteed due to power supply noise, etc. Therefore, be sure to initialize the circuit by NRESET after the IC power-up. S1V30120 Hardware Specification (Rev. 1.2) EPSON 7 6. Electrical Characteristics 6.3 DC Characteristics The DC input characteristics (based on Section 6.2 Recommended Operating Conditions) Parameter Symbol Condition Min. Typ. Max. Unit Supply current Supply current1 IDDH HVDD=3.3V - 0.05 - mA IDDL LVDD=1.8V - 20.0 - mA IDDP PLLVDD=1.8V - 1.5 - mA IDDAL AVDD=1.8V, no load - 0.4 - mA IDDAH AVDD=3.3V, no load - 1.0 - mA IDDSH VIN = HVDD or VSS - 2.0 - μA Static current Supply current2 IDDSL HVDD=3.6V - 5.0 - μA IDDSP LVDD=PLLVDD=1.95V - 0.2 - μA IDDSA AVDD=3.6V - 0.3 - μA -5 - 5 μA Input leakage Input leakage current HVDD=3.6V LVDD=1.95V PLLVDD=1.95V IL AVDD=3.6V HVIH=HVDD LVIH=LVDD VIL=VSS 1: Approximate current values during the Text to Speech Synthesis under the recommended operating conditions (Ta=25°C) 2: Static current under the recommended operating conditions (Ta=25°C) 8 EPSON S1V30120 Hardware Specification (Rev. 1.2) 6. Electrical Characteristics The DC input characteristics (based on Section 6.2, Recommended Operating Conditions) (Continued) Parameter Input characteristic (LVCMOS) Symbol Condition Min. Typ. Max. Unit Pin names: SIN, SCLK, SFRM1, SOUT, GPIOA[11:0], CLKI, TSTMODE[2:0], SCANEN, EXCKM, TDI, TMS, TCK H-level input voltage HVIH HVDD=3.6V 2.2 - - V L-level input voltage HVIL HVDD=3.0V - - 0.8 V Input characteristic (LVCMOS) H-level input voltage L-level input voltage Schmitt input characteristic (LVCMOS) H-level input voltage Pin name: TESTEN LVIH LVDD=1.95V 1.27 - - V LVIL LVDD=1.65V - - 0.57 V HVDD=3.6V 1.4 - 2.7 V Pin names: NRESET, NTRST VT+ L-level input voltage VT- HVDD=3.0V 0.6 - 1.8 V Hysteresis voltage ΔV HVDD=3.0V 0.3 - - V 25 50 120 kΩ 50 100 240 kΩ 50 100 240 kΩ 48 120 300 kΩ Input characteristic Pull-up resistance Input characteristic Pull-up resistance Input characteristic Pull-down resistance Input characteristic Pull-down resistance Pin name: TDI, TMS, TCK RPU1 VI=VSS Pin name: SFRM1,SOUT RPU2 VI=VSS Pin name: GPIOA[11:0], SCANEN RPD1 VI=HVDD Pin name: TESTEN RPD2 VI=LVDD S1V30120 Hardware Specification (Rev. 1.2) EPSON 9 6. Electrical Characteristics Parameter Symbol Output characteristic Min. Typ. Max. Unit Pin names: SIN, SCLK, GPIOA[11:0], AUDCLK, HPOP, SPPDN, SPHMT TDO, HPON H-level output voltage VOH1 HVDD=3.0V IOH=-2mA HVDD-0.4 - - V L-level output voltage VOL1 HVDD=3.0V IOL=2mA - - VSS+0.4 V Output characteristic Pin name: SOUT,SFRM1,SFRM2 H-level output voltage VOH2 HVDD=3.0V IOH=-8mA HVDD-0.4 - - V L-level output voltage VOL2 HVDD=3.0V IOL=8mA - - VSS+0.4 V Output characteristic Pin names: SIN, SCLK, SFRM1, SFRM2, SPPDN, SPHMT, AUDCLK, HPOP, HPON, SOUT, GPIOA[11:0], TDO Off-state leakage current Parameter Output characteristic Input pin capacitance Pin capacitance Output pin capacitance Pin capacitance I/O pin capacitance 10 Condition IOZ Symbol Pin names: CI HVDD=3.6V HVOH=HVDD VOL=VSS -5 Condition - 5 μA Min. Typ. Max. Unit - - 8 pF - - 8 pF - - 8 pF All input pins f=1MHz HVDD=LVDD=AVDD= PLLVDD=0V Pin names: All output pins except HPO CO1 Pin names: CIO f=1MHz HVDD=LVDD=AVDD= PLLVDD=0V All output pins f=1MHz HVDD=LVDD=AVDD= PLLVDD=0V EPSON S1V30120 Hardware Specification (Rev. 1.2) 6. Electrical Characteristics 6.4 AC Characteristics 6.4.1 Clock Timing tPWH tPWL 90% HVIH 10% HVIL tr tf T OSC tcycle1 tCJper Fig. 6-1 Symbol tcycle2 Clock Timing Parameter Min. Typ. Max. Unit - 32.768 - kHz fOSC Input clock frequency TOSC Input clock period - 1/fosc - μs tpwh Input clock pulse width high 5 - - μs tpwｌ Input clock pulse width low 5 - - μs tr Input clock rising time (10% ->90%) - - 12 μs tf Input clock falling time (90%->10%) - - 12 μs tCJper Input clock period jitter (*2, 4) -10 - 10 ns tCJcycle Input clock cycle jitter (*1, 3, 4) -10 - 10 ns *1 tCJcycle = tcycle1 - tcycle2 *2 The input clock period jitter is the displacement relative to the center period (reciprocal of center frequency). *3 The input clock cycle jitter is difference in period between adjacent cycles. *4 The jitter characteristics must meet both tCjper and tCjcycle characteristics. S1V30120 Hardware Specification (Rev. 1.2) EPSON 11 6. Electrical Characteristics 6.4.2 Initialization Timing 6.4.2.1 LVDD PLLVDD (AVDD) Power-on/Reset Timing t1 t2 HVDD (AVDD) t4 t3 t4 NRESET CLKI Fig. 6-2 Symbol 12 Power-on/Reset Timing Parameter Min. Max. Unit t1 Delay from the LVDD and PLLVDD (AVDD) power-on to HVDD (AVDD) power-on*1 10 - μs t2 Minimum delay from the HVDD power-on to theCLK1 rising edge before NRESET release 100 - μs t3 The minimum RESET assertion on system power up 2 - TOSC*2 t4 NRESET synchronization time (Number of clock cycles before NRESET is applied internally) 2 - TOSC*2 *1 See Section 6.2 Recommended Operating Conditions. *2 TOSC is the CLKI clock period. EPSON S1V30120 Hardware Specification (Rev. 1.2) 6. Electrical Characteristics 6.4.2.2 Power-off Sequence LVDD PLLVDD (AVDD) t1 HVDD (AVDD) Fig. 6-3 Symbol Power-off Sequence Parameter t1 Delay from HVDD (AVDD) power-off to LVDD and PLLVDD (AVDD) power-off *1. *1 See Section 6.2, Recommended Operating Conditions. S1V30120 Hardware Specification (Rev. 1.2) EPSON Min. Max. Unit - 500 μs 13 6. Electrical Characteristics 6.4.3 Clock Synchronous Serial Interface (SPI) t1 t3 t2 SFRM1 SCLK SIN Low SOUT MSB LSB MSB LSB Low t7 SCLK t5 t6 Input Data SIN Output Data SOUT t8 t1 t9 SFRM1 SCLK Low Fig. 6-4 Symbol 14 Low Active SOUT Clock Synchronous Serial Interface Parameter Min. Max. Unit t1 SFRM1 falling time to SCLK falling time 200 - ns t2 SCLK cycle time 1.0 - μs t3 SCLK rising time to SFRM1 rising time 200 - ns t5 SIN setup time 10 - ns t6 SIN hold time 200 - ns t7 SCLK falling time to SOUT going active - 200 ns t8 SCLK falling time to SOUT going active with SFRM1=L - 200 ns t9 SFRM1 rising time to SOUT going Low - 250 ns EPSON S1V30120 Hardware Specification (Rev. 1.2) 6. Electrical Characteristics 6.5 Full-Digital Audio Amplifier The electrical characteristics of the full-digital audio amplifier are as follows unless otherwise noted: − Ta = 25°C − HVDD = 3.3V, LVDD = 1.8V, PLLVDD = 1.8V − Input signal frequency = 1kHz − Input signal level = 0dBFS − fs = 32kHz − Test frequency range= 20Hz ~16kHz − Load impedance = 16Ω − Connection to the 2nd low-pass filter to the output (HPO) When AVDD = 1.8V Parameter Symbol Condition Min. Typ. Max. Unit Load impedance RL 16 - - Ω Output power Po 2 3 - mW Total harmonic distortion THD+N - 0.13 0.25 % Signal noise ratio SNR 73 76 - dB Min. Typ. Max. Unit 16 - - Ω Input signal level = -6dBFS When AVDD = 3.3V Parameter Symbol Load impedance RL Output power Po Total harmonic distortion THD+N Signal noise ratio SNR Condition Input signal level = -6dBFS 8 11 - mW - 0.1 0.15 % 79 82 - dB − Full Digital Amplifier characteristic may be deteriorated by AVDD Voltage fluctuation. Use stable power supplies for AVDD. S1V30120 Hardware Specification (Rev. 1.2) EPSON 15 7. External Connection Example 7. External Connection Example 7.1 Connection Example: Clock Synchronous Serial Interface Host Device S1V30120 Serial Clock Out SCLK Serial Data In SOUT Serial Data Out SIN I/O Port Fig. 7-1 SFRM1 Clock Synchronous Serial Interface Connection Example Note: When SFRM1 is Low, SOUT goes active. When SFRM1 is High, SOUT goes Low. 16 EPSON S1V30120 Hardware Specification (Rev. 1.2) 8. Package Dimensions 8. Package Dimensions Fig. 8-1 S1V30120F00A*** Dimensions S1V30120 Hardware Specification (Rev. 1.2) EPSON 17 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS EPSON (CHINA) CO., LTD. 2580 Orchard Parkway San Jose , CA 95131,USA Phone: +1-800-228-3964 FAX: +1-408-922-0238 SALES OFFICES Northeast 301 Edgewater Place, Suite 210 Wakefield, MA 01880, U.S.A. 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SHENZHEN BRANCH 12/F, Dawning Mansion, Keji South 12th Road, Hi- Tech Park, Shenzhen Phone: +86-755-2699-3828 FAX: +86-755-2699-3838 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110 Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 FAX: +65-6271-3182 SEIKO EPSON CORPORATION KOREA OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: +82-2-784-6027 FAX: +82-2-767-3677 GUMI OFFICE 2F, Grand B/D, 457-4 Songjeong-dong, Gumi-City, KOREA Phone: +82-54-454-6027 FAX: +82-54-454-6093 SEIKO EPSON CORPORATION SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept. IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 FAX: +81-42-587-5117 Document Code: 410996604 First Issue July 2007 Revised July 2008 in JAPAN ○ C