S2D13515B00B100

S1D13515 / S2D13515 Display Controller Hardware Functional Specification SEIKO EPSON CORPORATION Rev. 1.7 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ©SEIKO EPSON CORPORATION 2006 - 2011, All rights reserved. S1D13515/S2D13515 Table Of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 2 Features . . . . . . 2.1 Memory . . . . . . . 2.2 CPU Interfaces . . . . 2.3 Panel Interface Support . 2.4 Display Features . . . 2.5 Embedded CPU . . . . 2.6 Sprite Engine . . . . . 2.7 Video / Camera Input . 2.8 Clock Source . . . . . 2.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 14 14 15 15 15 16 Chapter 3 Typical Implementation Use Cases . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Use Case 1 - Heads-Up Display (HUD) with LCD Panel . . . . . . . . . . . . . 17 3.2 Use Case 2 - Dual-View Panel with Streaming Data and Camera Input . . . . . . . . 18 Chapter 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 5 Pins . . . . . . . . . . . . . 5.1 Pinout Diagram (QFP22 256-pin) . 5.2 Pinout Diagram (PBGA 256-pin) . 5.3 Pin Descriptions . . . . . . . 5.3.1 Host Interface . . . . . . . . 5.3.2 LCD Interface . . . . . . . . 5.3.3 SDRAM Interface . . . . . . 5.3.4 Camera / I2C Interface . . . 5.3.5 SPI Flash Interface . . . . . 5.3.6 I2S Interface . . . . . . . . . 5.3.7 Miscellaneous . . . . . . . . 5.3.8 Power And Ground . . . . . 5.4 Configuration Pins . . . . . . 5.5 Host Interface Pin Mapping . . . 5.6 LCD / Camera2 Pin Mapping . . Chapter 6 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 22 23 26 27 28 28 29 29 31 32 34 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Chapter 7 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Hardware Functional Specification Rev. 1.7 EPSON 3 S1D13515/S2D13515 7.1.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . 7.1.3 PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Power Supply Sequence . . . . . . . . . . . . . . . 7.2.1 Power Supply Structure . . . . . . . . . . . . . . . . . 7.2.2 Power-On Sequence . . . . . . . . . . . . . . . . . . . 7.2.3 Power-Off Sequence . . . . . . . . . . . . . . . . . . . 7.3 RESET# Timing . . . . . . . . . . . . . . . . . . 7.4 Parallel Host Bus Interface Timing . . . . . . . . . . . 7.4.1 Direct/Indirect Intel 80 Type 1 . . . . . . . . . . . . . 7.4.2 Direct/Indirect Intel 80 Type 2 . . . . . . . . . . . . . 7.4.3 Direct Marvell PXA3xx VLIO . . . . . . . . . . . . . 7.4.4 Direct/Indirect Renesas SH4 . . . . . . . . . . . . . . 7.4.5 Direct/Indirect Freescale MPC555 (Non-burst Mode) . 7.4.6 Direct/Indirect Freescale MPC555 (Burst Mode) . . . . 7.4.7 Direct/Indirect TI TSM470 (Non-burst Mode) . . . . . 7.4.8 Direct/Indirect TI TSM470 (Burst Mode) . . . . . . . . 7.4.9 Direct/Indirect NEC V850 Type 1 . . . . . . . . . . . . 7.4.10 Direct/Indirect NEC V850 Type 2 . . . . . . . . . . . . 7.5 Serial Host Bus Interface Timing . . . . . . . . . . . 7.5.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Panel Interface Timing . . . . . . . . . . . . . . . 7.6.1 Generic TFT Panel Timing . . . . . . . . . . . . . . . 7.6.2 ND-TFD 8-Bit Serial Interface Timing . . . . . . . . . 7.6.3 ND-TFD 9-Bit Serial Interface Timing . . . . . . . . . 7.6.4 a-Si TFT Serial Interface Timing . . . . . . . . . . . . 7.6.5 uWIRE Serial Interface Timing . . . . . . . . . . . . . 7.6.6 24-Bit Serial Interface Timing . . . . . . . . . . . . . . 7.6.7 Sharp DualView Panel Timing . . . . . . . . . . . . . 7.6.8 EID Double Screen Panel Timing (TCON Enabled) . . 7.7 Camera Interface Timing . . . . . . . . . . . . . . . 7.8 SDRAM Interface Timing . . . . . . . . . . . . . . 7.9 I2S Interface Timing . . . . . . . . . . . . . . . . 7.10 Keypad Interface Timing . . . . . . . . . . . . . . . 7.11 Serial Flash (SPI) Interface Timing . . . . . . . . . . . Chapter 8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 . . 46 . .47 . . 47 . . 48 . . 48 . .49 . .50 . . 50 . . 54 . . 58 . . 62 . . 66 . . 70 . . 74 . . 78 . . 82 . . 86 . .90 . . 90 . . 92 . .93 . . 93 . . 98 . .100 . .102 . .103 . .104 . .105 . .110 . 118 . 119 . 121 . 123 . 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Chapter 9 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Chapter 10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 10.2 Register Set . . . . . . . . . . . . . . . . . . 10.3 Register Restrictions . . . . . . . . . . . . . . . 10.4 Register Descriptions . . . . . . . . . . . . . . 10.4.1 System Control Registers . . . . . . . . . . . . . . 10.4.2 Host Interface Registers . . . . . . . . . . . . . . . 10.4.3 Bit Per Pixel Converter Configuration Registers . . 10.4.4 I2S Control Registers . . . . . . . . . . . . . . . . 10.4.5 I2S DMA Registers . . . . . . . . . . . . . . . . . 10.4.6 GPIO Registers . . . . . . . . . . . . . . . . . . . 10.4.7 Keypad Registers . . . . . . . . . . . . . . . . . . 10.4.8 PWM Registers . . . . . . . . . . . . . . . . . . . 10.4.9 SDRAM Read/Write Buffer Registers . . . . . . . 10.4.10 Warp Logic Configuration Registers . . . . . . . . 10.4.11 Blending Engine Configuration Registers . . . . . 10.4.12 Image Fetcher Configuration Registers . . . . . . . 10.4.13 LCD Configuration Registers . . . . . . . . . . . . 10.4.14 Interrupt Configuration Registers . . . . . . . . . . 10.4.15 Timer Configuration Registers . . . . . . . . . . . 10.4.16 SPI Flash Memory Interface Registers . . . . . . . 10.4.17 Cache Control Register . . . . . . . . . . . . . . . 10.4.18 Camera Interface Registers . . . . . . . . . . . . . 10.4.19 DMA Controller Registers . . . . . . . . . . . . . 10.4.20 SDRAM Controller Configuration Registers . . . . 10.4.21 LCD Panel Configuration Registers . . . . . . . . . 10.4.22 Sprite Registers . . . . . . . . . . . . . . . . . . . 10.4.23 Sprite Memory Based Registers . . . . . . . . . . . Chapter 11 Operating Configurations and States 11.1 Hard Reset State . . . . . . . . . . . . 11.2 C33PE Run State . . . . . . . . . . . . 11.3 C33PE Reset State . . . . . . . . . . . 11.4 Power Save State . . . . . . . . . . . . 11.5 Soft Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 . 140 . 140 . 140 . 159 . 164 . 181 . 187 . 190 . 195 . 202 . 207 . 217 . 233 . 268 . 275 . 296 . 317 . 321 . 325 . 326 . 354 . 366 . 369 . 414 . 421 . . . . . . . . . . . . . . . . . . . . . . . . . 432 . 433 . 438 . 439 . 439 . 439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 12 Bit-Per-Pixel Converter Functional Description . . . . . . . . . . . . . . . 440 12.1 System Level Connections . . . . . . . . . . . . . . . . . . . . . . . . . 442 Chapter 13 Display Subsystem . . . . 13.1 Block Diagram . . . . . . . . 13.2 Hardware Blocks . . . . . . . 13.2.1 LCD Panel Interface . . . . . 13.2.2 Blending Engine . . . . . . . Hardware Functional Specification Rev. 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPSON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 . . . . 443 . . . . 446 . . . . . 446 . . . . . 451 5 S1D13515/S2D13515 13.2.3 Warp Engine . . . . . . . . . . . . . . . . . . . 13.2.4 CH1OUT Writeback . . . . . . . . . . . . . . . 13.2.5 Warp Writeback . . . . . . . . . . . . . . . . . 13.2.6 Image Fetcher . . . . . . . . . . . . . . . . . . 13.2.7 Input Selectors for LCD Panel Interface . . . . 13.3 Memory Organization of Frames . . . . . . . . 13.3.1 “Line-by-Line” Image Storage . . . . . . . . . 13.3.2 “Tiled Frame” Image Storage . . . . . . . . . . 13.4 Frame Double-Buffering Scheme . . . . . . . . 13.4.1 Overview . . . . . . . . . . . . . . . . . . . . 13.4.2 Frame Producer Flowchart . . . . . . . . . . . 13.4.3 Frame Consumer Flowchart . . . . . . . . . . . 13.4.4 Registers for Frame Double-Buffering Control . 13.5 Gamma LUT . . . . . . . . . . . . . . . . 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 14 I2S Audio Output Interface . . . . . . . . . . 14.1 Overview of Operation . . . . . . . . . . . . . 14.2 Audio Data Formats and Organization in Memory . . . 14.3 WS Polarity . . . . . . . . . . . . . . . . . . 14.4 Channel Data Blanking . . . . . . . . . . . . . 14.5 WS Timing in Relation to SDO . . . . . . . . . . 14.6 PCM Data Bit Order . . . . . . . . . . . . . . 14.7 WS/SCK Signal Direction . . . . . . . . . . . . 14.8 Interrupts . . . . . . . . . . . . . . . . . . . 14.8.1 I2S FIFO Interrupts . . . . . . . . . . . . . . . . 14.8.2 I2S DMA Interrupt . . . . . . . . . . . . . . . . 14.9 I2S Typical Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 . . . . 476 . . . . 477 . . . . 477 . . . . 477 . . . . 477 . . . . 478 . . . . 478 . . . . 478 . . . . . .478 . . . . . .478 . . . . 479 Chapter 15 2D BitBLT . . . . . . . . . . . 15.1 ROM Monitor BitBLT Functions . . 15.2 Loadable BitBLT Functions . . . . 15.2.1 Small Library . . . . . . . . . . 15.2.2 Large Library . . . . . . . . . . 15.2.3 Other Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 . . . . 481 . . . . 482 . . . . . .482 . . . . . .482 . . . . . .482 Chapter 16 Sprite Engine . . . . . . . . . . . . . . . . . . . . 16.1 Sprite Data Path . . . . . . . . . . . . . . . . . . 16.2 8 Sprite Support with Z-ordering Transparency . . . . . . 16.3 8 Sprite Support with Z-ordering Alpha-Blending . . . . . 16.4 Reference Point Based 90°, 180° and 270° Rotation + Mirror 16.5 Sprite Display Orientation and Positioning . . . . . . . . 16.6 Sprite Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPSON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460 . .462 . .463 . .463 . .464 . 465 . .465 . .466 . 467 . .467 . .469 . .470 . .471 . 474 . 483 . 484 . 485 . 486 . 488 . 489 . 494 Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 17 SDRAM Interface . . . . . 17.1 SDRAM Device Types . . . . . 17.2 SDRAM Timing Options . . . . 17.2.1 tRP Timing Parameter . . . . 17.2.2 tRCD Timing Parameter . . 17.2.3 tRAS Timing Parameter . . . 17.3 SDRAM Initialization . . . . . 17.4 Self-Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 . . . . . . 497 . . . . . . 499 . . . . . . . . 499 . . . . . . . . 499 . . . . . . . . 499 . . . . . . 500 . . . . . . 501 Chapter 18 SDRAM Read/Write Buffer 18.1 Introduction . . . . . . . . . 18.2 Operation . . . . . . . . . . 18.2.1 Write Operation . . . . . . . 18.2.2 Read Operation . . . . . . . 18.2.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 . . . . . . 502 . . . . . . 502 . . . . . . . . 504 . . . . . . . . 505 . . . . . . . . 506 . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 19 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . 507 Chapter 20 General-Purpose IO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 Chapter 21 Host Interface . . . . . . . 21.1 Overview . . . . . . . . . . 21.2 Intel80 Type1 Interface . . . . . 21.3 Intel80 Type2 Interface . . . . . 21.4 NEC V850 Type1 Interface . . . 21.5 NEC V850 Type2 Interface . . . 21.6 Renesas SH4 Interface . . . . . 21.7 Marvell PXA3xx Interface . . . 21.8 TI TMS470 Interface . . . . . 21.9 MPC555 Interface . . . . . . . 21.10 SPI Host Interface . . . . . . . 21.11 I2C Host Interface . . . . . . . 21.12 Host Interface Access Methods . 21.12.1 Direct Mode . . . . . . . . . 21.12.2 Indirect Mode . . . . . . . . 21.13 Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 22 Camera Interface Subsystem 22.1 Overview . . . . . . . . . . . 22.2 IO Pins for Camera Interfaces . . . 22.2.1 8-bit Camera Interface . . . . . 22.2.2 RGB Streaming Input Interface 22.3 Camera Input Interface . . . . . . 22.4 Resizer . . . . . . . . . . . . Hardware Functional Specification Rev. 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 . . . . . . 512 . . . . . . 514 . . . . . . 515 . . . . . . 516 . . . . . . 517 . . . . . . 518 . . . . . . 519 . . . . . . 520 . . . . . . 521 . . . . . . 522 . . . . . . 526 . . . . . . 529 . . . . . . . . 529 . . . . . . . . 531 . . . . . . 533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 . . . . . . 535 . . . . . . 536 . . . . . . . . 536 . . . . . . . . 536 . . . . . . 537 . . . . . . 538 EPSON 7 S1D13515/S2D13515 22.5 YUV-to-RGB Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 539 22.6 Camera Writer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Chapter 23 Keypad Interface . . . . . . 23.1 Keypad Pin Mapping . . . . . . 23.2 Scanning Operation . . . . . . . 23.3 Input Glitch Filter . . . . . . . 23.4 General-Purpose Input Function . . 23.5 Interrupts . . . . . . . . . . . 23.6 Keypad Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 . 541 . 541 . 542 . 542 . 542 . 543 Chapter 24 Timers . . . . . 24.1 Watchdog Timer . . 24.2 Timer 0 . . . . . 24.3 Timer 1 . . . . . 24.4 Timer Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 . 545 . 545 . 545 . 546 Chapter 25 SPI Flash Memory Interface . . . . . . . . . 25.1 Overview . . . . . . . . . . . . . . . . . . . 25.2 IO Pins for SPI Interface . . . . . . . . . . . . . 25.3 SPI Interface Registers . . . . . . . . . . . . . 25.3.1 SPI Flash Chip Select Control Register . . . . . . 25.3.2 SPI Flash Control Register . . . . . . . . . . . . 25.3.3 SPI Flash Data Control Register . . . . . . . . . . 25.3.4 SPI Flash Write Data Register . . . . . . . . . . . 25.3.5 SPI Flash Read Data Register . . . . . . . . . . . 25.3.6 SPI Flash Status Register . . . . . . . . . . . . . 25.4 SPI Interface Operation Flow . . . . . . . . . . . 25.5 SPI Flash Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 . . . . 547 . . . . 548 . . . . 548 . . . . . .548 . . . . . .548 . . . . . .549 . . . . . .549 . . . . . .549 . . . . . .549 . . . . 550 . . . . 555 Chapter 26 JTAG Interface . . . . . . . . . . . . . . . . . 26.1 JTAG Pins . . . . . . . . . . . . . . . . . . 26.2 TAP Controller . . . . . . . . . . . . . . . . 26.2.1 TAP Controller Paths . . . . . . . . . . . . . . . 26.2.2 TAP Controller Main State . . . . . . . . . . . . 26.2.3 TAP Controller State Machine . . . . . . . . . . 26.3 JTAG Instruction Codes . . . . . . . . . . . . . 26.3.1 Boundary Scan Cell Definitions . . . . . . . . . . 26.3.2 Example BSDL File for the S2D13515 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 . . . . 556 . . . . 557 . . . . . .557 . . . . . .557 . . . . . .558 . . . . 559 . . . . . .560 . . . . . .560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 27 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 27.1 Guidelines for PLL Power Layout . . . . . . . . . . . . . . . . . . . . . . 572 Chapter 28 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 8 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 29 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 Chapter 30 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 Hardware Functional Specification Rev. 1.7 EPSON 9 S1D13515/S2D13515 10 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 1 Introduction Chapter 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13515/S2D13515 Display Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development. The latest revision can be downloaded at www.erd.epson.com. We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com. 1.2 Overview Description The S1D13515/S2D13515 is a highly integrated color LCD graphics controller with external memory interface. The architecture is designed to meet the needs of automotive and embedded markets requiring a flexible LCD solution. For automotive applications, the S2D13515 has three primary target placements within a vehicle. 1. Heads-Up Display 2. Instrument Cluster 3. Center Console The S1D13515/S2D13515 advances on the successes of other Epson LCD controllers by embedding a proprietary 32-bit RISC CPU and associated accelerator blocks to achieve an increase in flexibility and functionality over previous designs. Routines are provided allowing for audio playback, 2D BitBLT operations, warp and filtering before display operations, and the ability to offer OpenGL-ES 1.1 support. In particular, the warp functions make this an ideal solution for the automotive Heads-Up Display (HUD) market, or pseudo 3D navigation displays. The S1D13515/S2D13515 is an affordable, low power device which uses a flexible external SDRAM memory interface to provide its frame buffer. It supports a wide variety of CPU interfaces and LCD panel types, including Double Display panels, which makes it an excellent choice for instrumentation or center cluster applications. While focusing on the automotive market, the S1D13515/S2D13515’s impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of other markets. The S1D13515/S2D13515 design includes some of the following key features: 1. Warp engine for HUD projection correction 2. Embedded 32-bit proprietary RISC CPU 3. Support for two TFT Displays simultaneously 4. Support for Double Display LCD panels from Epson and Sharp 5. The ability to provide OpenGL-ES library functionality 6. The ability to playback audio 7. The ability to reset and display an image without the Host CPU involvement Hardware Functional Specification Rev. 1.7 EPSON 11 Chapter 2 Features S1D13515/S2D13515 Chapter 2 Features 2.1 Memory • Uses external SDRAM which is: • Accessible by both the internal and Host CPUs • Used for executable code, data, and the frame buffer • Addressable through direct or indirect access modes • Accessible linearly in configurable 4M byte paging windows (direct access mode) • SDRAM Interface: • SDRAM Clock Frequency: 100Mhz (typical) • Supports x16 and x32 SDRAM interfaces (x32 is strongly recommended in most cases) • Supports 8/16/32/64M bytes of 4 bank SDRAM • Low power design 2.2 CPU Interfaces Note The S1D/S2D13515 supports Little Endian interface only. • Direct and indirect interface support for the following CPU interfaces: • Intel 80 Types 1 and 2 (8/16-bit) • Renesas SH-4 (8/16-bit) • FreeScale MPC555 PowerPC bus interface with burst and non-burst modes (16-bit Little Endian configuration only) • NEC V850 Types 1 and 2 (8/16-bit) • Texas Instruments TMS470 with burst mode (16-bit only) • Marvell PXA3xx (16-bit Direct only) • Serial Host Interface • SPI • I2C 12 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 2 Features 2.3 Panel Interface Support • Single or Dual panels (dual panel implementations can have independent images) • LCD1 supports: • 12/16/18-bit interface for Generic TFT/TFD • Optionally, LCD1 pins can be used for a second Camera / RGB data stream • LCD2 supports: • 12/16/18/24-bit interface for Generic TFT/TFD • EID Double Screen panel • Sharp DualView panel • Optional Serial Command interface supports: • a-Si TFT interface (8-bit) • TFT w/u-Wire interface (16-bit) • EPSON ND-TFD 4 pin interface (8-bit) • EPSON ND-TFD 3 pin interface (9-bit) • 24-bit serial • Panel Resolution Examples: • 800x480 + 320x240 @ 32 bpp, 60Hz • 1024x768 @ 32 bpp, 60Hz • TV-Out can be achieved by connecting an external TV encoder, such as the S1D13746, to the LCD outputs Hardware Functional Specification Rev. 1.7 EPSON 13 Chapter 2 Features S1D13515/S2D13515 2.4 Display Features • Four input window sources can be stored in SDRAM (Main/Aux/OSD/LCD Fetcher) and support: • 8/16/24 bpp color depths • Hardware / Software Double Buffer Frame Control • Horizontal Flip • Virtual Width • Alpha Blending for the OSD • Blending Engine can combine various input window sources for output • Three input sources • Input sources can be blended in four different ways • Warp logic for HUD projection correction or other distortion compensation • Processed image can be sent back to SDRAM • Camera1 or Camera2 image can be stored in SDRAM and used for Main/Aux/OSD/LCD Fetcher/Warp/Sprite • Interrupt • Maskable Non-Display (Vsync) Interrupt support • Delayed version of Vsync Interrupt support • All interrupts are sent to the internal CPU, but can also be redirected to the HOST 2.5 Embedded CPU • Embedded CPU Speed: 50MHz (typical) • 32-bit RISC CPU with the following routines: • Audio decode (supported codecs: MP3, AAC, WAV, ADPCM, Ogg Vorbis) • 2D BitBLT Acceleration with API Some functions will be embedded in mask ROM, others will be provided as optional. • OpenGL-ES Assist (OpenGL-ES v1.1 compliant) • OEM defined functions 14 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 2 Features 2.6 Sprite Engine • 2D Sprite Engine • Up to Eight Sprites • Image rotation and mirror functions • Alpha Blending • Typical usage: Instrument Cluster, Simple GUI composition, etc. 2.7 Video / Camera Input • Video / Camera input port supporting one of the following configurations: • up to two 8-bit cameras • up to two RGB data streams • one 8-bit camera and one RGB data stream • Note: When the second camera input is used, only a single panel is available. • Supports ITU-R BT.656 YUV format • Supports Interlaced or Progressive input • Supports down-scaling of the video input stream • Captures YUV Data into SDRAM as RGB format 2.8 Clock Source • Flexible Clock Structure: • Two embedded PLLs • Built-in crystal input • Digital clock input • Clocks are dynamically turned off when modules are not needed Hardware Functional Specification Rev. 1.7 EPSON 15 Chapter 2 Features S1D13515/S2D13515 2.9 Miscellaneous • Internal System Clock Speed: 50MHz (typical) • IRQ output pin • Multiple interrupt sources (LCD1 / LCD2 / DMA / Timer / Keypad / etc.) • I2C interface (typically used for camera) • I2S interface (typically used for audio output) • PWM: 2 channel for backlight control • SPI Flash Memory interface • Keypad Interface • 5 x 5 matrix support • Software initiated power save mode • General Purpose Input/Output pins are available • IO operates at 3.3 volts ± 0.3v • Core operates at 1.8 volts ± 0.15v • Packages: • S1D13515B00B - PBGA1U 256-pin package (Body Size: 17 x 17 x 1.7 mm, Ball pitch: 1.0 mm) • S2D13515B00B - PBGA1U 256-pin package (Body Size: 17 x 17 x 1.7 mm, Ball pitch: 1.0 mm) • S1D13515F00A - QFP22 256-pin package (Body Size: 28 x 28 x 1.4 mm, Pin pitch: 0.4 mm) • S2D13515F00A - QFP22 256-pin package (Body Size: 28 x 28 x 1.4 mm, Pin pitch: 0.4 mm) • Temperature Range: • S1D13515; -40° C to +85° C • S2D13515; -40° C to +105° C 16 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 3 Typical Implementation Use Cases Chapter 3 Typical Implementation Use Cases The following are generic Use Cases. For specific implementations of the S1D13515 and S2D13515, please see the Application Notes. 3.1 Use Case 1 - Heads-Up Display (HUD) with LCD Panel SDRAM Memory Host CPU Data and Control Signals Display (TFT panels only) 13515 HUD Projection System Hardware Functional Specification Rev. 1.7 EPSON 17 Chapter 3 Typical Implementation Use Cases S1D13515/S2D13515 L R L R L R L R L R L R R L 3.2 Use Case 2 - Dual-View Panel with Streaming Data and Camera Input Streaming Data (TFT RGB 8:8:8) Camera Interface Rear View from Vehicle From DVD Player Host CPU Data and Control Signals 13515 Dual-View Display SDRAM Memory 18 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 4 Block Diagram Chapter 4 Block Diagram SDRAM Display Panels 16 16 Camera Interface Display Subsystem SDRAM Controller VBUS64 VBUS1 C33PE Data Host Interface VBUS to VBUS64 Bridge Arb Coproc. Data C33PE & Coproc. Core Arb Host C33PE Instruction Arb DMA Sprite Engine VBUS2 I2S Interrupt Controller VBUS to cAPB Bridge Serial Flash I/F Serial Flash / ROM cAPB Keypad Interface PWM Miscellaneous System Registers Timers GPIO S1D13515/S2D13515 Bus Masters / Requesters NOTE: Registers are accessed through the cAPB Bus. Bus Slaves Figure 4-1: Block Diagram Hardware Functional Specification Rev. 1.7 EPSON 19 Chapter 5 Pins S1D13515/S2D13515 Chapter 5 Pins 5.1 Pinout Diagram (QFP22 256-pin) PIO2VDD VSS FP2IO2 FP2IO1 FP2IO0 WSIO SDO SCKIO MCLKO PWM2 PWM1 IOVDD VSS COREVDD SPICS# SPICLK SPIDIO TESTEN TDO TCK TDI TMS TRST VSS CNF2 CNF1 CNF0 MEMDQM3 MEMDQM2 MEMDQM1 MEMDQM0 MEMCKE MEMCS# MEMRAS# MEMCAS# VSS SDVDD MEMWE# MEMBA1 MEMBA0 MEMA12 MEMA11 MEMA10 MEMA9 MEMA8 VSS SDVDD MEMDQ31 MEMDQ15 MEMDQ30 MEMDQ14 VSS COREVDD MEMDQ29 MEMDQ13 MEMDQ28 MEMDQ12 MEMDQ27 VSS SDVDD MEMDQ11 MEMDQ26 MEMDQ10 MEMDQ25 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 MEMDQ9 MEMDQ24 SDVDD VSS MEMDQ8 MEMDQ23 MEMDQ7 MEMDQ22 MEMDQ6 MEMDQ21 MEMDQ5 MEMDQ20 SDVDD COREVDD VSS MEMCLK VSS MEMDQ4 MEMDQ19 MEMDQ3 MEMDQ18 MEMDQ2 MEMDQ17 MEMDQ1 MEMDQ16 MEMDQ0 VSS SDVDD MEMA7 MEMA6 MEMA5 MEMA4 MEMA3 MEMA2 MEMA1 MEMA0 SCL SDA CM1FIELD CM1VREF CM1HREF CM1VDD CM1DAT7 CM1DAT6 CM1DAT5 CM1CLKOUT VSS CM1CLKIN COREVDD CM1DAT4 CM1DAT3 CM1DAT2 CM1DAT1 CM1DAT0 OSCVSS OSCO OSCI OSCVDD PLL2VSS VCP2 PLL2VDD PLL1VSS VCP1 PLL1VDD 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 INDEX FP2IO3 FP2IO4 FP2IO5 FP2IO6 FP2IO7 FP2IO8 VSS PIO2VDD FP2IO9 FP2IO10 FP2IO11 FP2IO12 FP2IO13 FP2IO14 FP2IO15 COREVDD VSS PIO2VDD FP2IO16 FP2IO17 FP2IO18 FP2IO19 FP2IO20 FP2IO21 FP2IO22 FP2IO23 VSS PIO2VDD FP2IO24 FP2IO25 FP2IO26 FP2IO27 FP1IO0 FP1IO1 FP1IO2 FP1IO3 PIO1VDD VSS FP1IO4 FP1IO5 FP1IO6 FP1IO7 FP1IO8 FP1IO9 FP1IO10 FP1IO12 PIO1VDD VSS COREVDD FP1IO23 FP1IO13 FP1IO15 FP1IO16 FP1IO20 FP1IO21 FP1IO22 PIO1VDD VSS FP1IO11 FP1IO14 FP1IO17 FP1IO18 FP1IO19 RESET# 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VSS IRQ WAIT# TEA# BDIP# BURST# BS# BE1# BE0# RD/WR# RD# M/R# CS# HIOVDD COREVDD VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 HIOVDD BUSCLK VSS DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 VSS HIOVDD AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 COREVDD VSS HIOVDD AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 VSS CLKI VSS Figure 5-1: QFP22-256 Pin Mapping 20 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins 5.2 Pinout Diagram (PBGA 256-pin) These marks are for reference only and do not appear on the top of the package. A B C D E F G H J K L M N P R T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TOP VIEW Figure 5-2: PBGA1U-256 Pin Mapping Table 5-1: PBGA1U-256 Pin Mapping 1 2 3 4 5 6 A VSS VCP1 PLL2VDD VCP2 OSCI OSCO B CLKI PLL1VDD PLL1VSS PLL2VSS OSCVDD OSCVSS C AB20 VSS CM1DAT0 CM1DAT1 CM1DAT2 CM1DAT3 D AB15 AB16 AB18 AB19 HIOVDD AB13 AB14 AB17 E COREVDD 7 8 CM1CLKOUT CM1DAT5 9 10 11 12 13 14 15 16 MEMA0 MEMA6 MEMDQ1 MEMCLK MEMDQ21 MEMDQ23 SDVDD VSS SDVDD MEMDQ18 VSS MEMDQ6 MEMDQ8 MEMDQ25 MEMDQ10 B CM1CLKIN CM1VREF MEMA1 A VSS CM1FIELD MEMA3 MEMDQ0 MEMDQ4 COREVDD MEMDQ22 MEMDQ9 MEMDQ26 MEMDQ11 C CM1DAT6 SDA MEMA5 MEMDQ16 VSS MEMDQ20 MEMDQ24 SDVDD MEMDQ27 MEMDQ12 D CM1DAT7 CM1VDD SCL MEMA7 MEMDQ2 SDVDD MEMDQ7 VSS MEMDQ28 VSS CM1DAT4 COREVDD COREVDD E F AB6 AB7 AB10 VSS AB11 AB12 CM1HREF MEMA2 MEMDQ17 MEMDQ19 MEMDQ5 MEMDQ29 MEMDQ14 MEMDQ30 MEMA8 SDVDD F G HIOVDD AB2 AB3 AB4 AB5 AB8 AB9 MEMA4 MEMDQ3 MEMDQ13 MEMDQ15 MEMDQ31 VSS MEMA9 MEMA10 MEMA12 G H DB12 DB15 DB13 DB14 VSS AB0 AB1 VSS VSS MEMA11 MEMBA1 MEMWE# SDVDD J BUSCLK DB8 DB9 HIOVDD DB7 DB10 DB11 VSS VSS CNF0 K DB3 DB2 DB4 DB5 DB6 DB1 FP1IO10 FP2IO26 FP2IO18 FP2IO10 L DB0 COREVDD CS# VSS HIOVDD FP1IO16 FP1IO9 FP1IO0 FP2IO21 M M/R# RD# RD/WR# BE0# BS# FP1IO15 FP1IO8 FP1IO1 FP2IO22 N BE1# BURST# BDIP# VSS FP1IO21 COREVDD FP1IO7 VSS P WAIT# TEA# FP1IO19 FP1IO14 FP1IO20 VSS FP1IO4 FP1IO2 R IRQ RESET# FP1IO17 FP1IO22 FP1IO13 FP1IO12 FP1IO5 T VSS FP1IO18 FP1IO11 PIO1VDD FP1IO23 PIO1VDD 1 2 3 4 5 6 Hardware Functional Specification Rev. 1.7 MEMBA0 MEMDQM3 MEMDQM2 MEMDQM1 MEMDQM0 MEMRAS# MEMCAS# H MEMCS# MEMCKE J CNF1 CNF2 K TDI L TCK TMS FP2IO13 SPIDIO VSS FP2IO6 PIO2VDD FP2IO17 FP2IO14 FP2IO8 WSIO SDO SCKIO MCLKO FP2IO24 FP2IO19 FP2IO15 FP2IO9 FP2IO7 FP2IO0 FP2IO2 FP2IO1 P FP1IO3 FP2IO25 FP2IO20 PIO2VDD FP2IO12 VSS FP2IO4 VP2IO3 PIO2VDD R FP1IO6 PIO1VDD FP2IO27 FP2IO23 FP2IO16 COREVDD FP2IO11 PIO2VDD FP2IO5 VSS T 7 8 9 10 11 12 13 14 15 16 EPSON TRST VSS SPICLK VSS TESTEN TDO PWM2 PWM1 IOVDD SPICS# COREVDD M 21 N Chapter 5 Pins S1D13515/S2D13515 5.3 Pin Descriptions Key: Pin Types I O IO P = = = = RESET# States H = L = Z = 1 = 0 = # = Input Output Bi-Directional (Input/Output) Power pin High level output Low level output High Impedance (Hi-Z) Pull-up resistor on input Pull-down resistor on input Active low level Table 5-2: Cell Descriptions Cell Description ILTR Low voltage transparent input OLTR Low voltage transparent output IC LVCMOS input ICS LVCMOS schmitt input ICD1T LVCMOS input with pull-down resistor (50kΩ@3.3V) with Test Function ICSU1T LVCMOS schmitt input with pull-up resistor (50kΩ@3.3V) with Test Function ICSU2T LVCMOS schmitt input with pull-up resistor (100kΩ@3.3V) with Test Function ICSD1T LVCMOS schmitt input with pull-down resistor (50kΩ@3.3V) with Test Function IOC2P1T Low noise LVCMOS IO buffer (2mA/4mA@3.3V) with pull-up resistor (50kΩ@3.3V) with Test Function IOC2P2T Low noise LVCMOS IO buffer (2mA/4mA@3.3V) with pull-up resistor (100kΩ@3.3V) with Test Function IOC2D1T Low noise LVCMOS IO buffer (2mA/4mA@3.3V) with pull-down resistor (50kΩ@3.3V) with Test Function IOC2D2T Low noise LVCMOS IO buffer (2mA/4mA@3.3V) with pull-down resistor (100kΩ@3.3V) with Test Function IOCS2D1T Low noise LVCMOS schmitt IO buffer (2mA/4mA@3.3V) with pull-down resistor (50kΩ@3.3V) with Test Function OLT2T Low noise 3-state Output buffer (2mA/4mA@3.3V) with Test Function OLT3 Low noise 3-state Output buffer (8mA@ 3.3V) OLT3T Low noise 3-state Output buffer (8mA@ 3.3V) with Test Function P Power 22 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins 5.3.1 Host Interface Many of the host interface pins have different functions depending on the host bus interface that is selected. For a summary of the possible host bus interface configurations and associated pin mapping details, see Section 5.4, “Configuration Pins” on page 32 and Section 5.5, “Host Interface Pin Mapping” on page 34. To determine the RESET# state for each pin, refer to Section 11.1, “Hard Reset State” on page 433. Table 5-3: Host Interface Pin Descriptions Pin Name AB[20:19] AB18 AB[17:8] AB7 AB6 AB[5:0] DB[15:10] Type IO QFP Pin# 4, 5 I 6 IO 7, 8, 9, 10, 11, 12, 13, 17, 18, 19 PBGA Pin# C1, D4 D3 Cell Power Description These input/output pins are the host address bus pins 20-19. For a summary of which pins are used for each IOCS2D1T HIOVDD host bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. ICSD1T This input pin is the host address pin 18. For a summary of which pins are used for each host bus HIOVDD interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. E5, D2, D1, These input/output pins are the host address bus pins E4, E3, F6, 17-6. For a summary of which pins are used for each IOCS2D1T HIOVDD F5, F3, G7, host bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. G6 F2 This input/output pin is the host address bus pin 7. For a summary of which pins are used for each host IOCS2D1T HIOVDD bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. 21 F1 This input/output pin is the host address bus pin 6. For a summary of which pins are used for each host IOCS2D1T HIOVDD bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. I 22-27 G5, G4, G3, G2, H7, H6 IO 30, 31, 32, 33, 34, 35, 36 H2, H4, H3, H1, J7, J6 These input/output pins are the host data bus pins 1510. For a summary of which pins are used for each IOC2D1T HIOVDD host bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. IO IO 20 ICSD1T These input pins are the host address bus pins 5-0. For a summary of which pins are used for each host HIOVDD bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. IO 36 J3 This input/output pin is the host data bus pin 9. For a summary of which pins are used for each host bus IOC2D1T HIOVDD interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. DB[8:0] IO 37, 41, 42, 43, 44, 45, 46, 47, 48 J2, J5, K5, K4, K3, K1, K2, K6, L1 These input/output pins are the host data bus pins 80. For a summary of which pins are used for each IOC2D1T HIOVDD host bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. CS# I 52 L3 DB9 M/R# IO 53 Hardware Functional Specification Rev. 1.7 M1 ICD1T HIOVDD This input pin is Chip Select. This input/output pin has multiple functions. For a summary of the pin functions for each host bus IOCS2D1T HIOVDD interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. EPSON 23 Chapter 5 Pins S1D13515/S2D13515 Table 5-3: Host Interface Pin Descriptions Pin Name RD# RD/WR# BE0# BE1# BS# Type I I I IO IO QFP Pin# 54 55 56 57 58 PBGA Pin# M2 M3 M4 Cell Power Description ICD1T This input pin has multiple functions. For a summary of the pin functions for each host bus interface HIOVDD configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. ICD1T This input pin has multiple functions. For a summary of the pin functions for each host bus interface HIOVDD configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. ICD1T This input pin has multiple functions. For a summary of the pin functions for each host bus interface HIOVDD configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. N1 This input/output pin has multiple functions. For the Intel 80 Type 2 Indirect 8-bit Host Interface, this pin must be connected to HIOVDD. IOC2D1T HIOVDD For a summary of the pin functions for each host bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. M5 This input/output pin has multiple functions. For a summary of the pin functions for each host bus IOC2P2T HIOVDD interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. This input pin is Burst Transfer for the MPC555 and TI TMS470 Host interfaces and is used for burst support. BURST# I 59 N2 IC HIOVDD For all other host bus interfaces, it is used in combination with the CNF[2:1] pins for selecting the host bus interface. For a summary of all possible host bus interfaces, see Section 5.4, “Configuration Pins” on page 32. This input pin is used for the MPC555 and TI TMS470 Host interfaces and indicates a burst transfer is in progress. BDIP# 24 I 60 N3 IC HIOVDD For all other host bus interfaces, it is used in combination with the CNF[2:1] pins for selecting the host bus interface. For a summary of all possible host bus interfaces, see Section 5.4, “Configuration Pins” on page 32. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins Table 5-3: Host Interface Pin Descriptions Pin Name TEA# Type IO QFP Pin# PBGA Pin# 61 P2 Cell Power Description This input/output pin is Transfer Error Acknowledge and is used for burst support for the MPC555 and TI TMS470 Host interfaces. This signal indicates that a bus error occurred in the current transaction. The MCU asserts this signal when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. The assertion of TEA# causes the termination of the current bus cycle, regardless of the state of TEA#. An external pull-up device is required IOC2D1T HIOVDD to negate TEA# quickly, before a second error is detected. That is, the pin must be pulled up within one clock cycle of the time it was tri-stated by the MPC555 / TI TMS470. For all other host bus interfaces, it is used in combination with the CNF[2:1] pins for selecting the host bus interface. For a summary of all possible host bus interfaces, see Section 5.4, “Configuration Pins” on page 32. WAIT# IO 62 P1 During a data transfer, this output pin is driven active to force the system to insert wait states. It is driven inactive to indicate the completion of a data transfer. WAIT# is released to a high impedance state after the IOC2P2T HIOVDD data transfer is complete. For a summary of the pin functions for each host bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. BUSCLK I 39 J1 ICD1T This input clock is typically used for an external clock source for the Host CPU bus interface. For a HIOVDD summary of the pin functions for each host bus interface configuration, see Section 5.5, “Host Interface Pin Mapping” on page 34. IRQ O 63 R1 OLT2T HIOVDD Hardware Functional Specification Rev. 1.7 EPSON This output pin is the IRQ output from the S1D13515/S2D13515. 25 Chapter 5 Pins S1D13515/S2D13515 5.3.2 LCD Interface The LCD interface consists of LCD1 and LCD2. LCD1 uses the FP1IO[23:0] pins and LCD2 uses the FP2IO[27:0] pins. Alternately, LCD1 can be used as a Camera2 or RGB stream input. For detailed pin mapping, see Section 5.6, “LCD / Camera2 Pin Mapping” on page 39. To determine the RESET# state for each pin, refer to Section 11.1, “Hard Reset State” on page 433. Table 5-4: LCD Interface Pin Descriptions Pin Name Type QFP Pin# PBGA Pin# Cell Power Description These input/output pins may be used for one of the following options. Note that if an EID Double Screen panel with TCON enabled is used on FP2, the available options may differ. FP1IO[23:0] IO 79, 73, 74, 75, 66, 67, 68, 76, 77, 69, 78, 83, 70, 84, 85, 86, 87, 88, 89, 90, 93, 94, 95, 96 T5, R4, N5, P5, P3, T2, R3, L6, M6, P4, R5, R6, IOCS2D1T PIO1VDD T3, K7, L7, M7, N7, T7, R7, P7, R8, P8, M8, L8 • 18-bit TFT panel • 16-bit TFT panel w/ serial command interface • 15-bit TFT panel (when EID Double Screen with TCON enabled is on FP2) • 12-bit TFT panel w/ serial command interface (when EID Double Screen with TCON enabled on FP2) • 18-bit RGB input stream • 8-bit Camera2 input and 5x5 keypad/GPIOs • 15-bit RGB input stream (when EID Double Screen with TCON enabled is on FP2) • 8-bit Camera2 input and 3x3 keypad/GPIOs (when EID Double Screen with TCON enabled is on FP2) Note that for some options, unused pins may be available as GPIO pins. For detailed pin mapping for each option, see Section 5.6, “LCD / Camera2 Pin Mapping” on page 39. FP2IO[27:24] O 97, 98, 99, 100 T9, K8, R9, P9 FP2IO[23:18] IO 103, 104, 105, 106, 107, 108 T10, M9, L9, R10, P10, IOCS2D1T PIO2VDD K9 FP2IO17 IO 109 N10 O 110, 114, 115, 116, 117, 118, 119, 120, 123, 124, 125, 126, 127, 128, 131, 132, 133 T11, P11, N11, L10, R12, T13, K10, P12, N12, P13, M11, T15, R14, R15, P15, P16, P14 FP2IO[16:0] 26 OLT2T PIO2VDD These input/output pins may be used for one of the following options. IOC2P1T PIO2VDD OLT2T PIO2VDD EPSON • • • • 24-bit TFT panel 18-bit TFT panel w/ serial command interface 18-bit TFT panel EID 18-bit Double Screen panel with TCON disabled • EID 18-bit Double Screen panel with TCON enabled • Sharp 18-bit DualView panel Note that for some options, unused pins may be available as GPIO pins. For detailed pin mapping for each option, see Section 5.6, “LCD / Camera2 Pin Mapping” on page 39. Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins 5.3.3 SDRAM Interface To determine the RESET# state for each pin, refer to Section 11.1, “Hard Reset State” on page 433. Table 5-5: SDRAM Interface Pin Descriptions Type QFP Pin# PBGA Pin# Cell Power MEMA[12:0] O 169, 170, 171, 172, 173, 221, 222, 223, 224, 225, 226, 227, 228 G16, H10, G15, G14, F15, E9, A10, D9, G8, C9, F8, B9, A9 OLT2T SDVDD These output pins are used for SDRAM bank row/column address mapping. MEMBA[1:0] O 167, 168 H12, H11 OLT2T SDVDD These output pins are used to select the SDRAM bank address. Pin Name Description MEMCS# O 161 J15 OLT2T SDVDD This output pin is the chip select for the SDRAM. MEMRAS# O 162 H15 OLT2T SDVDD This output pin is the RAS# for the SDRAM. MEMCAS# O 163 H16 OLT2T SDVDD This output pin is the CAS# for the SDRAM. MEMWE# O 166 H13 OLT2T SDVDD This output pin is the write enable for the SDRAM. IO 176, 178, 182, 184, 186, 190, 192, 194, 198, 200, 202, 204, 211, 213, 215, 217 G12, F14, F12, E14, D15, C15, B15, D13, A14, C13, A13, D12, F10, B11, F9, D10 MEMDQ[15:0] IO 177, 179, 183, 185, 189, 191, 193, 197, 199, 201, 203, 210, 212, 214, 216, 218 MEMDQM[3:2] O MEMDQM[1:0] IOC2D2T These input/output pins are the upper data bus used for x32 SDRAM configurations. For x16 SDVDD SDRAM configurations, these pins must be left unconnected since they have internal pull-down resistors. G11, F13, G10, D16, C16, B16, C14, B14, E12, B13, F11, C11, G9, E10, A11, C10 IOC2D2T These input/output pins are the data bus for the SDRAM. They are used for both x16 and x32 SDVDD configurations. These pins have internal pull-down resistors. 156, 157 J11, J12 OLT2T These output pins are the upper byte enables used SDVDD for x32 SDRAM configurations. For x16 SDRAM configurations, they must be left unconnected. O 158, 159 J13, J14 OLT2T These output pins are the byte enables for the SDVDD SDRAM. They are used for both x16 and x32 configurations. MEMCLK O 208 A12 OLT3T SDVDD This output pin is the clock for the SDRAM. MEMCKE O 160 J16 OLT2T SDVDD This output pin is the clock enable for the SDRAM. MEMDQ[31:16] Hardware Functional Specification Rev. 1.7 EPSON 27 Chapter 5 Pins S1D13515/S2D13515 5.3.4 Camera / I2C Interface To determine the RESET# state for each pin, refer to Section 11.1, “Hard Reset State” on page 433. Table 5-6: Camera / I2C Interface Pin Descriptions Type QFP Pin# PBGA Pin# Cell Power CM1DAT[7:0] I 235, 236, 237, 242, 243, 244, 245, 246 E6, D7, A8, D5, C6, C5, C4, C3 ICD1T CM1VDD These input pins are the Camera1 interface data pins. CM1CLKIN I 240 B7 ICD1T CM1VDD This pin is the camera clock input for the Camera1 interface. CM1CLKOUT O 238 A7 OLT2T CM1VDD This pin is the master clock output for the Camera1 interface. CM1HREF I 233 F7 ICD1T CM1VDD This input pin is the horizontal sync signal for the Camera1 interface. CM1VREF I 232 B8 ICD1T CM1VDD This input pin is the vertical sync signal for the Camera1 interface. CM1FIELD I 231 C8 ICD1T CM1VDD This input pin identifies the FIELD for interlaced input on the Camera1 interface. SCL IO 229 E8 This input/output pin is the I2C bus serial clock. If IOC2P2T CM1VDD the I2C interface is not used, this pin should be left unconnected. SDA IO 230 D8 This input/output pin is the I2C bus serial data. If the IOC2P2T CM1VDD I2C interface is not used, this pin should be left unconnected. Pin Name Description 5.3.5 SPI Flash Interface To determine the RESET# state for each pin, refer to Section 11.1, “Hard Reset State” on page 433. Table 5-7: SPI Flash Interface Pin Descriptions 28 Pin Name Type QFP Pin# PBGA Pin# Cell Power SPICS# O 143 M15 OLT2T IOVDD This output pin is chip select for the SPI Flash Memory interface. SPICLK O 144 L12 OLT2T IOVDD This output pin is the clock for the SPI Flash Memory interface. SPIDIO IO 145 L11 IOC2D2T Description This input/output is the data pin for the SPI Flash IOVDD Memory interface. If the SPI Flash interface is not used, this pin should be left unconnected. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins 5.3.6 I2S Interface To determine the RESET# state for each pin, refer to Section 11.1, “Hard Reset State” on page 433. Table 5-8: I2S Interface Pin Descriptions Pin Name WSIO Type IO QFP Pin# PBGA Pin# 134 N13 Cell Power Description IOC2P2T This pin is the serial word clock input/output for the I2S interface. This pin is configured based on the IOVDD setting of the I2S Data Clock Source bit, REG[0100h] bit 0. If the I2S interface is not used, this pin should be left unconnected. This pin is the serial bit clock input/output for the I2S interface. This pin is configured based on the setting IOVDD of the I2S Data Clock Source bit, REG[0100h] bit 0. If the I2S interface is not used, this pin should be left unconnected. SCKIO IO 136 N15 IOC2P2T SDO O 135 N14 OLT2T IOVDD This pin is the serial data output for the I2S interface. MCLKO O 137 N16 OLT2T IOVDD This pin is the bus output clock to the DAC for the I2S interface. 5.3.7 Miscellaneous To determine the RESET# state for each pin, refer to Section 11.1, “Hard Reset State” on page 433. Table 5-9: Miscellaneous Pin Descriptions Pin Name CNF[2:1] Type I QFP Pin# 153, 154 PBGA Pin# K16, K15 Cell IC Power Description IOVDD These input pins are used in combination with other pins to select the host bus interface. For a summary of all possible host bus interfaces, see Section 5.4, “Configuration Pins” on page 32. IOVDD This input pin is used to select the source for Input Clock 1 (see Chapter 9, “Clocks” on page 128). When CNF0=0, CLKI is the source for Input Clock 1. When CNF0=1, OSCI is the source for Input Clock 1. CNF0 I 155 J10 IC OSCI I 249 A5 ILTR Crystal input. If an external oscillator circuit is used, OSCVDD connect it to this pin. For details on the clock structure, see Chapter 9, “Clocks” on page 128. Crystal output. If an external oscillator circuit is used, this pin must be left unconnected. For details OSCVDD on the clock structure, see Chapter 9, “Clocks” on page 128. OSCO O 248 A6 OLTR CLKI I 2 B1 IC HIOVDD Clock input. For details on the clock structure, see Chapter 9, “Clocks” on page 128. TESTEN I 146 L14 ICSD1T IOVDD This input pin is for production test only and must be connected to VSS for normal operation. Hardware Functional Specification Rev. 1.7 EPSON 29 Chapter 5 Pins S1D13515/S2D13515 Table 5-9: Miscellaneous Pin Descriptions Pin Name Type QFP Pin# PBGA Pin# Cell Power Description VCP1 O 255 A2 OLTR PLL1VDD This output pin is for production test only and must be left unconnected for normal operation. VCP2 O 252 A4 OLTR PLL2VDD This output pin is for production test only and must be left unconnected for normal operation. RESET# I 65 R2 ICS PWM2 O 138 M12 OLT2T IOVDD This output pin is for PWM output. PWM1 O 139 M13 OLT2T IOVDD This output pin is for PWM output. TCK I 148 K11 ICSU1T IOVDD This input pin is a JTAG interface pin used for Boundary Scan tests. For normal operations, this pin must be left unconnected. TMS I 150 K12 ICSU1T IOVDD This input pin is a JTAG interface pin used for Boundary Scan tests. For normal operations, this pin must be left unconnected. TDI I 149 L16 ICSU1T IOVDD This input pin is a JTAG interface pin used for Boundary Scan tests. For normal operations, this pin must be left unconnected. TDO O 147 L15 OLT3 IOVDD This output pin is a JTAG interface pin used for Boundary Scan tests. For normal operations, this pin must be left unconnected. IOVDD This input pin is a JTAG interface pin used for Boundary Scan tests. For normal operations, this pin must be left unconnected. For normal operations, this pin must be connected to RESET#. TRST 30 This active low input sets all internal registers to their default states and forces all signals to their HIOVDD inactive states. For RESET# timing, see Section 7.3, “RESET# Timing” on page 49. I 151 K13 ICSU2T EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins 5.3.8 Power And Ground Table 5-10: Power And Ground Pin Descriptions Pin Name Type QFP Pin# PBGA Pin# Cell Description COREVDD P 16, 50, 80, C12, D6, E1, 113, 142, E16, L2, 181, 206, M16, N6, 241 T12 HIOVDD P 14, 28, 40, 51 E2, G1, J4, L5 P Power supply for the Host interface PIO1VDD P 72, 82, 92 T4, T6, T8 P Power supply for the Panel 1 interface PIO2VDD P 101, 111, 121, 129 N9, R11, R16, T14 P Power supply for the Panel 2 interface SDVDD P 165, 175, 188, 195, 205, 220 A15, B10, D14, E11, F16, H14 P Power supply for the SDRAM interface CM1VDD P 234 E7 P Power supply for the Camera1 interface IOVDD P 140 M14 P Power supply for the SPI / I2S interfaces and some miscellaneous pins P Common Ground 1, 3, 15, 29, A1, A16, 38, 49, 64, B12, C2, C7, 71, 81, 91, D11, E13, 102, 112, E15, F4, 122, 130, G13, H5, 141, 152, H8, H9, J8, 164, 174, J9, K14, L4, 180, 187, L13, M10, 196, 207, N4, N8, P6, 209, 219, R13, T1, 239 T16 P Core power supply VSS P OSCVDD P 250 B5 P Power supply for OSC OSCVDD must be the same voltage as COREVDD. OSCVSS P 247 B6 P Ground for OSC PLL1VDD P 256 B2 P Power supply for PLL1 PLL1VSS P 254 B3 P Ground for PLL1 PLL2VDD P 253 A3 P Power supply for PLL2 PLL2VSS P 251 B4 P Ground for PLL2 Hardware Functional Specification Rev. 1.7 EPSON 31 Chapter 5 Pins S1D13515/S2D13515 5.4 Configuration Pins The S1D13515/S2D13515 has three dedicated configuration pins, CNF[2:0], which should be pulled high or low based on the following table. Table 5-11: Configuration Pin Summary CNF[2:0] CNF2 CNF1 CNF0 1 (connected to VDD) 0 (connected to VSS) CNF[2:1] are used in combination with other host interface pins to select the host bus interface. For a summary of the possible host bus interfaces, see Section Table 5-12 :, “Host Interface Configuration Summary” on page 33. OSCI is the source for Input Clock 1 CLKI is the source for Input Clock 1 The host bus interface is selected using a combination of the CNF[2:1] pins and host interface pins that are normally unused for the selected host bus interface. 32 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins Table 5-12 : Host Interface Configuration Summary MPC555/TI CNF1 8-bit/16-bit Direct/Indirect CNF2 Parallel Type [2:0] Serial Type CNF3 CNF4 CNF5 CNF6 CNF7 Host Interface 0 — 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB3) — Indirect, 8-bit, Intel80 Type1 0 — 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB3) — Indirect, 8-bit, Intel80 Type2 0 — 0 0 (TEA#) 0 (BDIP#) 1 (BURST#) 0 (AB3) — Reserved 0 — 0 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 0 (AB4) Reserved 0 — 0 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 1 (AB4) Reserved 0 — 0 0 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB3) — Indirect, 8-bit, NEC V850 Type1 0 — 0 0 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB3) — Indirect, 8-bit, NEC V850 Type2 0 — 0 0 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB3) — Indirect, 8-bit, Renesas SH4 0 — 1 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB3) — Indirect, 16-bit, Intel80 Type1 0 — 1 0 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB3) — Indirect, 16-bit, Intel80 Type2 0 — 1 0 (TEA#) 0 (BDIP#) 1 (BURST#) 0 (AB3) — Reserved 0 — 1 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 0 (AB4) SPI (2-stream) 0 — 1 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 1 (AB4) Reserved 0 — 1 0 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB3) — Indirect, 16-bit, NEC V850 Type1 0 — 1 0 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB3) — Indirect, 16-bit, NEC V850 Type2 0 — 1 0 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB3) — Indirect, 16-bit, Renesas SH4 0 — 0 1 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (BE1#) — Direct, 8-bit, Intel80 Type1 0 — 0 1 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (BE1#) — Direct, 8-bit, Intel80 Type2 0 — 0 1 (TEA#) 0 (BDIP#) 1 (BURST#) 0 (BE1#) — Reserved 0 — 0 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (BE1#) 0 (AB4) Reserved 0 — 0 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (BE1#) 1 (AB4) Reserved 0 — 0 1 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (BE1#) — Direct, 8-bit, NEC V850 Type1 0 — 0 1 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (BE1#) — Direct, 8-bit, NEC V850 Type2 0 — 0 1 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (BE1#) — Direct, 8-bit, Renesas SH4 0 — 1 1 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB0) — Direct, 16-bit, Intel80 Type1 0 — 1 1 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB0) — Direct, 16-bit, Intel80 Type2 0 — 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 0 (AB0) — Direct, 16-bit, Marvell PXA3xx 0 — 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB0) 0 (AB4) SPI 0 — 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB0) 1 (AB4) I2C 0 — 1 1 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB0) — Direct, 16-bit, NEC V850 Type1 0 — 1 1 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB0) — Direct, 16-bit, NEC V850 Type2 0 — 1 1 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB0) — Direct, 16-bit, Renesas SH4 1 0 — 0 (AB0) — — — — Indirect, 16-bit, TI TMS470 1 0 — 1 (AB0) — — — — Direct, 16-bit, TI TMS470 1 1 — 0 (BE1#) — — — — Indirect, 16-bit, MPC555 (Little Endian only) 1 1 — 1 (BE1#) — — — — Direct, 16-bit, MPC555 (Little Endian only) Hardware Functional Specification Rev. 1.7 EPSON 33 Chapter 5 Pins S1D13515/S2D13515 5.5 Host Interface Pin Mapping Table 5-13 : Host Interface Pin Mapping 1 S1D13515/ S2D13515 Pin NEC V850 Type1 8-bit Indirect Intel80 Type1 Intel80 Type2 8-bit Indirect 8-bit Indirect NEC V850 Type2 8-bit Indirect Renesas SH4 Intel80 Type1 Intel80 Type2 8-bit Indirect 16-bit Indirect 16-bit Indirect DB15 D15 D15 DB14 D14 D14 DB13 D13 D13 DB12 D12 D12 DB11 D11 D11 DB10 D10 D10 DB9 D9 D9 DB8 D8 D8 DB7 D7 D7 D7 D7 D7 D7 D7 DB6 D6 D6 D6 D6 D6 D6 D6 DB5 D5 D5 D5 D5 D5 D5 D5 DB4 D4 D4 D4 D4 D4 D4 D4 DB3 D3 D3 D3 D3 D3 D3 D3 DB2 D2 D2 D2 D2 D2 D2 D2 DB1 D1 D1 D1 D1 D1 D1 D1 DB0 D0 D0 D0 D0 D0 D0 D0 M/R# GPIO9/KPR0 GPIO9/KPR0 GPIO9/KPR0 GPIO9/KPR0 GPIO9/KPR0 GPIO9/KPR0 GPIO9/KPR0 AB20 GPIO10/KPR1 GPIO10/KPR1 GPIO10/KPR1 GPIO10/KPR1 GPIO10/KPR1 GPIO10/KPR1 GPIO10/KPR1 AB19 GPIO12/KPR2 GPIO12/KPR2 GPIO12/KPR2 GPIO12/KPR2 GPIO12/KPR2 GPIO12/KPR2 GPIO12/KPR2 AB18 KPR3 KPR3 KPR3 KPR3 KPR3 KPR3 KPR3 AB17 GPIO8/KPR4 GPIO8/KPR4 GPIO8/KPR4 GPIO8/KPR4 GPIO8/KPR4 GPIO8/KPR4 GPIO8/KPR4 AB16 GPIO13/KPC0 GPIO13/KPC0 GPIO13/KPC0 GPIO13/KPC0 GPIO13/KPC0 GPIO13/KPC0 GPIO13/KPC0 AB15 GPIO14/KPC1 GPIO14/KPC1 GPIO14/KPC1 GPIO14/KPC1 GPIO14/KPC1 GPIO14/KPC1 GPIO14/KPC1 AB14 GPIO15/KPC2 GPIO15/KPC2 GPIO15/KPC2 GPIO15/KPC2 GPIO15/KPC2 GPIO15/KPC2 GPIO15/KPC2 AB13 GPIO11/KPC3 GPIO11/KPC3 GPIO11/KPC3 GPIO11/KPC3 GPIO11/KPC3 GPIO11/KPC3 GPIO11/KPC3 AB12 KPC4 KPC4 KPC4 KPC4 KPC4 KPC4 KPC4 AB11 PEDST0 PEDST0 PEDST0 PEDST0 PEDST0 PEDST0 PEDST0 AB10 PEDST1 PEDST1 PEDST1 PEDST1 PEDST1 PEDST1 PEDST1 AB9 PEDST2 PEDST2 PEDST2 PEDST2 PEDST2 PEDST2 PEDST2 AB8 PEDCLK PEDCLK PEDCLK PEDCLK PEDCLK PEDCLK PEDCLK AB7 PEDSIO PEDSIO PEDSIO PEDSIO PEDSIO PEDSIO PEDSIO AB6 PEDCPCO PEDCPCO PEDCPCO PEDCPCO PEDCPCO PEDCPCO PEDCPCO 0 (as CNF6) 1 (as CNF6) 0 (as CNF6) 1 (as CNF6) 0 (as CNF6) 0 (as CNF6) 1 (as CNF6) A2 A2 A1 A1 AB5 AB4 AB3 AB2 AB1 A1 A1 A1 A1 A1 AB0 A0 A0 A0 A0 A0 CLK CLK CLK BUSCLK BS# BS# WAIT# WAIT# WAIT# WAIT# WAIT# RDY# WAIT# WAIT# RD# RD# RD# DSTB# RD# RD# RD# RD# RD/WR# WE# WR# WE# CS# CS# CS# CS# CS# 0 WE# BE1# R/W# CS# CS# BE0# 0 WE# BURST# 0 (as CNF5) 0 (as CNF5) WE# 0 (as CNF5) 0 (as CNF5) WR# 1 (as CNF5) 0 (as CNF5) 0 (as CNF5) BDIP# 0 (as CNF4) 0 (as CNF4) 1 (as CNF4) 1 (as CNF4) 1 (as CNF4) 0 (as CNF4) 0 (as CNF4) TEA# 0 (as CNF3) 0 (as CNF3) 0 (as CNF3) 0 (as CNF3) 0 (as CNF3) 0 (as CNF3) 0 (as CNF3) CNF2 0 0 0 0 0 1 1 CNF1 0 0 0 0 0 0 0 = These pins select the interface. 34 CS# 1 = These pins are unused for the interface. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins Table 5-14 : Host Interface Pin Mapping 2 S1D13515/ S2D13515 Pin SPI (2-stream) NEC V850 Type1 16-bit Indirect NEC V850 Type2 16-bit Indirect DB15 C1RIN5 D15 D15 D15 DB14 C1GIN7 D14 D14 D14 DB13 C1GIN6 D13 D13 D13 PEDST0 PEDST0 PEDST0 DB12 C1GIN5 D12 D12 D12 PEDST1 PEDST1 PEDST1 DB11 C1BIN7 D11 D11 D11 PEDST2 PEDST2 PEDST2 DB10 C1BIN6 D10 D10 D10 PEDCLK PEDCLK PEDCLK DB9 C1BIN5 D9 D9 D9 PEDSIO PEDSIO PEDSIO DB8 C1RIN4 D8 D8 D8 PEDCPCO PEDCPCO PEDCPCO DB7 C1RIN3 D7 D7 D7 D7 D7 D7 DB6 C1RIN2 D6 D6 D6 D6 D6 D6 DB5 C1GIN4 D5 D5 D5 D5 D5 D5 DB4 C1GIN3 D4 D4 D4 D4 D4 D4 DB3 C1GIN2 D3 D3 D3 D3 D3 D3 DB2 C1BIN4 D2 D2 D2 D2 D2 D2 DB1 C1BIN3 D1 D1 D1 D1 D1 D1 DB0 C1BIN2 D0 D0 D0 D0 D0 D0 M/R# GPIO9/KPR0 GPIO9/KPR0 GPIO9/KPR0 GPIO9/KPR0 M/R# M/R# M/R# AB20 GPIO10/KPR1 GPIO10/KPR1 GPIO10/KPR1 GPIO10/KPR1 A20 A20 A20 AB19 GPIO12/KPR2 GPIO12/KPR2 GPIO12/KPR2 GPIO12/KPR2 A19 A19 A19 Renesas SH4 Intel80 Type1 Intel80 Type2 16-bit Indirect 8-bit Direct 8-bit Direct NEC V850 Type1 8-bit Direct AB18 KPR3 KPR3 KPR3 KPR3 A18 A18 A18 AB17 GPIO8/KPR4 GPIO8/KPR4 GPIO8/KPR4 GPIO8/KPR4 A17 A17 A17 AB16 GPIO13/KPC0 GPIO13/KPC0 GPIO13/KPC0 GPIO13/KPC0 A16 A16 A16 AB15 GPIO14/KPC1 GPIO14/KPC1 GPIO14/KPC1 GPIO14/KPC1 A15 A15 A15 AB14 GPIO15/KPC2 GPIO15/KPC2 GPIO15/KPC2 GPIO15/KPC2 A14 A14 A14 AB13 GPIO11/KPC3 GPIO11/KPC3 GPIO11/KPC3 GPIO11/KPC3 A13 A13 A13 AB12 KPC4 KPC4 KPC4 KPC4 A12 A12 A12 AB11 PEDST0 PEDST0 PEDST0 PEDST0 A11 A11 A11 AB10 PEDST1 PEDST1 PEDST1 PEDST1 A10 A10 A10 AB9 PEDST2 PEDST2 PEDST2 PEDST2 A9 A9 A9 AB8 PEDCLK PEDCLK PEDCLK PEDCLK A8 A8 A8 AB7 PEDSIO PEDSIO PEDSIO PEDSIO A7 A7 A7 AB6 PEDCPCO PEDCPCO PEDCPCO PEDCPCO A6 A6 A6 AB5 SPICLKSEL A5 A5 A5 AB4 0 (as CNF7) A4 A4 A4 AB3 1 (as CNF6) 0 (as CNF6) 1 (as CNF6) 0 (as CNF6) A3 A3 A3 AB2 C1HSIN A2 A2 A2 A2 A2 A2 AB1 C1VSIN A1 A1 A1 A1 A1 A1 AB0 C1DEIN A0 A0 BUSCLK CLK CLK CLK A0 CLK BS# C1PCLKIN WAIT# HSDO WAIT# WAIT# RDY# BS# WAIT# WAIT# WAIT# RD# C1RIN7 DSTB# RD# RD# RD# RD# DSTB# RD/WR# HSDI R/W# CS# HSCS# CS# CS# CS# CS# CS# CS# BE1# C1RIN6 0 WR# WR# 0 (as CNF6) 1 (as CNF6) 0 (as CNF6) WE# R/W# BE0# HSCK 0 WR# WR# BURST# 1 (as CNF5) 0 (as CNF5) 0 (as CNF5) 1 (as CNF5) 0 (as CNF5) 0 (as CNF5) 0 (as CNF5) BDIP# 0 (as CNF4) 1 (as CNF4) 1 (as CNF4) 1 (as CNF4) 0 (as CNF4) 0 (as CNF4) 1 (as CNF4) TEA# 0 (as CNF3) 0 (as CNF3) 0 (as CNF3) 0 (as CNF3) 1 (as CNF3) 1 (as CNF3) 1 (as CNF3) CNF2 1 1 1 1 0 0 0 CNF1 0 0 0 0 0 0 0 = These pins select the interface. Hardware Functional Specification Rev. 1.7 WE# = These pins are unused for the interface. EPSON 35 Chapter 5 Pins S1D13515/S2D13515 Table 5-15 : Host Interface Pin Mapping 3 S1D13515/ S2D13515 Pin NEC V850 Type2 8-bit Direct Renesas SH4 Intel80 Type1 Intel80 Type2 8-bit Direct 16-bit Direct 16-bit Direct Marvell PXA3xx 16-bit Direct DB15 D15 D15 DF_IO15 DB14 D14 D14 DF_IO14 I2C DB13 PEDST0 PEDST0 D13 D13 DF_IO13 DB12 PEDST1 PEDST1 D12 D12 DF_IO12 DB11 PEDST2 PEDST2 D11 D11 DF_IO11 DB10 PEDCLK PEDCLK D10 D10 DF_IO10 DB9 PEDSIO PEDSIO D9 D9 DF_IO9 DB8 PEDCPCO PEDCPCO D8 D8 DF_IO8 DB7 D7 D7 D7 D7 DF_IO7 DB6 D6 D6 D6 D6 DF_IO6 SLADDR6 DB5 D5 D5 D5 D5 DF_IO5 SLADDR5 DB4 D4 D4 D4 D4 DF_IO4 SLADDR4 DB3 D3 D3 D3 D3 DF_IO3 SLADDR3 DB2 D2 D2 D2 D2 DF_IO2 SLADDR2 DB1 D1 D1 D1 D1 DF_IO1 SLADDR1 DB0 D0 D0 D0 D0 DF_IO0 M/R# M/R# M/R# M/R# M/R# GPIO9/KPR0 AB20 A20 A20 A20 A20 GPIO10/KPR1 GPIO10/KPR1 GPIO10/KPR1 AB19 A19 A19 A19 A19 GPIO12/KPR2 GPIO12/KPR2 GPIO12/KPR2 AB18 A18 A18 A18 A18 KPR3 KPR3 KPR3 AB17 A17 A17 A17 A17 GPIO8/KPR4 GPIO8/KPR4 GPIO8/KPR4 AB16 A16 A16 A16 A16 GPIO13/KPC0 GPIO13/KPC0 GPIO13/KPC0 AB15 A15 A15 A15 A15 GPIO14/KPC1 GPIO14/KPC1 GPIO14/KPC1 AB14 A14 A14 A14 A14 GPIO15/KPC2 GPIO15/KPC2 GPIO15/KPC2 AB13 A13 A13 A13 A13 GPIO11/KPC3 GPIO11/KPC3 GPIO11/KPC3 AB12 A12 A12 A12 A12 KPC4 KPC4 KPC4 AB11 A11 A11 A11 A11 PEDST0 PEDST0 PEDST0 AB10 A10 A10 A10 A10 PEDST1 PEDST1 PEDST1 AB9 A9 A9 A9 A9 PEDST2 PEDST2 PEDST2 AB8 A8 A8 A8 A8 PEDCLK PEDCLK PEDCLK AB7 A7 A7 A7 A7 PEDSIO PEDSIO PEDSIO AB6 A6 A6 A6 A6 nLUA PEDCPCO PEDCPCO AB5 A5 A5 A5 A5 nLLA SPICLKSEL I2CCLKSEL AB4 A4 A4 A4 A4 DF_ADDR3 0 (as CNF7) 1 (as CNF7) AB3 A3 A3 A3 A3 DF_ADDR2 AB2 A2 A2 A2 A2 DF_ADDR1 AB1 A1 A1 A1 A1 DF_ADDR0 AB0 A0 A0 0 (as CNF6) 1 (as CNF6) 0 (as CNF6) 1 (as CNF6) 1 (as CNF6) BUSCLK CLK CLK WAIT# WAIT# RDY# WAIT# WAIT# RD# RD# RD# BS# BS# RD/WR# SLADDR0 GPIO9/KPR0 PEDCPCO RD# RD# WR# WE# RDY GPIO9/KPR0 HSDA HSDO DF_nOE DF_nWE HSDI HSCS# CS# CS# CS# CS# CS# CS# BE1# 1 (as CNF6) 0 (as CNF6) UBE# WEU# nBE1 BE0# WR# ULE# WEL# nBE0 HSCK HSCL BURST# 0 (as CNF5) 1 (as CNF5) 0 (as CNF5) 0 (as CNF5) 1 (as CNF5) 1 (as CNF5) 1 (as CNF5) BDIP# 1 (as CNF4) 1 (as CNF4) 0 (as CNF4) 0 (as CNF4) 0 (as CNF4) 0 (as CNF4) 0 (as CNF4) TEA# 1 (as CNF3) 1 (as CNF3) 1 (as CNF3) 1 (as CNF3) 1 (as CNF3) 1 (as CNF3) 1 (as CNF3) CNF2 0 0 1 1 1 1 1 CNF1 0 0 0 0 0 0 0 = These pins select the interface. 36 SPI = These pins are unused for the interface. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins Note The I2C slave address configuration from DB[6:0] is latched on RESET#. Reserved I2C slave addresses are not supported. See Section 21.11, “I2C Host Interface” on page 526 for information. Any changes to the I2C Slave Address requires a hardware RESET#. Hardware Functional Specification Rev. 1.7 EPSON 37 Chapter 5 Pins S1D13515/S2D13515 Table 5-16: Host Interface Pin Mapping 4 S1D13515/ S2D13515 Pin NEC V850 Type1 16-bit Direct NEC V850 Type2 16-bit Direct MPC555 MPC555 Renesas SH4 TI TMS470 TI TMS470 16-bit Indirect 16-bit Direct 16-bit Direct 16-bit Indirect 16-bit Direct Little Endian Little Endian DB15 D15 D15 D15 D15 D15 D0 D0 DB14 D14 D14 D14 D14 D14 D1 D1 DB13 D13 D13 D13 D13 D13 D2 D2 DB12 D12 D12 D12 D12 D12 D3 D3 DB11 D11 D11 D11 D11 D11 D4 D4 DB10 D10 D10 D10 D10 D10 D5 D5 DB9 D9 D9 D9 D9 D9 D6 D6 DB8 D8 D8 D8 D8 D8 D7 D7 DB7 D7 D7 D7 D7 D7 D8 D8 DB6 D6 D6 D6 D6 D6 D9 D9 DB5 D5 D5 D5 D5 D5 D10 D10 DB4 D4 D4 D4 D4 D4 D11 D11 DB3 D3 D3 D3 D3 D3 D12 D12 DB2 D2 D2 D2 D2 D2 D13 D13 DB1 D1 D1 D1 D1 D1 D14 D14 DB0 D0 D0 D0 D0 D0 D15 D15 M/R# M/R# M/R# M/R# GPIO9/KPR0 M/R# GPIO9/KPR0 M/R# AB20 A20 A20 A20 GPIO10/KPR1 GPIO10/KPR1 A11 AB19 A19 A19 A19 GPIO12/KPR2 A19 GPIO12/KPR2 A12 AB18 A18 A18 A18 KPR3 A18 KPR3 A13 AB17 A17 A17 A17 GPIO8/KPR4 A17 GPIO8/KPR4 A14 AB16 A16 A16 A16 GPIO13/KPC0 A16 GPIO13/KPC0 A15 AB15 A15 A15 A15 GPIO14/KPC1 A15 GPIO14/KPC1 A16 AB14 A14 A14 A14 GPIO15/KPC2 A14 GPIO15/KPC2 A17 AB13 A13 A13 A13 GPIO11/KPC3 A13 GPIO11/KPC3 A18 AB12 A12 A12 A12 KPC4 A12 KPC4 A19 AB11 A11 A11 A11 PEDST0 A11 PEDST0 A20 AB10 A10 A10 A10 PEDST1 A10 PEDST1 A21 AB9 A9 A9 A9 PEDST2 A9 PEDST2 A22 AB8 A8 A8 A8 PEDCLK A8 PEDCLK A23 AB7 A7 A7 A7 PEDSIO A7 PEDSIO A24 AB6 A6 A6 A6 PEDCPCO A6 PEDCPCO A25 AB5 A5 A5 A5 A5 A26 AB4 A4 A4 A4 A4 A27 AB3 A3 A3 A3 A3 AB2 A2 A2 A2 A2 A2 A29 A29 AB1 A1 A1 A1 A1 A1 A30 A30 AB0 0 (as CNF6) 1 (as CNF6) 0 (as CNF6) 0 (as CNF3) 1 (as CNF3) BUSCLK CLK CLK CLK CLK CLK CLK CLK WAIT# WAIT# WAIT# RDY# TA# TA# TA# TA# RD# DSTB# RD# RD# OE# OE# 1 TSIZ0 RD/WR# R/W# RD/WR# RD/WR# RD/WR# RD/WR# CS# CS# CS# CS# CS# CS# CS# CS# BE1# UBEN# WRH# WE1# 0 UB# 0 (as CNF3) 1 (as CNF3) BE0# LBEN# WRL# WE0# 0 LB# 0 TSIZ1 BS# TS# TS# TS# TS# BURST# BURST# BURST# BURST# BS# A31 BURST# 0 (as CNF5) 0 (as CNF5) 1 (as CNF5) BDIP# 1 (as CNF4) 1 (as CNF4) 1 (as CNF4) BDIP# BDIP# BDIP# BDIP# TEA# 1 (as CNF3) 1 (as CNF3) 1 (as CNF3) ERR_ACK# ERR_ACK# TEA# TEA# CNF2 1 1 1 0 0 1 1 CNF1 0 0 0 1 1 1 1 = These pins select the interface. 38 A28 = These pins are unused for the interface. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 5 Pins 5.6 LCD / Camera2 Pin Mapping The primary use for the FP1IO[23:0] pins is for the LCD1 interface or Camera2 interface. However, these pins may also be used for an EID Double Screen panel on LCD2, Keypad interface, or GPIOs. In these cases, the pin mapping for each interface changes as shown in the following table. Table 5-17: FP1IO Pin Mapping Summary (LCD1 / Camera2) Generic TFT/TFD on LCD1 (REG[4000h] bit 3 = 0b) S1D13515/ S2D13515 Pin LCD2 does not use any FP1 Pins (see Note 1) RGB 6:6:6 (REG[4000h] bit 2 = 0b) RGB 5:6:5 with SCI (REG[4000h] bit 2 = 1b) Camera2 Interface (REG[4000h] bit 3 = 1b) LCD2 uses FP1 Pins (see Note 2) RGB 5:5:5 (REG[4000h] bit 2 = 0b) RGB 4:4:4 with SCI REG[4000h] bit 2 = 1b LCD2 does not use any FP1 Pins (see Note 1) 8-bit Camera (REG[0D46h] bit 2 = 0b) RGB Data Stream (REG[0D46h] bit 2 = 1b) LCD2 uses FP1 Pins (see Note 2) 8-bit Camera (REG[0D46h] bit 2 = 0b) RGB Data Stream (REG[0D46h] bit 2 = 1b) FP1 Mode 0 1 2 3 5 4 7 6 FP1IO0 R7 R7 R7 R7 CM2DAT0 C2RIN7 CM2DAT0 C2RIN7 FP1IO1 R6 R6 R6 R6 CM2DAT1 C2RIN6 CM2DAT1 C2RIN6 FP1IO2 R5 R5 R5 R5 CM2DAT2 C2RIN5 CM2DAT2 C2RIN5 FP1IO3 G7 G7 G7 G7 CM2DAT3 C2GIN7 CM2DAT3 C2GIN7 FP1IO4 G6 G6 G6 G6 CM2DAT4 C2GIN6 CM2DAT4 C2GIN6 FP1IO5 G5 G5 G5 G5 CM2DAT5 C2GIN5 CM2DAT5 C2GIN5 FP1IO6 B7 B7 B7 B7 CM2DAT6 C2BIN7 CM2DAT6 C2BIN7 FP1IO7 B6 B6 B6 B6 CM2DAT7 C2BIN6 CM2DAT7 C2BIN6 FP1IO8 B5 B5 B5 B5 CM2CLKIN C2BIN5 CM2CLKIN C2BIN5 FP1IO9 R4 R4 R4 R4 CM2CLKOUT C2RIN4 CM2CLKOUT C2RIN4 FP1IO10 R3 R3 R3 SCS CM2FIELD C2RIN3 CM2FIELD C2RIN3 FP1IO11 R2 SCS POLGMA POLGMA KPR3 C2RIN2 POLGMA POLGMA FP1IO12 G4 G4 G4 G4 CM2VREF C2GIN4 CM2VREF C2GIN4 FP1IO13 G3 G3 G3 SCK CM2HREF C2GIN3 CM2HREF C2GIN3 FP1IO14 G2 G2 DEXR DEXR KPR4/GPIO8 C2GIN2 DEXR DEXR FP1IO15 B4 B4 B4 B4 KPR0/GPIO9 C2BIN4 KPR0/GPIO9 C2BIN4 FP1IO16 B3 B3 B3 SDO KPR1/GPIO10 C2BIN3 KPR1/GPIO10 C2BIN3 FP1IO17 B2 SCK CPV CPV KPC3/GPIO11 C2BIN2 CPV CPV FP1IO18 GPIO6 SDA0 OE OE GPIO6 GPIO6 OE OE FP1IO19 GPIO7 (Note 3) SDO LED_DIM_OUT LED_DIM_OUT KPC4/GPIO7 GPIO7 LED_DIM_OUT LED_DIM_OUT FP1IO20 HSYNC HSYNC HSYNC HSYNC KPR2/GPIO12 C2HSIN KPR2/GPIO12 C2HSIN FP1IO21 VSYNC VSYNC VSYNC VSYNC KPC0/GPIO13 C2VSIN KPC0/GPIO13 C2VSIN FP1IO22 DE DE DE DE KPC1/GPIO14 C2DEIN KPC1/GPIO14 C2DEIN FP1IO23 PCLK PCLK PCLK PCLK KPC2/GPIO15 C2PCLKIN KPC2/GPIO15 C2PCLKIN 1. This pin mapping applies when: - LCD2 is not an EID Double Screen panel (REG[4000h] bits 5-4 = 00b or 10b) - LCD2 is an EID Double Screen panel with TCON Disabled (REG[4000h] bits 5-4 = 01b and REG[4040h] bit 0 = 0b) - LCD2 is an EID Double Screen panel with TCON Enabled on the I2S pins ([REG[4000h] bits 5-4 = 01b and REG[4040h] bit 0 = 1b] and REG[4000h] bit 1 = 1b) 2. This pin mapping applies when: - LCD2 is an EID Double Screen panel with TCON Enabled on the FP1 pins ([REG[4000h] bits 5-4 = 01b and REG[4040h] bit 0 = 1b] and REG[4000h] bit 1 = 0b) 3. GPIO7 is not available when the Keypad Interface is configured to use the FP1IO pins, REG[0186h] bit 5 = 1b. Hardware Functional Specification Rev. 1.7 EPSON 39 Chapter 5 Pins S1D13515/S2D13515 The FP2IO[27:0] pins are used for the LCD2 interface. When the LCD2 interface is configured for a generic TFT/TFD, EID Double Screen with TCON disabled (REG[4040h] bit 0 = 0b), or Sharp DualView panel, all LCD2 pins can be mapped to the FP2IO[27:0] pins. However, when LCD2 is configured for a EID Double Screen with TCON enabled (REG[4040h] bit 0 = 1b), additional pins are required and must be selected from either the FP1IO pins or the I2S/PWM1 pins. The following table summarizes the possible FP2IO pin mappings. Table 5-18: FP2IO Pin Mapping Summary (LCD2) S1D13515/ S2D13515 Pin Generic RGB or EID Double Screen with TCON Disabled2 (REG[4000h] bits 5-4 = 00b) or (REG[4000h] bits 5-4 = 01b and REG[4040h] bit 0 = 0b) RGB 8:8:8 no SCI (REG[4000h] bits 7-6 = 00b) RGB 6:6:6 with SCI (REG[4000h] bits 7-6 = 01b) RGB 6:6:6 no SCI (REG[4000h] bits 7-6 = 10b) EID Double Screen with EID Double Screen with TCON Enabled on FP1 TCON Enabled on I2S (REG[4000h] (REG[4000h] bits 5-4 = 01b and bits 5-4 = 01b and REG[4040h] bit 0 = 1b) and REG[4040h] bit 0 = 1b) and REG[4000h] bit 1 = 0b REG[4000h] bit 1 = 1b Sharp DualView (REG[4000h] bits 5-4 = 10b) FP2 Mode 0 1 2 3 3 4 FP2IO0 R7 R7 R7 R7 R7 R7 FP2IO1 R6 R6 R6 R6 R6 R6 FP2IO2 R5 R5 R5 R5 R5 R5 FP2IO3 G7 G7 G7 G7 G7 G7 FP2IO4 G6 G6 G6 G6 G6 G6 FP2IO5 G5 G5 G5 G5 G5 G5 FP2IO6 B7 B7 B7 B7 B7 B7 FP2IO7 B6 B6 B6 B6 B6 B6 FP2IO8 B5 B5 B5 B5 B5 B5 FP2IO9 R4 R4 R4 R4 R4 R4 FP2IO10 R3 / PEDST01 R3 / PEDST01 R3 / PEDST01 R3 / PEDST01 R3 / PEDST01 R3 / PEDST01 FP2IO11 1 1 1 1 1 R2 / PEDST11 R2 / PEDST1 R2 / PEDST1 R2 / PEDST1 R2 / PEDST1 R2 / PEDST1 FP2IO12 G4 G4 G4 G4 G4 G4 FP2IO13 G3 / PEDST21 G3 / PEDST21 G3 / PEDST21 G3 / PEDST21 G3 / PEDST21 G3 / PEDST21 FP2IO14 G2 / PEDCLK1 G2 / PEDCLK1 G2 / PEDCLK1 G2 / PEDCLK1 G2 / PEDCLK1 G2 / PEDCLK1 FP2IO15 B4 B4 B4 B4 B4 B4 FP2IO16 B3 / PEDCPCO1 B3 / PEDCPCO1 B3 / PEDCPCO1 B3 / PEDCPCO1 B3 / PEDCPCO1 B3 / PEDCPCO1 FP2IO17 B2 / PEDSIO1 B2 / PEDSIO1 B2 / PEDSIO1 B2 / PEDSIO1 B2 / PEDSIO1 B2 / PEDSIO1 FP2IO18 R1 SCS GPIO0 ONA ONA VCOM FP2IO19 R0 SCK GPIO1 ONB ONB VCOMB FP2IO20 G1 SDA0 GPIO2 ONC ONC SPR FP2IO21 G0 SDO GPIO3 OND OND SPL FP2IO22 B1 GPIO4 GPIO4 VREVOUT VREVOUT GPIO4 GPIO5 FP2IO23 B0 GPIO5 GPIO5 HREVOUT HREVOUT FP2IO24 HSYNC HSYNC OHSYNC EISF EISF LS FP2IO25 VSYNC VSYNC OVSYNC FLMF FLMF SPS FP2IO26 DE DE ODE STRB STRB CLS FP2IO27 PCLK PCLK ODCK ODCK ODCK CK FP1IO11 — POLGMA — — FP1IO14 — — — DEXR — — FP1IO17 — — — CPV — — FP1IO18 — — — OE — — FP1IO19 — — — LED_DIM_OUT — — WSIO — — — — POLGMA — SCKIO — — — — DEXR — SDO — — — — CPV — MCLKO — — — — OE — PWM1 — — — — LED_DIM_OUT — 1. These pins are used for the C33PE debugger interface (PED*) if REG[008Ah] bit 1 is 1b, the Host Interface selected is Direct 16-bit, and the Host Interface selected is not Marvell PXA3xx Direct 16-bit. 2. When LCD2 is an EID Doublescreen with TCON disabled, FP2IO[23:18] is driven LOW. 40 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 6 D.C. Characteristics Chapter 6 D.C. Characteristics Note 1. When applying supply voltages to the S1D13515/S2D13515, Core VDD must be applied to the chip before, or simultaneously with H VDD, or damage to the chip may result. 2. Core VDD, OSC VDD, and PLL VDD must be equal to or lower than H VDD. Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Core VDD Supply Voltage VSS - 0.3 to 2.5 V H VDD Supply Voltage VSS - 0.3 to 4.0 V OSC VDD Supply Voltage VSS - 0.3 to 2.1 V PLL VDD Supply Voltage VSS - 0.3 to 2.1 V Input Voltage VSS - 0.3 to H VDD + 0.5 V VOUT Output Voltage VSS - 0.3 to H VDD + 0.5 V TSTG Storage Temperature -65 to 150 °C VIN Table 6-2 : Recommended Operating Conditions 1 Symbol Parameter Condition Min Typ Max Units Core VDD Supply Voltage VSS = 0 V 1.65 1.8 1.95 V H VDD-HIO Supply Voltage VSS = 0 V 3.0 3.3 3.6 V H VDD-PIO1 Supply Voltage VSS = 0 V 3.0 3.3 3.6 V H VDD-PIO2 Supply Voltage VSS = 0 V 3.0 3.3 3.6 V H VDD-SD Supply Voltage VSS = 0 V 3.0 3.3 3.6 V H VDD-CM1 Supply Voltage VSS = 0 V 3.0 3.3 3.6 V H VDD-IO Supply Voltage VSS = 0 V 3.0 3.3 3.6 V OSC VDD Supply Voltage (note) VSS = 0 V 1.65 1.8 1.95 V PLL1 VDD Supply Voltage VSS = 0 V 1.65 1.8 1.95 V PLL2 VDD Supply Voltage VSS = 0 V 1.65 1.8 1.95 V VSS — Core VDD V VSS — IO VDD V S1D13515 -40 25 85 °C S2D13515 -40 25 105 °C VIN TOPR Input Voltage Operating Temperature Note OSC VDD must be the same voltage as CORE VDD. Hardware Functional Specification Rev. 1.7 EPSON 41 Chapter 6 D.C. Characteristics S1D13515/S2D13515 Table 6-3 : Recommended Operating Conditions 2 Symbol Parameter Condition Min Typ Max Units Core VDD Supply Voltage VSS = 0 V 1.65 1.8 1.95 V H VDD-HIO Supply Voltage VSS = 0 V 2.3 2.5 2.7 V H VDD-PIO1 Supply Voltage VSS = 0 V 2.3 2.5 2.7 V H VDD-PIO2 Supply Voltage VSS = 0 V 2.3 2.5 2.7 V H VDD-SD Supply Voltage VSS = 0 V 3.0 3.3 3.6 V H VDD-CM1 Supply Voltage VSS = 0 V 2.3 2.5 2.7 V H VDD-IO Supply Voltage VSS = 0 V 2.3 2.5 2.7 V OSC VDD Supply Voltage VSS = 0 V 1.65 1.8 1.95 V PLL1 VDD Supply Voltage VSS = 0 V 1.65 1.8 1.95 V PLL2 VDD Supply Voltage VSS = 0 V 1.65 1.8 1.95 V VSS — Core VDD V VSS — IO VDD V S1D13515 -40 25 85 °C S2D13515 -40 25 105 °C Max Units μA μA μA mA mA mA mA V V V V V kΩ kΩ kΩ kΩ pF pF pF VIN TOPR Input Voltage Operating Temperature Table 6-4: Electrical Characteristics for VDD = 3.3V typical Symbol IDDS IIZ IOZ IOH2 IOH3 IOL2 IOL3 VIH VIL VT+ VTVH RPU RPD CI CO CIO 42 Parameter Quiescent Current Input Leakage Current Output Leakage Current High Level Output Current High Level Output Current Low Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage Condition Quiescent Conditions VI = 0V or VDD VO = 0V or VDD VOH = H VDD - 0.4V H VDD = min VOL = 0.4V H VDD = min LVCMOS level, H VDD = max LVCMOS level, H VDD = min LVCMOS Schmitt LVCMOS Schmitt LVCMOS Schmitt VI = 0V, Type 1 Pull-up Resistance VI = 0V, Type 2 VI = H VDD, Type 1 Pull-down Resistance VI = H VDD, Type 2 Input Pin Capacitance F = 1MHz, H VDD = 0V Output Pin Capacitance F = 1MHz, H VDD = 0V Bi-Directional Pin Capacitance F = 1MHz, H VDD = 0V EPSON Min -5 -5 -4 -8 4 8 2.2 -0.3 1.4 0.6 0.3 25 50 25 50 — — — Typ 23 — — — — — — — — — — — 50 100 50 100 — — — 5 5 — — — — H VDD + 0.3 0.8 2.7 1.8 — 120 240 120 240 8 8 8 Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 6 D.C. Characteristics Table 6-5: Electrical Characteristics for VDD = 2.5V typical Symbol IDDS IIZ IOZ IOH2 IOH3 IOL2 IOL3 VIH VIL VT+ VTVH RPU RPD CI CO CIO Parameter Quiescent Current Input Leakage Current Output Leakage Current High Level Output Current High Level Output Current Low Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage Condition Quiescent Conditions VI = 0V or VDD VO = 0V or VDD VOH = H VDD - 0.4V H VDD = min VOL = 0.4V H VDD = min LVCMOS level, H VDD = max LVCMOS level, H VDD = min LVCMOS Schmitt LVCMOS Schmitt LVCMOS Schmitt VI = 0V, Type 1 Pull-up Resistance VI = 0V, Type 2 VI = H VDD, Type 1 Pull-down Resistance VI = H VDD, Type 2 Input Pin Capacitance F = 1MHz, H VDD = 0V Output Pin Capacitance F = 1MHz, H VDD = 0V Bi-Directional Pin Capacitance F = 1MHz, H VDD = 0V Hardware Functional Specification Rev. 1.7 EPSON Min -5 -5 -3 -6 3 6 1.7 -0.2 0.8 0.5 0.3 35 70 35 70 — — — Typ 23 — — — — — — — — — — — 70 140 70 140 — — — Max 5 5 — — — — H VDD + 0.2 0.7 1.9 1.3 — 175 350 175 350 8 8 8 Units μA μA μA mA mA mA mA V V V V V kΩ kΩ kΩ kΩ pF pF pF 43 Chapter 7 A.C. Characteristics S1D13515/S2D13515 Chapter 7 A.C. Characteristics Conditions: IO VDD = 3.3V +/- 10% Core VDD = 1.8V +/- 10% TA = -40 to 85°C for the S1D13515 -40 to 105°C for the S2D13515 Trise and Tfall for all inputs must be < 5 ns (10% ~ 90%) CL = 30 pF, except for the Host Interface (50 pF) and the SDRAM Interface (15 pF) 7.1 Clock Timing 7.1.1 Input Clocks t t PWH PWL 90% V IH VIL 10% t tr T f OSC Figure 7-1: Clock Requirements for OSC/CLKI Table 7-1: Clock Requirements for OSC/CLKI when used as Clock Input Symbol Parameter Min Typ Max Units fOSC Input Clock Frequency for OSC 20 — 40 MHz TOSC Input Clock Period for OSC — 1/fOSC — ns fCLKI Input Clock Frequency for CLKI 5 — 100 MHz TCLKI Input Clock Period for CLKI — 1/fCLKI — ns tPWH Input Clock Pulse Width High 0.4 — 0.6 TOSC tPWL Input Clock Pulse Width Low 0.4 — 0.6 TOSC tf Input Clock Fall Time (10% - 90%) — — 0.2 TOSC tr Input Clock Rise Time (10% - 90%) — — 0.2 TOSC -150 — 150 ps tjitter Input Clock Jitter Table 7-2: Clock Requirements for OSC when used as Crystal Oscillator Input Symbol 44 Parameter Min Typ Max Units fOSC Input Clock Frequency for OSC 20 — 40 MHz TOSC Input Clock Period for OSC — 1/fOSC — ns EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.1.2 Internal Clocks Table 7-3: Internal Clock Requirements Symbol Parameter Min Max Units fSDRAMCLK SDRAM Clock Frequency — 100 MHz fSYSCLK System Clock Frequency — 50 MHz For further information on the internal clocks, refer to Section Chapter 9, “Clocks” on page 128. Note For XGA 1024x768 panel support, the DRAMCLK must be 100MHz. See Chapter 13, “Display Subsystem” on page 443 for further information. Hardware Functional Specification Rev. 1.7 EPSON 45 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.1.3 PLL Clock The PLL circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The jitter of the input clock waveform should be as small as possible. PLL Enable 200μs Lock In Time PLL Stable 5-100MHz Reference Clock PLL xxMHz Output (xx = 20-200MHz) Jitter (ns) Lock in time 200μs Time (ms) The PLL frequency will ramp between the OFF state and the programmed frequency. To guarantee the lowest possible clock jitter, 200μs is required for stabilization. Figure 7-2: PLL Start-Up Time Table 7-4: PLL Clock Requirements Symbol 46 Parameter Min Max Units fPLL PLL output clock frequency 20 200 MHz tPStal PLL output stable time — 200 μs EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.2 Power Supply Sequence 7.2.1 Power Supply Structure S1D13515/S2D13515 HIOVDD IOVDD PIO1VDD PIO2VDD SDVDD CM1VDD COREVDD VSS OSCVDD OSCVSS PLLVDD1 PLLVSS1 PLLVDD2 PLLVSS2 Figure 7-3: Internal Power Structure Hardware Functional Specification Rev. 1.7 EPSON 47 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.2.2 Power-On Sequence COREVDD PLLVDD1 PLLVDD2 OSCVDD HIOVDD IOVDD PIO1VDD PIO2VDD SDVDD CM1VDD t1 approx. 0.8V t2 RESET# Figure 7-4: Power-On Sequence Table 7-5: Power-On Sequence Symbol Parameter Min Max Units t1 HIOVDD, IOVDD, PIO1VDD, PIO2VDD, SDVDD, CM1VDD on delay from COREVDD, OSCVDD, PLLVDD1, PLLVDD2 on 0 500 ms t2 RESET# deasserted from HIOVDD, IOVDD, PIO1VDD, PIO2VDD, SDVDD, CM1VDD on 55 — ns 7.2.3 Power-Off Sequence COREVDD PLLVDD1 PLLVDD2 OSCVDD t1 HIOVDD IOVDD PIO1VDD PIO2VDD SDVDD CM1VDD approx. 0.8V Figure 7-5: Power-Off Sequence Table 7-6: Power-Off Sequence 48 Symbol Parameter Min Max Units t1 COREVDD, OSCVDD, PLLVDD1, PLLVDD2 off delay from HIOVDD, IOVDD, PIO1VDD, PIO2VDD, SDVDD, CM1VDD off 0 500 ms EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.3 RESET# Timing t1 t2 RESET# Figure 7-6 RESET# Timing Table 7-7 RESET# Timing Symbol Parameter Min Max Units t1 Reset Pulse Width to be ignored — 20 ns t2 Active Reset Pulse Width 55 — ns 1. If the reset pulse width is less than t1max, it is ignored. If the reset pulse width is between t1max and t2min, there is no guarantee that the reset will take effect. To ensure that reset takes effect, the reset pulse width must be greater than t2min. 2. When the OSC is used to supply clock source for system clock, CNF0 = 1b, then the RESET# should be asserted long enough for the crystal oscillator to stabilize its clock output before de-asserting. The crystal startup time varies based on crystal, and external crystal oscillator components used. Hardware Functional Specification Rev. 1.7 EPSON 49 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4 Parallel Host Bus Interface Timing 7.4.1 Direct/Indirect Intel 80 Type 1 t1 t6 CS# t7 t2 A[20:0] M/R# UBE#, LBE# t15 t13 t14 WE# t16 RD# t4 t3 WAIT# Hi-Z Hi-Z t20 DB[15:0] t9 Hi-Z Valid Hi-Z Figure 7-7: Direct/Indirect Intel 80 Type 1 Host Interface Write Timing Note For Indirect Intel 80 Type #1 8-bit, the BE1# and BE0# pins are not used. For Indirect Intel 80 Type #1 16-bit, the BE1# and BE0# pins should be tied to logic 0. For byte access in this mode, refer to Section 21.2, “Intel80 Type1 Interface” on page 514, note 2. 50 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-8: Direct/Indirect Intel 80 Type 1 Host Interface Write Timing Symbol Parameter t1 CS# setup time to WE# falling edge AB[20:0], M/R#, UBE#, LBE# setup time to WE# falling edge WE# falling edge to WAIT# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b WE# rising edge to WAIT# release for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b WE# rising edge to CS# hold time WE# rising edge to AB[20:0], M/R#, UBE#, LBE# hold time DB[15:0] hold time from WE# rising edge WE# cycle time - synchronous register access WE# cycle time - asynchronous register access WE# pulse active time - synchronous register access WE# pulse active time - asynchronous register access WE# pulse inactive time - synchronous register access WE# pulse inactive time - asynchronous register access WE# rising edge to RD# falling edge synchronous register access WE# rising edge to RD# falling edge asynchronous register access WE# falling edge to DB[15:0] valid write data synchronous register access WE# falling edge to DB[15:0] valid write data asynchronous register access t2 t3 t4 t6 t7 t9 t13 t14 t15 t16 t20 1. Ts HIOVDD = 2.5V Min Max 7 — HIOVDD = 3.3V Min Max 7 — Units ns 7 — 7 — ns 6 24 6 21 ns 5 23 5 20 ns 3 15 3 15 ns 3 7 15 — 3 7 15 — ns ns 7 — 7 — ns 5 3 55 — — — 5 3 55 — — — ns Ts (Note 1) ns 2 — 2 — Ts 37 — 37 — ns 1 — 1 — Ts 19 — 19 — ns 1 — 1 — Ts 19 — 19 — ns — Ts-10 — Ts-10 ns — 8 — 8 ns = System clock period Hardware Functional Specification Rev. 1.7 EPSON 51 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t6 CS# t2 t7 A[20:0] M/R# UBE#, LBE# t15 t13 t14 RD# t16 WE# t4 t3 WAIT# Hi-Z Hi-Z DB[15:0] Hi-Z t10 t11 t5 Invalid Valid Hi-Z t12 Figure 7-8: Direct/Indirect Intel 80 Type 1 Host Interface Read Timing Note For Indirect Intel 80 Type #1 8-bit, the BE1# and BE0# pins are not used. For Indirect Intel 80 Type #1 16-bit, the BE1# and BE0# pins should be tied to logic 0. For byte access in this mode, refer to Section 21.2, “Intel80 Type1 Interface” on page 514, note 2. 52 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-9: Direct/Indirect Intel 80 Type 1 Host Interface Read Timing Symbol Parameter t1 CS# setup time to RD# falling edge AB[20:0], M/R#, UBE#, LBE# setup time to RD# falling edge RD# falling edge to WAIT# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# rising edge to WAIT# release for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# falling edge to DB[15:0] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# rising edge to CS# hold time RD# rising edge to AB[20:0], M/R#, UBE#, LBE# hold time DB[15:0] hold time from RD# rising edge for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b WAIT# rising edge to valid DATA if WAIT# asserted for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# falling edge to valid DATA if WAIT# is NOT asserted for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# cycle time - synchronous register access RD# cycle time - asynchronous register access RD# pulse active time - synchronous register access RD# pulse active time - asynchronous register access RD# pulse inactive time - synchronous register access RD# pulse inactive time - asynchronous register access RD# rising edge to WE# falling edge synchronous register access RD# rising edge to WE# falling edge asynchronous register access t2 t3 t4 t5 t6 t7 t10 t11 t12 t13 t14 t15 t16 1. Ts HIOVDD = 2.5V Min Max 7 — HIOVDD = 3.3V Min Max 7 — Units ns 7 — 7 — ns 8 28 8 25 ns 7 27 7 25 ns 4 19 4 19 ns 4 19 4 18 ns 7 28 7 25 ns 7 10 27 — 6 10 25 — ns ns 10 — 10 — ns 4 20 4 20 ns 4 20 4 20 ns — 6 — 4 ns — 6 — 4 ns — 28 — 26 ns — 3 55 28 — — — 3 55 25 — — ns Ts (Note 1) ns 2 — 2 — Ts 37 — 37 — ns 1 — 1 — Ts 19 — 19 — ns 1 — 1 — Ts 19 — 19 — ns = System clock period Hardware Functional Specification Rev. 1.7 EPSON 53 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.2 Direct/Indirect Intel 80 Type 2 t1 t6 CS# t7 t2 A[20:0] M/R# t15 t13 t14 WEU# WEL# t16 RD# t4 t3 WAIT# Hi-Z Hi-Z t20 DB[15:0] t9 Hi-Z Valid Hi-Z Figure 7-9: Direct/Indirect Intel 80 Type 2 Host Interface Write Timing Note For Indirect Intel 80 Type #2 8-bit, the WEU# is not used. For Indirect Intel 80 Type #2 16-bit, the WEU# and WEL# pins should be driven in unison (16-bit host write access is mandatory). For byte access in this mode, refer to Section 21.3, “Intel80 Type2 Interface” on page 515, note 2. 54 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-10: Direct/Indirect Intel 80 Type 2 Host Interface Write Timing Symbol Parameter t1 CS# setup time to WEU#, WEL# falling edge AB[20:0], M/R# setup time to WEU#, WEL# falling edge WEU#, WEL# falling edge to WAIT# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b WEU#, WEL# rising edge to WAIT# release for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b WEU#, WEL# rising edge to CS# hold time WEU#, WEL# rising edge to AB[20:0], M/R# hold time DB[15:0] hold time from WEU#, WEL# rising edge WEU#, WEL# cycle time - synchronous register access WEU#, WEL# cycle time - asynchronous register access WEU#, WEL# pulse active time - synchronous register access WEU#, WEL# pulse active time - asynchronous register access WEU#, WEL# pulse inactive time - synchronous register access WEU#, WEL# pulse inactive time asynchronous register access WEU#, WEL# rising edge to RD# falling edge synchronous register access WEU#, WEL# rising edge to RD# falling edge asynchronous register access WEU#, WEL# falling edge to DB[15:0] valid write data - synchronous register access WEU#, WEL# falling edge to DB[15:0] valid write data - asynchronous register access t2 t3 t4 t6 t7 t9 t13 t14 t15 t16 t20 1. Ts HIOVDD = 2.5V Min Max 7 — HIOVDD = 3.3V Min Max 7 — Units ns 7 — 7 — ns 6 25 6 22 ns 5 24 5 21 ns 2 16 2 16 ns 2 7 16 — 2 7 16 — ns ns 7 — 7 — ns 5 — 5 — ns 3 — 3 — 55 — 55 — ns 2 — 2 — Ts 37 — 37 — ns 1 — 1 — Ts 19 — 19 — ns 1 — 1 — Ts 19 — 19 — ns — Ts-10 — Ts-10 ns — 8 — 8 ns Ts (Note 1) = System clock period Hardware Functional Specification Rev. 1.7 EPSON 55 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t6 CS# t2 t7 A[20:0] M/R# t15 t13 t14 RD# t16 WEU# WEL# t4 t3 WAIT# Hi-Z Hi-Z DB[15:0] Hi-Z t10 t11 t5 Invalid Valid Hi-Z t12 Figure 7-10: Direct/Indirect Intel 80 Type 2 Host Interface Read Timing Note For Indirect Intel 80 Type #2 8-bit, the WEU# is not used. For Indirect Intel 80 Type #2 16-bit, the WEU# and WEL# pins should be driven in unison (16-bit host write access is mandatory). For byte access in this mode, refer to Section 21.3, “Intel80 Type2 Interface” on page 515, note 2. 56 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-11: Direct/Indirect Intel 80 Type 2 Host Interface Read Timing Symbol Parameter t1 t2 CS# setup time to RD# falling edge AB[20:0], M/R# setup time to RD# falling edge RD# falling edge to WAIT# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# rising edge to WAIT# release for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# falling edge to DB[15:0] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# rising edge to CS# hold time RD# rising edge to AB[20:0], M/R# hold time DB[15:0] hold time from RD# rising edge for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b WAIT# rising edge to valid DATA if WAIT# asserted for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# falling edge to valid DATA if WAIT# is NOT asserted for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# cycle time - synchronous register access RD# cycle time - asynchronous register access RD# pulse active time - synchronous register access RD# pulse active time - asynchronous register access RD# pulse inactive time - synchronous register access RD# pulse inactive time - asynchronous register access RD# rising edge to WEU#, WEL# falling edge synchronous register access RD# rising edge to WEU#, WEL# falling edge asynchronous register access t3 t4 t5 t6 t7 t10 t11 t12 t13 t14 t15 t16 1. Ts HIOVDD = 2.5V Min Max 7 — 7 — HIOVDD = 3.3V Min Max 7 — 7 — Units ns ns 8 28 8 25 ns 7 27 7 25 ns 4 19 4 19 ns 4 19 4 19 ns 7 28 7 25 ns 7 9 9 27 — — 6 9 9 25 — — ns ns ns 4 20 4 20 ns 4 20 4 20 ns — 5 — 4 ns — 5 — 4 ns — 29 — 27 ns — 3 55 28 — — — 3 55 25 — — ns Ts (Note 1) ns 2 — 2 — Ts 37 — 37 — ns 1 — 1 — Ts 19 — 19 — ns 1 — 1 — Ts 19 — 19 — ns = System clock period Hardware Functional Specification Rev. 1.7 EPSON 57 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.3 Direct Marvell PXA3xx VLIO t3 CS# t4 t2 DF_ADDR[3:0] 0 1 t16 t6 DF_IO[15:0] U Add t17 L Add wd0 wd1 t9 nLUA t8 t10 nLLA t20 t21 t22 DF_nWE t13 t11 RDY t14 nBE[1:0] Hi-Z Hi-Z Hi-Z “00” t15 m0 m1 Figure 7-11: Direct Marvell PXA3xx VLIO Host Interface Write Timing 58 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-12: Direct Marvell PXA3xx VLIO Host Interface Write Timing Symbol t2 t3 t4 t6 t8 t9 t10 t11 t13 t14 t15 t16 t17 t20 t21 t22 1. Ts HIOVDD = 2.5V Min Max Parameter DF_ADDR[3:0] setup time to DF_nWE falling edge CS# hold time from DF_nWE rising edge DF_ADDR[3:0] hold time from DF_nWE rising edge DF_IO[15:0] hold time from nLUA rising edge DF_IO[15:0] hold time from nLLA rising edge nLUA pulse active time nLLA pulse active time DF_nWE falling edge to RDY driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DF_nWE rising edge to RDY tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b nBE[1:0] setup time to DF_nWE falling edge nBE[1:0] hold time from DF_nWE rising edge DF_IO[15:0] setup time to DF_nWE falling edge DF_IO[15:0] hold time from DF_nWE rising edge DF_nWE rising edge to nLUA falling edge synchronous register access DF_nWE rising edge to nLUA falling edge asynchronous register access DF_nWE pulse active time - synchronous register access DF_nWE pulse active time - asynchronous register access DF_nWE pulse inactive time - synchronous register access DF_nWE pulse inactive time - asynchronous register access HIOVDD = 3.3V Min Max Units 6 — 6 — ns 7 — 7 — ns 7 — 7 — ns 0 0 25 25 — — — — 0 0 25 25 — — — — ns ns ns ns 6 24 6 21 ns 5 23 5 20 ns 3 15 3 15 ns 3 6 7 0 15 — — — 3 6 7 0 15 — — — ns ns ns ns 4 — 4 — ns 1 — 1 — 19 — 19 — ns 2 — 2 — Ts 37 — 37 — ns 1 — 1 — Ts 19 — 19 — ns Ts (Note 1) = System clock period Hardware Functional Specification Rev. 1.7 EPSON 59 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t3 CS# t2 DF_ADDR[3:0] wd0 0 DF_IO[15:0] U Add 1 t16 t6 wd1 t19 t17 Invalid L Add t4 rd0 Invalid rd1 Hi-Z t9 nLUA t8 t10 t18 nLLA t20 t21 t22 DF_nOE t13 t11 RDY nBE[1:0] Hi-Z Hi-Z Hi-Z “00” Figure 7-12: Direct Marvell PXA3xx VLIO Host Interface Read Timing 60 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-13: Direct Marvell PXA3xx VLIO Host Interface Read Timing Symbol Parameter t2 t3 DF_ADDR[3:0] setup time to DF_nOE falling edge CS# hold time from DF_nOE rising edge DF_ADDR[3:0] hold time from DF_nOE rising edge DF_IO[15:0] hold time from nLUA rising edge DF_IO[15:0] hold time from nLLA rising edge nLUA pulse active time nLLA pulse active time DF_nOE falling edge to RDY driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DF_nOE rising edge to RDY tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DF_nOE falling edge to DF_IO[15:0] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DF_IO[15:0] hold time from DF_nOE rising edge for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DF_nOE falling edge to valid data if RDY does not go to low - synchronous register access for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Valid data before RDY rising edge if RDY goes to low - asynchronous register access f or REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DF_nOE rising edge to nLUA falling edge synchronous register access DF_nOE rising edge to nLUA falling edge asynchronous register access DF_nOE pulse active time - synchronous register access DF_nOE pulse active time - asynchronous register access DF_nOE pulse inactive time - synchronous register access DF_nOE pulse inactive time - asynchronous register access t4 t6 t8 t9 t10 t11 t13 t16 t17 t18 t19 t20 t21 t22 HIOVDD = 2.5V Min Max 6 — 8 — HIOVDD = 3.3V Min Max 6 — 8 — Units ns ns 8 — 8 — Ns 0 0 25 25 — — — — 0 0 25 25 — — — — Ns Ns Ns Ns 8 28 8 25 ns 7 27 7 25 ns 4 19 4 19 ns 4 19 4 19 ns 7 28 7 25 ns 7 27 6 25 ns 4 20 4 20 ns 4 20 4 20 ns — 28 — 25 ns — 27 — 25 ns Note 2 — Note 4 — ns Note 3 — Note 5 — 1 — 1 — ns Ts (Note 1) 19 — 19 — ns 2 — 2 — Ts 37 — 37 — ns 1 — 1 — Ts 19 — 19 — ns 1. Ts = System clock period 2. When HIOVDD = 2.5V and REG[003Dh] bit 0 = 0b, t19min is calculated using the following formula. t19min = (REG[0085h] bits 2-0) x (System clock period) - 8.0ns 3. When HIOVDD = 2.5V and REG[003Dh] bit 0 = 1b, t19min is calculated using the following formula. t19min = (REG[0085h] bits 2-0) x (System clock period) - 8.0ns 4. When HIOVDD = 3.3V and REG[003Dh] bit 0 = 0b, t19min is calculated using the following formula. t19min = (REG[0085h] bits 2-0) x (System clock period) - 7.0ns 5. When HIOVDD = 3.3V and REG[003Dh] bit 0 = 1b, t19min is calculated using the following formula. t19min = (REG[0085h] bits 2-0) x (System clock period) - 7.0ns Hardware Functional Specification Rev. 1.7 EPSON 61 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.4 Direct/Indirect Renesas SH4 t1 t2 t3 1st 2nd CKIO t5 t4 A[20:0] M/R# RD/WR# t6 t7 BS# t17 t8 CS# t20 t20 WE0# WE1# t12 t11 RDY# t21 Hi-Z Hi-Z t14 t13 DB[15:0] t10 Hi-Z Hi-Z Valid Figure 7-13: Direct/Indirect Renesas SH4 Host Interface Write Timing Note For Indirect SH4 8-bit, the WE1# and WE0# is not used. For Indirect SH4 16-bit, the WE1# and WE0# pins should be driven in unison (16-bit host write access is mandatory). For byte access in this mode, refer to Section 21.6, “Renesas SH4 Interface” on page 518, note 2. 62 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-14: Direct/Indirect Renesas SH4 Host Interface Write Timing Symbol fCKIO t1 t2 t3 t4 t5 t6 t7 t8 t10 t11 t12 t13 t14 t17 t20 t21 (Note 2) HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 7 — 0 — 5 — Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low AB[20:0], M/R#, RD/WR# setup to CKIO AB[20:0], M/R#, RD/WR# hold from CKIO BS# setup BS# hold CS# setup CKIO to RDY# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CKIO to RDY# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CKIO to RDY# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DB[15:0] setup to 2nd CKIO after BS# DB[15:0] hold from CKIO CS# hold from CKIO WE0#, WE1# setup to CKIO CKIO to RDY# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 7 — 0 — 5 — Units MHz ns ns ns ns ns ns ns ns 4 24 4 21 ns 4 23 4 21 ns 4 24 4 21 ns 4 23 4 21 ns — 20 — 18 ns — 0 0 0 8 19 — — — — — 0 0 0 8 17 — — — — ns ns ns ns ns 0 — 0 — ns 0 — 0 — ns Note 1. When the S1D13515/S2D13515 completes a write, RDY# is driven low and then asserted high 2 CKIO later. This means that RDY# is only low for a 2 CKIO period. To sample RDY# low correctly, the SH4 Wait Control Register 2 (WCR2) must be set appropriately. For details on SH4 registers, refer to the SH4 specification. 2. At the end of the write cycle, RDY# may not drive HIGH and may become tri-stated (high impedance) 1 bus clock after RDY# was asserted LOW. Hardware Functional Specification Rev. 1.7 EPSON 63 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t2 t3 1st 2nd CKIO t5 t4 AB[20:0] M/R# RD/WR# t6 t7 t8 t11 BS# t18 CS# t17 t16 t19 t20 RD# t20 t12 RDY# Hi-Z Hi-Z t15 t9 DB[15:0] t10 t21 Hi-Z Invalid Valid Hi-Z Figure 7-14: Direct/Indirect Renesas SH4 Host Interface Read Timing Note For Indirect SH4 8-bit, the WE1# and WE0# is not used. For Indirect SH4 16-bit, the WE1# and WE0# pins should be driven in unison (16-bit host write access is mandatory). For byte access in this mode, refer to Section 21.6, “Renesas SH4 Interface” on page 518, note 2. 64 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-15: Direct/Indirect Renesas SH4 Host Interface Read Timing Symbol fCKIO t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t15 t16 t17 t18 t19 t20 t21 (Note 2) HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 7 — 0 — 5 — Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low AB[20:0], M/R#, RD/WR# setup to CKIO AB[20:0], M/R#, RD/WR# hold from CKIO BS# setup BS# hold CS# setup Falling edge of RD# to DB[15:0] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CKIO to RDY# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CKIO to RDY# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CKIO to RDY# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CKIO to DB[15:0] valid for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# rising edge to DB[15:0] tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CS# rising edge to DB[15:0] tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CS# hold from CKIO RD# hold from CKIO RD# setup to CKIO CKIO to RDY# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b HIOVDD = 3.3V Min Max 25 40 — 20 — 20 — 7 — 0 — 7 — 0 — 5 — Units MHz ns ns ns ns ns ns ns ns 7 — 7 — ns 7 — 7 — ns 4 24 4 21 ns 4 23 4 21 ns 4 24 4 21 ns 4 23 4 21 ns — 20 — 18 ns — 19 — 17 ns — 20 — 17 ns — 19 — 17 ns 4 22 4 22 ns 4 22 4 22 ns 3 13 3 13 ns 3 0 0 10 13 — — — 3 0 0 10 13 — — — ns ns ns ns 0 — 0 — ns 0 — 0 — ns Note 1. When read data is ready, RDY# is driven low and then asserted high 2 CKIO later. This means that RDY# is only low for a 2 CKIO period. To sample RDY# low correctly, the SH4 Wait Control Register 2 (WCR2) must be set appropriately. For details on SH4 registers, refer to the SH4 specification. 2. At the end of the read cycle, RDY# may not drive HIGH and may become tri-stated (high impedance) 1 bus clock after RDY# was asserted LOW. Hardware Functional Specification Rev. 1.7 EPSON 65 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.5 Direct/Indirect Freescale MPC555 (Non-burst Mode) t1 t2 t3 1st 2nd CLKOUT A[11:31] M/R# RD/WR# TSIZ[0:1] t4 t5 t6 t7 CS# t8 t9 TS# t13 t11 t10 TA# TEA# (see Note) t12 Hi-Z Hi-Z t19 t20 BURST# t17 D[0:15] t18 Hi-Z Valid Hi-Z Note: TEA# has a mild pull-down resistance and is never driven low. If ERR_ACK# is used, an external pull-up resistor (typically 10K ohm) should be connected. Figure 7-15: Direct/Indirect Freescale MPC555 Host Interface Write Timing (Non-burst Mode) Note 1. For Indirect MPC555, the TSIZ0 pin should be tied to “1” and TSIZ1 should be tied to “0” (16-bit host access is mandatory). For byte access in this mode, refer to Section 21.9, “MPC555 Interface” on page 521 note 3. 2. The S1D13515/S2D13515 does not support Big Endian configuration. The host processor must be configured for Little Endian External Bus when connected to the S1D13515/S2D13515 using the MPC555 interface. 66 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-16: Direct/Indirect Freescale MPC555 Host Interface Write Timing (Non-burst Mode) Symbol fCLKOUT t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t17 t18 t19 t20 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[11:31], M/R#, RD/WR#, TSIZ[0:1] setup A[11:31], M/R#, RD/WR#, TSIZ[0:1] hold CS# setup CS# hold TS# setup TS# hold CLKOUT to TA#, TEA# driven for REG[003Dh] bit0 = 0b for REG[003Dh] bit0 = 1b CLKOUT to TA#, TEA# low for REG[003Dh] bit0 = 0b for REG[003Dh] bit0 = 1b CLKOUT to TA#, TEA# high for REG[003Dh] bit0 = 0b for REG[003Dh] bit0 = 1b Negative edge CLKOUT to TA#, TEA# tristate for REG[003Dh] bit0 = 0b for REG[003Dh] bit0 = 1b D[0:15] setup to 1st CLKOUT after TS#=0 CLKOUT to D[0:15] hold BURST# setup BURST# hold Hardware Functional Specification Rev. 1.7 EPSON HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — Units MHz ns ns ns ns ns ns ns ns ns 4 24 4 21 ns 4 23 4 21 ns — 20 — 17 ns — 19 — 17 ns 6 20 5 17 ns 5 19 5 17 ns 4 24 4 21 ns 4 0 0 7 0 23 — — — — 4 0 0 7 0 20 — — — — ns ns ns ns ns 67 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t2 t3 1st 2nd CLKOUT A[11:31] M/R# RD/WR# TSIZ[0:1] t4 t5 t6 t7 CS# t8 t9 TS# t13 t11 t10 TA# TEA# (see Note) t12 Hi-Z Hi-Z t22 t23 BURST# t20 t19 D[0:15] Hi-Z Invalid t21 Valid Hi-Z Note: TEA# has a mild pull-down resistance and is never driven low. If ERR_ACK# is used, an external pull-up resistor (typically 10K ohm) should be connected. Figure 7-16: Direct/Indirect Freescale MPC555 Host Interface Read Timing (Non-burst Mode) Note 1. For Indirect MPC555, the TSIZ0 pin should be tied to “1” and TSIZ1 should be tied to “0” (16-bit host access is mandatory). For byte access in this mode, refer to Section 21.9, “MPC555 Interface” on page 521 note 3. 2. The S1D13515/S2D13515 does not support Big Endian configuration. The host processor must be configured for Little Endian External Bus when connected to the S1D13515/S2D13515 using the MPC555 interface. 68 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-17: Direct/Indirect Freescale MPC555 Host Interface Read Timing (Non-burst Mode) Symbol fCLKOUT t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t19 t20 t21 t22 t23 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[11:31], M/R#, RD/WR#, TSIZ[0:1] setup A[11:31], M/R#, RD/WR#, TSIZ[0:1] hold CS# setup CS# hold TS# setup TS# hold CLKOUT to TA#, TEA# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to TA#, TEA# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to TA#, TEA# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge CLKOUT to TA#, TEA# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to D[0:15] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to D[0:15] valid for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to D[0:15] tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b BURST# setup BURST# hold Hardware Functional Specification Rev. 1.7 EPSON HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — Units MHz ns ns ns ns ns ns ns ns ns 4 24 4 21 ns 4 23 4 21 ns — 20 — 17 ns — 19 — 17 ns 6 20 5 17 ns 5 19 5 17 ns 4 24 4 21 ns 4 23 4 20 ns 5 — 5 — ns 5 — 5 — ns — 20 — 17 ns — 19 — 16 ns 5 25 5 23 ns 5 7 0 24 — — 5 7 0 22 — — ns ns ns 69 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.6 Direct/Indirect Freescale MPC555 (Burst Mode) t1 t2 t3 CLKOUT A[11:31] M/R# RD/WR# TSIZ[0:1] t4 t5 t6 t7 CS# t8 t9 TS# t13 t11 t12 t10 TA# TEA# (see Note) Hi-Z Hi-Z t24 t25 BURST# t26 t27 BDIP# t18 t28 D[0:15] Valid t18 t28 Valid Note: TEA# has a mild pull-down resistance and is never driven low. If ERR_ACK# is used, an external pull-up resistor (typically 10K ohm) should be connected. Figure 7-17: Direct/Indirect Freescale MPC555 Host Interface Write Timing (Burst Mode) Note 1. For Indirect MPC555, the TSIZ0 pin should be tied to “1” and TSIZ1 should be tied to “0” (16-bit host access is mandatory). For byte access in this mode, refer to Section 21.9, “MPC555 Interface” on page 521 note 3. 2. The S1D13515/S2D13515 does not support Big Endian configuration. The host processor must be configured for Little Endian External Bus when connected to the S1D13515/S2D13515 using the MPC555 interface. 70 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-18: Direct/Indirect Freescale MPC555 Host Interface Write Timing (Burst Mode) Symbol fCLKOUT t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t18 t24 t25 t26 t27 t28 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[11:31], M/R#, RD/WR#, TSIZ[0:1] setup A[11:31], M/R#, RD/WR#, TSIZ[0:1] hold CS# setup CS# hold TS# setup TS# hold CLKOUT to TA#, TEA# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to TA#, TEA# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to TA#, TEA# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge CLKOUT to TA#, TEA# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to D[0:15] hold BURST# setup BURST# hold BDIP# setup BDIP# hold D[0:15] setup to CLKOUT Hardware Functional Specification Rev. 1.7 EPSON HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — Units MHz ns ns ns ns ns ns ns ns ns 4 24 4 21 ns 4 23 4 21 ns — 20 — 17 ns — 19 — 17 ns 6 20 5 17 ns 5 19 5 17 ns 4 24 4 21 ns 4 0 7 0 8 0 0 23 — — — — — — 4 0 7 0 8 0 0 20 — — — — — — ns ns ns ns ns ns ns 71 Chapter 7 A.C. Characteristics t1 S1D13515/S2D13515 t2 t3 CLKOUT A[11:31] M/R# RD/WR# TSIZ[0:1] t4 t5 t6 t7 CS# t8 t9 TS# t13 t11 t12 t10 TA# TEA# (see Note) Hi-Z Hi-Z t24 t25 BURST# t26 t27 BDIP# t20 t19 D[0:15] Hi-Z Invalid Valid t21 t29 Invalid Valid Hi-Z Note: TEA# has a mild pull-down resistance and is never driven low. If ERR_ACK# is used, an external pull-up resistor (typically 10K ohm) should be connected. Figure 7-18: Direct/Indirect Freescale MPC555 Host Interface Read Timing (Burst Mode) Note 1. For Indirect MPC555, the TSIZ0 pin should be tied to “1” and TSIZ1 should be tied to “0” (16-bit host access is mandatory). For byte access in this mode, refer to Section 21.9, “MPC555 Interface” on page 521 note 3. 2. The S1D13515/S2D13515 does not support Big Endian configuration. The host processor must be configured for Little Endian External Bus when connected to the S1D13515/S2D13515 using the MPC555 interface. 72 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-19: Direct/Indirect Freescale MPC555 Host Interface Read Timing (Burst Mode) Symbol fCLKOUT t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t19 t20 t21 t24 t25 t26 t27 t29 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[11:31], M/R#, RD/WR#, TSIZ[0:1] setup A[11:31], M/R#, RD/WR#, TSIZ[0:1] hold CS# setup CS# hold TS# setup TS# hold CLKOUT to TA#, TEA# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to TA#, TEA# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to TA#, TEA# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge CLKOUT to TA#, TEA# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to D[0:15] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to D[0:15] valid for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to D[0:15] tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b BURST# setup BURST# hold BDIP# setup BDIP# hold CLKOUT to D[0:15] delay for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Hardware Functional Specification Rev. 1.7 EPSON HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — Units MHz ns ns ns ns ns ns ns ns ns 4 24 4 21 ns 4 23 4 21 ns — 20 — 17 ns — 19 — 17 ns 6 20 5 17 ns 5 19 5 17 ns 4 24 4 21 ns 4 23 4 20 ns 5 — 5 — ns 5 — 5 — ns — 20 — 17 ns — 19 — 16 ns 5 25 5 23 ns 5 7 0 8 0 24 — — — — 5 7 0 8 0 22 — — — — ns ns ns ns ns 5 — 5 — ns 5 — 5 — ns 73 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.7 Direct/Indirect TI TSM470 (Non-burst Mode) t1 t2 t3 1st 2nd EBI_CLK t4 t5 t6 t7 A[19:1] M/R# UB#,LB# CS# t26 t25 RD/WR# t8 t9 TS# t11 t10 TA# ERR_ACK# (see Note) t13 t12 Hi-Z Hi-Z t19 t20 BURST# t17 D[15:0] t18 Hi-Z Valid Hi-Z Note: ERR_ACK# has a mild pull-down resistance and is never driven low. If ERR_ACK# is used, an external pull-up resistor (typically 10K ohm) should be connected. Figure 7-19: Direct/Indirect TI TSM470 Host Interface Write Timing (Non-burst Mode) Note For Indirect TI TMS470, the UB# and LB# pins should be tied to “0’ (16-bit host access is mandatory). For byte access in this mode, refer to Section 21.8, “TI TMS470 Interface” on page 520, note 3. 74 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-20: Direct/Indirect TI TSM470 Host Interface Write Timing (Non-burst Mode) Symbol fEBI_CLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t17 t18 t19 t20 t25 t26 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[19:1], M/R#, UB#/LB# setup A[19:1], M/R#, UB#/LB# hold CS# setup CS# hold TS# setup TS# hold EBI_CLK to TA#, ERR_ACK# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to TA#, ERR_ACK# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to TA#, ERR_ACK# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge EBI_CLK to TA#, ERR_ACK# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b D[15:0] setup to 1st EBI_CLK after TS#=0 EBI_CLK to D[15:0] hold BURST# setup BURST# hold RD/WR# setup RD/WR# hold Hardware Functional Specification Rev. 1.7 EPSON HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — Units MHz ns ns ns ns ns ns ns ns ns 4 24 4 22 ns 4 23 4 21 ns — 20 — 17 ns — 19 — 17 ns 6 20 5 17 ns 5 19 5 17 ns 4 24 4 21 ns 4 0 0 7 0 7 0 23 — — — — — — 4 0 0 7 0 7 0 20 — — — — — — ns ns ns ns ns ns ns 75 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t2 t3 1st 2nd EBI_CLK A[19:1] M/R# UB#,LB# t4 t5 t6 t7 t25 t26 CS# OE# t8 t9 TS# t11 t10 TA# ERR_ACK# (see Note) t13 t12 Hi-Z Hi-Z t22 t23 BURST# t20 t19 D[15:0] Hi-Z Invalid t21 Valid Hi-Z Note: ERR_ACK# has a mild pull-down resistance and is never driven low. If ERR_ACK# is used, an external pull-up resistor (typically 10K ohm) should be connected. Figure 7-20: Direct/Indirect TI TSM470 Host Interface Read Timing (Non-burst Mode) Note For Indirect TI TMS470, the UB# and LB# pins should be tied to “0’ (16-bit host access is mandatory). For byte access in this mode, refer to Section 21.8, “TI TMS470 Interface” on page 520, note 3. 76 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-21: Direct/Indirect TI TSM470 Host Interface Read Timing (Non-burst Mode) Symbol fEBI_CLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t19 t20 t21 t22 t23 t25 t26 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[19:1], M/R#, UB#/LB# setup A[19:1], M/R#, UB#/LB# hold CS# setup CS# hold TS# setup TS# hold EBI_CLK to TA#, ERR_ACK# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to TA#, ERR_ACK# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to TA#, ERR_ACK# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge EBI_CLK to TA#, ERR_ACK# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to D[15:0] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to D[15:0] valid for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to D[15:0] tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b BURST# setup BURST# hold OE# setup OE# hold Hardware Functional Specification Rev. 1.7 EPSON HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — Units MHz ns ns ns ns ns ns ns ns ns 4 24 4 22 ns 4 23 4 21 ns — 20 — 17 ns — 19 — 17 ns 6 20 5 17 ns 5 19 5 17 ns 4 24 4 21 ns 4 23 4 20 ns 4 — 4 — ns 4 — 4 — ns — 20 — 17 ns — 19 — 17 ns 4 25 4 23 ns 4 7 0 10 0 24 — — — — 4 7 0 10 0 22 — — — — ns ns ns ns ns 77 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.8 Direct/Indirect TI TSM470 (Burst Mode) t1 t2 t3 EBI_CLK A[19:1] M/R# UB#,LB# t4 t5 t6 t7 t25 t26 CS# RD/WR# t8 t9 TS# TA# ERR_ACK# (see Note) t13 t11 t10 t12 Hi-Z Hi-Z t19 t20 BURST# t28 t27 BDIP# t17 D[15:0] t18 t17 Valid[15:0] Valid[31:16] Note: ERR_ACK# has a mild pull-down resistance and is never driven low. If ERR_ACK# is used, an external pull-up resistor (typically 10K ohm) should be connected. Figure 7-21: Direct/Indirect TI TSM470 Host Interface Write Timing (Burst Mode) Note For Indirect TI TMS470, the UB# and LB# pins should be tied to “0’ (16-bit host access is mandatory). For byte access in this mode, refer to Section 21.8, “TI TMS470 Interface” on page 520, note 3. 78 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-22: Direct/Indirect TI TSM470 Host Interface Write Timing (Burst Mode) Symbol fEBI_CLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t17 t18 t19 t20 t25 t26 t27 t28 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[19:1], M/R#, UB#/LB# setup A[19:1], M/R#, UB#/LB# hold CS# setup CS# hold TS# setup TS# hold EBI_CLK to TA#, ERR_ACK# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to TA#, ERR_ACK# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to TA#, ERR_ACK# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge EBI_CLK to TA#, ERR_ACK# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b D[15:0] setup to EBI_CLK EBI_CLK to D[15:0] hold BURST# setup BURST# hold RD/WR# setup RD/WR# hold BDIP# setup BDIP# hold Hardware Functional Specification Rev. 1.7 EPSON HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — Units MHz ns ns ns ns ns ns ns ns ns 4 24 4 22 ns 4 23 4 21 ns — 20 — 17 ns — 19 — 17 ns 6 20 5 17 ns 5 19 5 17 ns 4 24 4 21 ns 4 0 0 7 0 7 0 8 0 23 — — — — — — — — 4 0 0 7 0 7 0 8 0 20 — — — — — — — — ns ns ns ns ns ns ns ns ns 79 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t2 t3 EBI_CLK t4 t5 t6 t7 t25 t26 A[19:1] M/R# UB#/LB# CS# OE# t8 t9 TS# t12 t10 TA# ERR_ACK# (see Note) t13 t11 t11 Hi-Z Hi-Z t22 t23 BURST# t27 t28 BDIP# t20 t19 D[15:0] Hi-Z Invalid Valid[15:0] t20 t29 Invalid t21 Valid[31:16] Hi-Z Note: ERR_ACK# has a mild pull-down resistance and is never driven low. If ERR_ACK# is used, an external pull-up resistor (typically 10K ohm) should be connected. Figure 7-22: Direct/Indirect TI TSM470 Host Interface Read Timing (Burst Mode) Note For Indirect TI TMS470, the UB# and LB# pins should be tied to “0’ (16-bit host access is mandatory). For byte access in this mode, refer to Section 21.8, “TI TMS470 Interface” on page 520, note 3. 80 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-23: Direct/Indirect TI TSM470 Host Interface Read Timing (Burst Mode) Symbol fEBI_CLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t19 t20 t21 t22 t23 t25 t26 t27 t28 t29 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[19:1], M/R#, UB#/LB# setup A[19:1], M/R#, UB#/LB# hold CS# setup CS# hold TS# setup TS# hold EBI_CLK to TA#, ERR_ACK# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to TA#, ERR_ACK# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to TA#, ERR_ACK# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge EBI_CLK to TA#, ERR_ACK# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to D[15:0] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to D[15:0] valid for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b EBI_CLK to D[15:0] tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b BURST# setup BURST# hold OE# setup OE# hold BDIP# setup BDIP# hold EBI_CLK to D[15:0] delay for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Hardware Functional Specification Rev. 1.7 EPSON HIOVDD = 2.5V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — HIOVDD = 3.3V Min Max — 25 40 — 20 — 20 — 7 — 0 — 5 — 0 — 8 — 0 — Units MHz ns ns ns ns ns ns ns ns ns 4 24 4 22 ns 4 23 4 21 ns — 20 — 17 ns — 19 — 17 ns 6 20 5 17 ns 5 19 5 17 ns 4 24 4 21 ns 4 23 4 20 ns 4 — 4 — ns 4 — 4 — ns — 20 — 17 ns — 19 — 17 ns 4 25 4 23 ns 4 7 0 10 0 8 0 24 — — — — — — 4 7 0 10 0 8 0 22 — — — — — — ns ns ns ns ns ns ns 4 — 4 — ns 4 — 4 — ns 81 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.9 Direct/Indirect NEC V850 Type 1 t1 t2 t3 1st CLKOUT t4 t5 t6 t7 A[20:0] M/R# UBEN#/LBEN# CS# t24 t25 t8 R/W# t9 DSTB# t10 WAIT# t11 t12 Hi-Z Hi-Z t18 t17 AD[15:0] t13 Hi-Z Hi-Z Valid Figure 7-23: Direct/Indirect NEC V850 Type 1 Host Interface Write Timing Note For Indirect NECV850 Type #1 8-bit, the UBEN# and LBEN# pins are not used. For Indirect NECV850 Type #1 16-bit, the UBEN# and LBEN# pins should be tied to logic 0. For byte access in this mode, refer to Section 21.4, “NEC V850 Type1 Interface” on page 516, note 2. 82 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-24: Direct/Indirect NEC V850 Type 1 Host Interface Write Timing Symbol fCLKOUT t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t17 t18 t24 t25 HIOVDD = 2.5V Min Max — 20 50 — 25 — 25 — 10 — 0 — 10 — 0 — 11 — -8 — Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:0], M/R#, UBEN#/LBEN# setup A[20:0], M/R#, UBEN#/LBEN# hold CS# setup CS# hold DSTB# setup DSTB# hold DSTB# falling edge to WAIT# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to WAIT# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DSTB# rising edge to WAIT# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to WAIT# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b AD[15:0] write data setup to 1st CLKOUT DSTB# rising edge to AD[15:0] hold R/W# setup R/W# hold HIOVDD = 3.3V Min Max — 20 50 — 25 — 25 — 10 — 0 — 10 — 0 — 11 — -8 — Units MHz ns ns ns ns ns ns ns ns ns 6 28 6 25 ns 5 27 5 24 ns — 20 — 17 ns — 19 — 17 ns 2 19 2 19 ns 2 19 2 19 ns 4 — 4 — ns 4 0 0 10 0 — — — — — 4 0 0 10 0 — — — — — ns ns ns ns ns Note 1. When the CLKOUT period (t1) is short, the V850 may sample an invalid WAIT# status because of the t10 timing. To allow the V850 to sample the WAIT# status correctly, a programmable wait must be inserted. The programmable wait is controlled by the V850 Data Wait Control Register (DWC). For details on V850 registers, refer to the V850 specification. 2. When the S1D13515/S2D13515 completes a write, WAIT# is driven high and then asserted low 1 CLKOUT later. This means that WAIT# is only high for a 1 CLKOUT period. To sample WAIT# high correctly, the V850 Data Wait Control Register (DWC) must be set appropriately. For details on V850 registers, refer to the V850 specification. Hardware Functional Specification Rev. 1.7 EPSON 83 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t2 t3 1st CLKOUT t4 t5 t6 t7 t24 t25 A[20:0] M/R# UBEN#/LBEN# CS# R/W# t9 t8 DSTB# t12 t11 t10 WAIT# Hi-Z Hi-Z t21 t20 t19 AD[15:0] t13 Hi-Z Invalid Valid Hi-Z Figure 7-24: Direct/Indirect NEC V850 Type 1 Host Interface Read Timing Note For Indirect NECV850 Type #1 8-bit, the UBEN# and LBEN# pins are not used. For Indirect NECV850 Type #1 16-bit, the UBEN# and LBEN# pins should be tied to logic 0. For byte access in this mode, refer to Section 21.4, “NEC V850 Type1 Interface” on page 516, note 2. 84 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-25: Direct/Indirect NEC V850 Type 1 Host Interface Read Timing Symbol fCLKOUT t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t19 t20 t21 t24 t25 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:0], M/R#, UBEN#/LBEN# setup A[20:0], M/R#, UBEN#/LBEN# hold CS# setup CS# hold DSTB# setup DSTB# hold DSTB# falling edge to WAIT# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to WAIT# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b DSTB# rising edge to WAIT# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to WAIT# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge CLKOUT to AD[15:0] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to AD[15:0] valid for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge CLKOUT to AD[15:0] tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b R/W# setup R/W# hold HIOVDD = 2.5V Min Max — 20 50 — 25 — 25 — 10 — 0 — 10 — 0 — 11 — -8 — HIOVDD = 3.3V Min Max — 20 50 — 25 — 25 — 10 — 0 — 10 — 0 — 11 — -8 — Units MHz ns ns ns ns ns ns ns ns ns 6 28 6 25 ns 5 27 5 24 ns — 20 — 17 ns — 19 — 17 ns 2 19 2 19 ns 2 19 2 19 ns 4 — 4 — ns 4 — 4 — ns 2 — 2 — ns 2 — 2 — ns — 20 — 17 ns — 19 — 16 ns 2 22 2 19 ns 2 10 0 21 — — 2 10 0 18 — — ns ns ns Note 1. When the CLKOUT period (t1) is short, the V850 may sample an invalid WAIT# status because of the t10 timing. To allow the V850 to sample the WAIT# status correctly, a programmable wait must be inserted. The programmable wait is controlled by the V850 Data Wait Control Register (DWC). For details on V850 registers, refer to the V850 specification. 2. When read data is ready, WAIT# is driven high and then asserted low 1 CLKOUT later. This means that WAIT# is only high for a 1 CLKOUT period. To sample WAIT# high correctly, the V850 Data Wait Control Register (DWC) must be set appropriately. For details on V850 registers, refer to the V850 specification. Hardware Functional Specification Rev. 1.7 EPSON 85 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.4.10 Direct/Indirect NEC V850 Type 2 t1 t2 t3 1st CLKOUT t5 t4 A[20:0] M/R# t7 t6 CS# t8 t9 WRH# WRL# t12 t10 WAIT# t11 Hi-Z Hi-Z t18 t17 AD[15:0] t13 Hi-Z Hi-Z Valid Figure 7-25: Direct/Indirect NEC V850 Type 2 Host Interface Write Timing Note For Indirect NEC V850 Type #2 8-bit, the WRH# is not used. For Indirect NEC V850 Type #2 16-bit, the WRH# and WRL# pins should be driven in unison (16-bit host write access is mandatory). For byte access in this mode, refer to Section 21.5, “NEC V850 Type2 Interface” on page 517, note 2. 86 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-26: Direct/Indirect NEC V850 Type 2 Host Interface Write Timing Symbol fCLKOUT t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t17 t18 HIOVDD = 2.5V Min Max — 20 50 — 25 — 25 — 10 — 0 — 10 — 0 — 8 — -8 — Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:0], M/R# setup A[20:0], M/R# hold CS# setup CS# hold WRL#/WRH# setup WRL#/WRH# hold WRL#/WRH# falling edge to WAIT# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to WAIT# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b WRL#/WRH# rising edge to WAIT# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to WAIT# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b AD[15:0] write data setup to 1st CLKOUT WRL#/WRH# rising edge to AD[15:0] hold HIOVDD = 3.3V Min Max — 20 50 — 25 — 25 — 10 — 0 — 10 — 0 — 8 — -8 — Units MHz ns ns ns ns ns ns ns ns ns 6 24 6 21 ns 5 23 5 20 ns — 20 — 17 ns — 19 — 17 ns 2 16 2 15 ns 2 16 2 15 ns 4 — 4 — ns 4 0 0 — — — 4 0 0 — — — ns ns ns Note 1. When the CLKOUT period (t1) is short, the V850 may sample an invalid WAIT# status because of the t10 timing. To allow the V850 to sample the WAIT# status correctly, a programmable wait must be inserted. The programmable wait is controlled by the V850 Data Wait Control Register (DWC). For details on V850 registers, refer to the V850 specification. 2. When the S1D13515/S2D13515 completes a write, WAIT# is driven high and then asserted low 1 CLKOUT later. This means that WAIT# is only high for a 1 CLKOUT period. To sample WAIT# high correctly, the V850 Data Wait Control Register (DWC) must be set appropriately. For details on V850 registers, refer to the V850 specification. Hardware Functional Specification Rev. 1.7 EPSON 87 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t2 t3 1st CLKOUT t5 t4 A[20:0] M/R# t7 t6 CS# t9 t8 RD# t12 t11 t10 WAIT# Hi-Z Hi-Z Hi-Z t21 t20 t19 AD[15:0] t13 Invalid Valid Hi-Z Figure 7-26: Direct/Indirect NEC V850 Type 2 Host Interface Read Timing Note For Indirect NEC V850 Type #2 8-bit, the WRH# is not used. For Indirect NEC V850 Type #2 16-bit, the WRH# and WRL# pins should be driven in unison (16-bit host write access is mandatory). For byte access in this mode, refer to Section 21.5, “NEC V850 Type2 Interface” on page 517, note 2. 88 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-27: Direct/Indirect NEC V850 Type 2 Host Interface Read Timing Symbol fCLKOUT t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t19 t20 t21 Parameter Clock frequency Clock period Clock pulse width high Clock pulse width low A[20:0], M/R# setup A[20:0], M/R# hold CS# setup CS# hold RD# setup RD# hold RD# falling edge to WAIT# driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to WAIT# high for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b RD# rising edge to WAIT# tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to WAIT# low for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge CLKOUT to AD[15:0] driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b CLKOUT to AD[15:0] valid for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b Negative edge CLKOUT to AD[15:0] tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b HIOVDD = 2.5V Min Max — 20 50 — 25 — 25 — 10 — 0 — 10 — 0 — 11 — -8 — HIOVDD = 3.3V Min Max — 20 50 — 25 — 25 — 10 — 0 — 10 — 0 — 11 — -8 — Units MHz ns ns ns ns ns ns ns ns ns 8 28 7 25 ns 7 27 7 24 ns — 20 — 17 ns — 19 — 17 ns 4 19 4 19 ns 4 19 4 19 ns 4 — 4 — ns 4 — 4 — ns 2 — 2 — ns 2 — 2 — ns — 20 — 17 ns — 19 — 16 ns 2 22 2 19 ns 2 21 2 18 ns Note 1. When the CLKOUT period (t1) is short, the V850 may sample an invalid WAIT# status because of the t10 timing. To allow the V850 to sample the WAIT# status correctly, a programmable wait must be inserted. The programmable wait is controlled by the V850 Data Wait Control Register (DWC). For details on V850 registers, refer to the V850 specification. 2. When read data is ready, WAIT# is driven high and then asserted low 1 CLKOUT later. This means that WAIT# is only high for a 1 CLKOUT period. To sample WAIT# high correctly, the V850 Data Wait Control Register (DWC) must be set appropriately. For details on V850 registers, refer to the V850 specification. Hardware Functional Specification Rev. 1.7 EPSON 89 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.5 Serial Host Bus Interface Timing 7.5.1 SPI The SPI host module requires a valid clock selection before the interface can operate. The SPI host module clock selection is determined by a combination of SPICLKEN (AB5) pin and REG[0061h] bits 2 and 0. t4 HSCS# t1 tHSCK t2 HSCK tHSDIS tHSDIH HSDI Invalid t5 HSDO Hi-Z Invalid LSB MSB t3 tHSDOH LSB MSB Invalid Hi-Z Figure 7-27: SPI Host Interface Timing 90 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-28: SPI Host Interface Timing Symbol fHSCK tHSCK tHSDIS tHSDIH t1 HSCK Clock frequency HSCK Clock period (Note 2) HSDI data setup time HSDI data hold time HSDO data hold time for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b HSCS# falling edge to HSCK falling edge t2 HSCK rising edge to HSCS# rising edge tHSDOH t3 t4 t5 HIOVDD = 2.5V Min Max — 10 100 — 3 — 3 — Parameter HSCS# rising edge to HSDO tristate for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b HSCS# rising edge to HSCS# falling edge HSCS# falling edge to HSDO driven for REG[003Dh] bit 0 = 0b for REG[003Dh] bit 0 = 1b HIOVDD = 3.3V Min Max — 10 100 — 3 — 3 — Units MHz ns ns ns 5 — 5 — ns 5 5 — — 5 5 — — 2 — 2 — ns ns ClkSPI (Note1) 3 11 3 10 ns 3 1 11 — 3 1 10 — ns tHSCK 6 19 6 16 ns 5 18 5 16 ns 1. ClkSPI = SPI control module clock period 2. The user must select a HSCK (Serial Clock) frequency, ClkSPI (SPI control module clock) frequency and System Clock frequency that meet the following equation. For synchronous register access: 8 HSCK cycles ≥ X + 7 ClkSPI cycles + 5 System Clock cycles where X is: 0 if the DMA Controller is not running AND C33 processor is not running; 16 system clocks if the DMA Controller is transferring data AND [the C33 processor is not running OR the C33 processing is running but the Instruction Cache is disabled]; 64 system clocks if the C33 processor is running with the Instruction Cache enabled. For asynchronous register access: 8 HSCK cycles ≥ 7 ClkSPI cycles + 91ns Hardware Functional Specification Rev. 1.7 EPSON 91 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.5.2 I2C The I2C host module requires a valid clock selection before the interface can operate. The I2C host module clock selection is determined by a combination of I2CCLKEN (AB5) pin and REG[0063h] bits 2 and 0. t2 SDA t11 t7 t6 t8 t3 t9 t10 t5 SCL t4 t1 Figure 7-28: I2C Host Interface Timing Table 7-29: I2C Host Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Parameter SCL Frequency Bus Free time between a STOP and START condition Hold time for a START Condition SCL Low Width SCL High Width Setup time for a repeated START Condition SDA setup time from SCL Rising SDA hold time to SCL Falling Rise Time of both SCL and SDA Fall Time of both SCL and SDA Setup time for a STOP Condition HIOVDD = 2.5V Min Max — 400 HIOVDD = 3.3V Min Max — 400 1.3 — 1.3 — μs 0.6 1.3 0.6 0.6 100 0 — — 0.6 — — — — — — 300 300 — 0.6 1.3 0.6 0.6 100 0 — — 0.6 — — — — — — 300 300 — μs μs μs μs Units KHz ns μs ns ns μs The user must select a ClkI2C (I2C control module clock) frequency and System Clock frequency that meet the following equation. For synchronous register access: 8 SCL cycles ≥ X + 17 ClkI2C cycles + 5 System Clock cycles where X is: 0 if the DMA Controller is not running AND C33 processor is not running; 16 system clocks if the DMA Controller is transferring data AND [the C33 processor is not running OR the C33 processing is running but the Instruction Cache is disabled]; 64 system clocks if the C33 processor is running with the Instruction Cache enabled. For asynchronous register access: 8 SCL cycles ≥ 17 ClkI2C cycles + 91ns 92 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.6 Panel Interface Timing Note For XGA 1024x768 panel support, only single panel, single window with no virtual width function is supported (i.e. Blend Mode 0 with MAIN window only (AUX and OSD windows disabled) and Main Virtual Width, REG[0954h] ~ REG[0955h] is same as the Main Width, REG[0950h] REG[0951h]). Any additional accesses to DRAM could potentially result in internal bandwidth limitations and must be evaluated on a case-by-case situation to ensure bandwidth throughput availability. The following table contains recommended values for XGA panel support. Table 7-30: Recommended Settings for XGA Support DRAM CLK (MHz) PCLK (MHz) HT (REG[4020h] ~ REG[4021h]) VT Frame Rate (REG[402Ah] ~ REG[402Bh]) (Hz) 100 60 1280 774 60 100 50 1056 774 60 100 65 1402 774 60 7.6.1 Generic TFT Panel Timing HT HDPS VPW VPS VDPS HPS HPW VDP VT HDP Figure 7-29: Generic TFT Panel Timing Hardware Functional Specification Rev. 1.7 EPSON 93 Chapter 7 A.C. Characteristics S1D13515/S2D13515 Table 7-31: Generic TFT Panel Timing for LCD1 Symbol HT HDP HDPS HPW HPS VT VDP VDPS VPW VPS Description Horizontal Total (HSYNC period) Horizontal Display Period Horizontal Display Period Start Position Horizontal Pulse (HSYNC) Width Horizontal Pulse (HSYNC) Start Position Vertical Total (VSYNC period) Vertical Display Period Vertical Display Period Start Position Vertical Pulse (VSYNC) Width Vertical Pulse (VSYNC) Start Position Derived From (REG[4002h] bits 11-0) + 1 ((REG[4004h] bits 10-0) + 1) x 2 (REG[4006h] bits 11-0) + 1 (REG[4008h] bits 8-0) + 1 REG[400Ah] bits 11-0 (REG[400Ch] bits 11-0) + 1 (REG[400Eh] bits 11-0) + 1 REG[4010h] bits 11-0 (REG[4012h] bits 4-0) + 1 REG[4014h] bits 11-0 Units Tp Lines 1. Tp is the period of the pixel clock (1 / Fp) for LCD1. The frequency of the pixel clock (Fp) for LCD1 is determined by REG[003Ch] bit 2, REG[003Eh] bits 7-4, and REG[0030h]. 2. The following formulas must be valid for all panel timings: HPS + HDPS + HDP < HT VDPS + VDP < VT Table 7-32: Generic TFT Panel Timing for LCD2 Symbol HT HDP HDPS HPW HPS VT VDP VDPS VPW VPS Description Horizontal Total (HSYNC period) Horizontal Display Period Horizontal Display Period Start Position Horizontal Pulse (HSYNC) Width Horizontal Pulse (HSYNC) Start Position Vertical Total (VSYNC period) Vertical Display Period Vertical Display Period Start Position Vertical Pulse (VSYNC) Width Vertical Pulse (VSYNC) Start Position Derived From (REG[4020h] bits 11-0) + 1 ((REG[4022h] bits 10-0) + 1) x 2 (REG[4024h] bits 11-0) + 1 (REG[4026h] bits 8-0) + 1 REG[4028h] bits 11-0 (REG[402Ah] bits 11-0) + 1 (REG[402Ch] bits 11-0) + 1 REG[402Eh] bits 11-0 (REG[4030h] bits 4-0) + 1 REG[4032h] bits 11-0 Units Tp Lines 1. Tp is the period of the pixel clock (1 / Fp) for LCD2. The frequency of the pixel clock (Fp) for LCD2 is determined by REG[003Ch] bit 2, REG[003Eh] bits 7-4, and REG[0031h]. 2. The following formulas must be valid for all panel timings: HPS + HDPS + HDP < HT VDPS + VDP < VT 94 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Generic RGB Type Interface Panel Horizontal Timing VSYNC t1 HSYNC t2 t3 HSYNC t15 t5 t4 DE t6 t8 t7 Tp t10 t11 t12 PCLK t13 t14 RGB Data Invalid 1 2 Last Invalid Figure 7-30: Generic RGB Type Interface Panel Horizontal Timing Hardware Functional Specification Rev. 1.7 EPSON 95 Chapter 7 A.C. Characteristics S1D13515/S2D13515 Table 7-33: Generic RGB Type Interface Panel Horizontal Timing for LCD1 (FP1IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Tp t10 t11 t12 t13 t14 t15 Parameter VSYNC falling edge to HSYNC falling edge Horizontal total period HSYNC pulse width HSYNC falling edge to DRDY active Horizontal display period DE falling edge to HSYNC falling edge HSYNC setup time to PCLK falling edge DE setup to PCLK falling edge PCLK period PCLK pulse width high PCLK pulse width low DE hold from PCLK falling edge Data setup to PCLK falling edge Data hold from PCLK falling edge HSYNC hold time from PCLK falling edge Min — — — — — — 0.5Tp 0.5Tp 15.625 0.5Tp - 1.5ns 0.5Tp 0.5Tp - 5ns 0.5Tp - 2ns 0.5Tp - 5ns 0.5Tp - 3ns Typ HPS HT HPW HDPS HDP Note 2 0.5 0.5 — — — 0.5 0.5 0.5 0.5 Max — — — — — — — — — 0.5Tp 0.5Tp+1.5ns — — — — Units Tp (Note 1) Tp Tp Tp Tp Tp Tp Tp ns Tp Tp Tp Tp Tp Tp Table 7-34: Generic RGB Type Interface Panel Horizontal Timing for LCD2 (FP2IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Tp t10 t11 t12 t13 t14 t15 Parameter VSYNC falling edge to HSYNC falling edge Horizontal total period HSYNC pulse width HSYNC falling edge to DRDY active Horizontal display period DE falling edge to HSYNC falling edge HSYNC setup time to PCLK falling edge DE setup to PCLK falling edge PCLK period PCLK pulse width high PCLK pulse width low DE hold from PCLK falling edge Data setup to PCLK falling edge Data hold from PCLK falling edge HSYNC hold time from PCLK falling edge Min — — — — — — 0.5Tp - 2ns 0.5Tp - 2ns 13.89 0.5Tp - 0.5ns 0.5Tp 0.5Tp - 2ns 0.5Tp - 2ns 0.5Tp - 2ns 0.5Tp - 1ns Typ HPS HT HPW HDPS HDP Note 2 0.5 0.5 — — — 0.5 0.5 0.5 0.5 Max — — — — — — — — — 0.5Tp 0.5Tp+0.5ns — — — — Units Tp (Note 1) Tp Tp Tp Tp Tp Tp Tp ns Tp Tp Tp Tp Tp Tp 1. Tp = pixel clock period 2. t6typ = t2 - t4 - t5 3. The Generic TFT timing diagrams assume the following polarity of signals: VSYNC Pulse Polarity bit is active low. HSYNC Pulse Polarity bit is active low. PCLK Polarity is programmed so that all panel interface signals change at the falling edge of PCLK. 96 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Generic RGB Type Interface Panel Vertical Timing t1 t2 VSYNC HSYNC t3 RGB Data Invalid t4 Line1 Last Invalid DE t5 t6 PCLK Figure 7-31: Generic RGB Type Interface Panel Vertical timing Table 7-35: Generic RGB Type Interface Panel Vertical Timing for LCD1 (FP1IO*) Symbol t1 t2 t3 t4 t5 t6 Parameter Vertical total period VSYNC pulse width Vertical display start position (Note 1) Vertical display period VSYNC setup to PCLK falling edge VSYNC hold from PCLK falling edge Min — — — — 0.5Tp - 1ns 0.5Tp - 3ns Typ VT VPW Note 2 VDP 0.5 0.5 Max — — — — — — Units Lines Lines Lines Lines Tp Tp Table 7-36: Generic RGB Type Interface Panel Vertical Timing for LCD2 (FP2IO*) Symbol t1 t2 t3 t4 t5 t6 Parameter Vertical total period VSYNC pulse width Vertical display start position (Note 1) Vertical display period VSYNC setup to PCLK falling edge VSYNC hold from PCLK falling edge Min — — — — 0.5Tp - 2ns 0.5Tp - 1ns Typ VT VPW Note 2 VDP 0.5 0.5 Max — — — — — — Units Lines Lines Lines Lines Tp Tp 1. t3 is measured from the first HSYNC pulse after the start of the frame to the first HSYNC pulse when RGB Data is valid. 2. t3typ = VDPS - VPS Hardware Functional Specification Rev. 1.7 EPSON 97 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.6.2 ND-TFD 8-Bit Serial Interface Timing t8 LCD Command/Parameter Transfer SCS (LCD1=FP1IO11,FP1IO10) LCD2=FP2IO18) SDA0 (LCD1=FP1IO18) (LCD2=FP2IO20) t1 SDO (LCD1=FP1IO19,FP1IO16) (LCD2=FP2IO21) SDO (LCD1=FP1IO18,FP1IO16) (LCD2=FP2IO21) t7 (MSB first) D7 D6 D5 D4 D3 D2 D1 D0 (LSB first) D0 D1 D2 t2 t3 D3 D4 D5 D6 D7 SCK (LCD1=FP1IO17,FP1IO13) (LCD2=FP2IO19) (PHA = 1, POL = 0) (PHA = 1, POL = 1) (PHA = 0, POL = 0) (PHA = 0, POL = 1) t4 t5 t6 PHA: Serial Clock Phase (REG[4016h] bit 1 for LCD1, REG[4034h] bit 1 for LCD2) POL: Serial Clock Polarity (REG[4016h] bit 0 for LCD1, REG[4034h] bit 0 for LCD2) Figure 7-32: ND-TFD 8-Bit Serial Interface Timing 98 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-37: ND-TFD 8-Bit Serial Interface Timing for LCD1(FP1IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter SCS/SDA0 setup time Data setup time Data hold time Serial clock pulse width low (high) Serial clock pulse width high (low) Serial clock period SCS/SDA0 hold time Chip select de-assert to reassert Min 1.5Ts - 3ns 0.5Ts - 3ns 0.5Ts - 2ns 0.5Ts - 3ns 0.5Ts - 3ns — 1.5Ts -2ns — Typ 1.5 0.5 0.5 0.5 0.5 1 1.5 Note 2 Max — — — 0.5Ts + 3ns 0.5Ts + 3ns — — — Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts Table 7-38: ND-TFD 8-Bit Serial Interface Timing for LCD2(FP2IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter SCS/SDA0 setup time Data setup time Data hold time Serial clock pulse width low (high) Serial clock pulse width high (low) Serial clock period SCS/SDA0 hold time Chip select de-assert to reassert Min 1.5Ts - 2ns 0.5Ts - 1ns 0.5Ts 0.5Ts - 1ns 0.5Ts - 1ns — 1.5Ts — Typ 1.5 0.5 0.5 0.5 0.5 1 1.5 Note 2 Max — — — 0.5Ts + 1ns 0.5Ts + 1ns — — — Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts 1. Ts = Serial clock period 2. This result is software dependent, based on host register access latency. Hardware Functional Specification Rev. 1.7 EPSON 99 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.6.3 ND-TFD 9-Bit Serial Interface Timing t8 LCD Command/Parameter Transfer SCS (LCD1=FP1IO11,FP1IO10) LCD2=FP2IO18) t7 t1 SDO (LCD1=FP1IO19,FP1IO16) (LCD2=FP2IO21) SDO (LCD1=FP1IO19,FP1IO16) (LCD2=FP2IO21) (MSB first) P/C D7 D6 D5 D4 D3 D2 D1 D0 (LSB first) P/C D0 D1 D2 D3 D4 D5 D6 D7 SCK t2 t3 (LCD1=FP1IO17,FP1IO13) (LCD2=FP2IO19) (PHA = 1, POL = 0) (PHA = 1, POL = 1) (PHA = 0, POL = 0) (PHA = 0, POL = 1) t4 t5 t6 PHA: Serial Clock Phase (REG[4016h] bit 1 for LCD1, REG[4034h] bit 1 for LCD2) POL: Serial Clock Polarity (REG[4016h] bit 0 for LCD1, REG[4034h] bit 0 for LCD2) Figure 7-33: ND-TFD 9-Bit Serial Interface Timing 100 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-39: ND-TFD 9-Bit Serial Interface Timing for LCD1 (FP1IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter Chip select setup time Data setup time Data hold time Serial clock pulse width low (high) Serial clock pulse width high (low) Serial clock period Chip select hold time Chip select de-assert to reassert Min 1.5Ts - 3ns 0.5Ts - 3ns 0.5Ts - 2ns 0.5Ts - 3ns 0.5Ts - 3ns — 1.5Ts - 2ns — Typ 1.5 0.5 0.5 0.5 0.5 1 1.5 Note 2 Max — — — 0.5Ts + 3ns 0.5Ts + 3ns — — — Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts Table 7-40: ND-TFD 9-Bit Serial Interface Timing for LCD1 (FP2IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter Chip select setup time Data setup time Data hold time Serial clock pulse width low (high) Serial clock pulse width high (low) Serial clock period Chip select hold time Chip select de-assert to reassert Min 1.5Ts - 2ns 0.5Ts - 1ns 0.5Ts 0.5Ts - 1ns 0.5Ts - 1ns — 1.5Ts — Typ 1.5 0.5 0.5 0.5 0.5 1 1.5 Note 2 Max — — — 0.5Ts + 1ns 0.5Ts + 1ns — — — Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts 1. Ts = Serial clock period 2. This result is software dependent, based on host register access latency. Hardware Functional Specification Rev. 1.7 EPSON 101 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.6.4 a-Si TFT Serial Interface Timing t7 SCS (LCD1=FP1IO11,FP1IO10) LCD2=FP2IO18) SDO (LCD1=FP1IO19,FP1IO16) (LCD2=FP2IO21) Invalid D0 t8 D1 D2 t1 t2 D3 D4 D5 D6 D7 t6 SCK (LCD1=FP1IO17,FP1IO13) (LCD2=FP2IO19) t3 t4 t5 Note: The a-Si interface is affected by REG[4016h] / REG[4034h] bits 4 and 1-0. For these AC timings, REG[4016h] / REG[4034h] bit 4 = 1b and REG[4016h] / REG[4034h] bits 1-0 = 00b. Figure 7-34: a-Si TFT Serial Interface Timing Table 7-41: a-Si TFT Serial Interface Timing for LCD1 (FP1IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter Data Setup Time Data Hold Time Serial clock plus low period Serial clock pulse high period Serial clock period Chip select hold time Chip select de-assert to reassert SCK rising edge to SCS (strobe) falling edge Min 0.5Ts - 3ns 0.5Ts - 2ns 0.5Ts - 3ns 0.5Ts - 3ns — 1.5Ts - 2ns — — Typ 0.5 0.5 0.5 0.5 1 1.5 Note 2 0.5 Max — — 0.5Ts + 3ns 0.5Ts + 3ns — — — 0.5Ts + 3ns Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts Table 7-42: a-Si TFT Serial Interface Timing for LCD1 (FP2IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter Data Setup Time Data Hold Time Serial clock plus low period Serial clock pulse high period Serial clock period Chip select hold time Chip select de-assert to reassert SCK rising edge to SCS (strobe) falling edge Min 0.5Ts - 1ns 0.5Ts 0.5Ts - 1ns 0.5Ts - 1ns — 1.5Ts — — Typ 0.5 0.5 0.5 0.5 1 1.5 Note 2 0.5 Max — — 0.5Ts + 1ns 0.5Ts + 1ns — — — 0.5Ts + 2ns Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts 1. Ts = Serial clock period 2. This setting depends on software. 102 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.6.5 uWIRE Serial Interface Timing t8 SCS (LCD1=FP1IO11,FP1IO10) LCD2=FP2IO18) t7 t2 t1 SCK (LCD1=FP1IO17,FP1IO13) (LCD2=FP2IO19) t3 t4 (PHA = 1, POL = 0) t5 t6 SDO (LCD1=FP1IO19,FP1IO16) (LCD2=FP2IO21) Invalid A7 A6 A0 D7 D6 D0 Note: The uWIRE interface is affected by REG[4016h] / REG[4034h] bits 4 and 1-0. For these AC timings, REG[4016h] / REG[4034h] bit 4 = 0b and REG[4016h] / REG[4034h] bits 1-0 = 10b. Figure 7-35: uWIRE Serial Interface Timing Table 7-43: uWIRE Serial Interface Timing for LCD1 (FP1IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter Chip select setup time Serial clock Period Serial clock pulse width low Serial clock pulse width high Data setup time Data hold time Chip select hold time Chip select de-assert to reassert Min 1.5Ts - 3ns — 0.5Ts - 3ns 0.5Ts - 3ns 0.5Ts - 3ns 0.5Ts -2ns 1.5Ts - 2ns — Typ 1.5 1 0.5 0.5 0.5 0.5 1.5 Note 2 Max — — 0.5Ts + 3ns 0.5Ts + 3ns — — — — Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts Table 7-44: uWIRE Serial Interface Timing for LCD2 (FP2IO*) Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter Chip select setup time Serial clock Period Serial clock pulse width low Serial clock pulse width high Data setup time Data hold time Chip select hold time Chip select de-assert to reassert Min 1.5Ts - 2ns — 0.5Ts - 1ns 0.5Ts - 1ns 0.5Ts - 1ns 0.5Ts 1.5Ts — Typ 1.5 1 0.5 0.5 0.5 0.5 1.5 Note 2 Max — — 0.5Ts + 1ns 0.5Ts + 1ns — — — — Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts 1. Ts = Serial clock period 2. This setting depends on software Hardware Functional Specification Rev. 1.7 EPSON 103 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.6.6 24-Bit Serial Interface Timing t8 SCS (LCD1=FP1IO11,FP1IO10) LCD2=FP2IO18) t4 t5 t1 (see Note) SCK (LCD1=FP1IO17,FP1IO13) (LCD2=FP2IO19) t6 t7 (PHA = 0, POL = 0) t2 t3 SDO (LCD1=FP1IO19,FP1IO16) (LCD2=FP2IO21) Invalid D23 D22 D21 D3 D2 D1 D0 Note: The 24-bit serial interface is affected by REG[4016h] / REG[4034h] bits 4 and 1-0. For these AC timings, REG[4016h] / REG[4034h] bit 4 = 0b and REG[4016h] / REG[4034h] bits 1-0 = 00b. Figure 7-36: 24-Bit Serial Interface Timing Table 7-45: 24-bit Serial Interface Timing for LCD1 (FP1IO*) Symbol Parameter Min Typ Max t1 Chip select setup time 1.5Ts - 3ns 1.5 — t2 t3 t4 t5 t6 t7 t8 Data setup time Data hold time Chip select hold time Serial clock period Serial clock pulse low Serial clock pulse high Chip select de-assert to re-assert 0.5Ts - 3ns 0.5Ts - 2ns 1.5Ts - 2ns — 0.5Ts - 3ns 0.5Ts - 3ns — 0.5 0.5 1.5 1 0.5 0.5 Note 2 — — — — 0.5Ts + 3ns 0.5Ts + 3ns — Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts Table 7-46: 24-Bit Serial Interface Timing for LCD2 (FP2IO*) Symbol Parameter Min Typ Max t1 Chip select setup time 1.5Ts - 2ns 1.5 — t2 t3 t4 t5 t6 t7 t8 Data setup time Data hold time Chip select hold time Serial clock period Serial clock pulse low Serial clock pulse high Chip select de-assert to re-assert 0.5Ts - 1ns 0.5Ts 1.5Ts — 0.5Ts - 1ns 0.5Ts - 1ns — 0.5 0.5 1.5 1 0.5 0.5 Note 2 — — — — 0.5Ts + 1ns 0.5Ts + 1ns — Units Ts (Note 1) Ts Ts Ts Ts Ts Ts Ts 1. Ts = Serial clock period 2. This setting depends on software 104 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.6.7 Sharp DualView Panel Timing t1 t2 CK Tp t5 RGB Data t3 1 2 3 last t4 SPL SPR t7 t7 t6 t6 LS t8 CLS Note 2 t9 t9 VCOM VCOMB Figure 7-37: Sharp DualView Panel Horizontal Timing Table 7-47: Sharp DualView Panel Programmable Horizontal Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 Description Horizontal Total (LS period) CK Active Period Horizontal Display Period SPL/SPR Pulse Width Horizontal Display Period Start Position Horizontal Pulse (LS) Width Horizontal Pulse (LS) Start Position CLS Pulse Width VCOM/VCOMB Toggle Position Nominal (REG[4020h] bits 11-0) + 1 [((REG[4022h] bits 10-0) + 1) x 2] + 1 ((REG[4022h] bits 10-0) + 1) x 2 1 (REG[4024h] bits 11-0) +1 (REG[4026h] bits 8-0) + 1 REG[4056h] bits 7-0 (REG[4052h] bits 10-0) > 0 REG[4054h] bits 6-0 Units Tp 1. Tp = pixel clock period 2. CLS rising edge occurs at the same time as the LS falling edge. 3. The Sharp DualView horizontal timings are based on the following: LS (HSYNC) Pulse Polarity bit is active high. CK Pulse Polarity is 0b (REG[4001h] bit 7 = 0b) so all panel interface signals change at the falling edge of CK. Hardware Functional Specification Rev. 1.7 EPSON 105 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 t2 SPS t6 LS t3 t4 RGB Data Line 1 Last t5 VCOM VCOMB Figure 7-38: Sharp DualView Panel Vertical Timing Table 7-48: Sharp DualView Panel Programmable Vertical Timing Symbol t1 t2 t3 t4 Description Vertical Pulse (SPS) Width (see Note 7) Vertical Total (SPS period) Vertical Display Period Start Position (see Note 3) Vertical Display Period t5 Last pixel data to VCOM/VCOMB inversion t6 SPS falling edge to LS rising edge Nominal (REG[4030h] bits 4-0) + 1 (REG[402Ah] bits 11-0) + 1 Note 4 (REG[402Ch] bits 11-0) + 1 (REG[4020h] bits 11-0) (((REG[4022h] bits 10-0) + 1) x 2) (REG[4024h] bits 11-0) (REG[4028h] bits 11-0) + (REG[4056h] bits 7-0) Units Lines Tp 1. Tp = pixel clock period 2. The Sharp DualView vertical timings are based on the following: SPS (VSYNC) Pulse Polarity bit is active low. 3. t3 is measured from the first LS pulse after the start of the frame to the first LS pulse when RGB Data is valid. 4. t3 = (REG[402Eh] bits 11-0) - (REG[4032h] bits 11-0) 5. VCOM toggles every line (including non-display period). The Vertical Total Period (REG[402Ah] + 1) should be programmed to be an odd number of lines so that the logic of VCOM at the beginning of the next frame is opposite of the logic of VCOM at the beginning of the current frame. 6. VCOM and VCOMB are in phase at the start of frame (SPS going low) until the end of display period, and they are out of phase (180 degrees) during the non-display period. 7. t1 > t3 in order for VCOMB to be in phase with VCOM between SPS going low to the start of display period. 106 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Tp CK t2 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t3 LS CLS SPS SPR SPL RGB Data VCOM VCOMB Figure 7-39: Sharp DualView Panel Timing Hardware Functional Specification Rev. 1.7 EPSON 107 Chapter 7 A.C. Characteristics S1D13515/S2D13515 Table 7-49: Sharp DualView Panel Timing Symbol Tp t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 1. Tp 108 Parameter Pixel clock period Pixel clock pulse low Pixel clock pulse high LS setup before CK rising edge LS hold after CK rising edge CLS setup before CK rising edge CLS hold after CK rising edge SPS setup before CK rising edge SPS hold after CK rising edge SPR setup before CK rising edge SPR hold after CK rising edge SPL setup before CK rising edge SPL hold after CK rising edge Pixel Data setup before CK rising edge Pixel Data hold after CK rising edge VCOM setup before CK rising edge VCOM hold after CK rising edge VCOMB setup before CK rising edge VCOMB hold after CK rising edge Min 27.78 0.5Tp 0.5Tp 0.5Tp - 2ns 0.5Tp - 1ns 0.5Tp - 1ns 0.5Tp - 2ns 0.5Tp - 2ns 0.5Tp - 1ns 0.5Tp - 1ns 0.5Tp - 2ns 0.5Tp - 1ns 0.5Tp - 2ns 0.5Tp - 2ns 0.5Tp - 2ns 0.5Tp - 2ns 0.5Tp - 1ns 0.5Tp - 4ns 0.5Tp - 1ns Typ — — — 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 0.5Tp 0.5Tp+1.5ns 0.5Tp+1.5ns — — — — — — — — — — — — — — — — Units ns Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp = pixel clock period EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics VCOM VCOM INPHASE VCOMB INPHASE2 LS LS S1D13515/S2D13515 VCOMBSEL 1 VCOMB* 0 VCOM VCOMB INPHASE LS INPHASE2 VCOMBSEL VCOMB* Figure 7-40: Required External VCOMB Logic Hardware Functional Specification Rev. 1.7 EPSON 109 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.6.8 EID Double Screen Panel Timing (TCON Enabled) Note When using the EID Double Screen Panel with TCON enabled, the LCD2 Pixel Clock divide must be 1:1. tLED tLED tLEDLO LED_DIM_OUT tLEDHI Figure 7-41: EID Double Screen Panel LED_DIM_OUT Timing Table 7-50: EID Double Screen Panel LED_DIM_OUT Timing Symbol tLED tLEDHI tLEDLO Description LED clock period LED HIGH time LED LOW time Nominal 400 x 16 x (100-(REG[404Fh] bits 7-0)) [(REG[404Eh] bits 7-0) x 2] x 16 x (100-(REG[404Fh] bits 7-0)) tLED - tLEDHI Units Tp Tp Tp 1. Tp = pixel clock period 2. REG[404Fh] bits 7-0 = 98 max. If REG[404Fh] bits 7-0 > 98, it will be clipped internally to 98. 3. REG[404Eh] bits 7-0 should be < 200. If REG[404Eh] bits 7-0 > 200, it will be clipped internally to 200. 110 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Tp ODCLK (REG[4040h] bit 0 = 1) max PWCP + (VPW+1) line t1 + (HPS+20) clk ON_A t2 ON_B t3 ON_C t4 ON_D FLMF t5 Figure 7-42: EID Double Screen Panel Start-Up Control Signals Timing Table 7-51: EID Double Screen Panel Start-Up Control Signals Timing Symbol Tpwrclk t1 t2 t3 t4 t5 1. Tp 2. VT Description Period of internal PWR_CLK signal first ODCLK after Power On to ON_A ON_A high to ON_B high delay ON_B high to ON_C high delay ON_C to ON_D0 signal high delay FLMF (Vertical Total (VSYNC Period)) Min — — — — Tpwrclk + t5 — Typical 5,242,880 — 1 1 — VT Max Units — Tp 1 Tpwrclk — Tpwrclk — Tpwrclk Tpwrclk + 2(t5) — line = pixel clock period = Vertical Total (VSYNC Period) = (REG[402Ah] bits 7-0, REG[402Bh] bits 3-0) +1 Hardware Functional Specification Rev. 1.7 EPSON 111 Chapter 7 A.C. Characteristics S1D13515/S2D13515 Tp ODCLK (REG[4040h] bit 0 = 0) t1 ON_D t2 ON_C t3 ON_B t4 ON_A FLMF Figure 7-43: EID Double Screen Panel Shut-Down Control Signals Timing Table 7-52: EID Double Screen Panel Shut-Down Control Signals Timing Symbol Tpwrclk t1 t2 t3 t4 1. Tp 2. VT 112 Parameter Period of internal PWR_CLK signal Power Off to ON_D delay ON_D low to ON_C low delay ON_C low to ON_B low delay ON_B low to ON_A low delay Min — — — — — Typ 5,242,880 — 1 1 1 Max — VT + 17Tpwrclk — — — Units Tp Tpwrclk Tpwrclk Tpwrclk = pixel clock period = Vertical Total (VSYNC Period) = (REG[402Ah] bits 7-0, REG[402Bh] bits 3-0) +1 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics FLMF t1 EISF t2 t3 t4 RGB Data DEXR Invalid D1 D2 D3 Invalid Last t5 STRB t7 t6 OE t8 t9 CPV t10 POLGMA (1H/2H Inversion) t5/2 POLGMA (0.5HV Inversion) t11 Tp ODCLK Figure 7-44: EID Double Screen Panel Horizontal Timing Table 7-53: EID Double Screen Panel Horizontal Timing Symbol Tp t1 Description ODCLK - Pixel Clock FLMF rising edge to EISF rising edge t2 Horizontal Display Period Start Position t3 Horizontal Display Period t4 EISF pulse width t5 Horizontal Total (HSYNC period) t6 t7 t8 t9 t10 t11 OE low width STRB rising to FLMF falling, OE rising OE falling to CPV rising CPV high width POLGMA 1H/2H Inversion to STRB rising POLGMA 0.5HV Inversion 1. Tp Nominal Units 4 (REG[4024h] bits 7-0, REG[4025h] bits 3-0) - 1 (REG[4022h] bits 7-0, REG[4023h] bits 2-0) x 2 1 (REG[4020h] bits 7-0, REG[4021h] bits 3-0) + 1 REG[4046h] bits 7-0 10 2 50 3 REG[404Ah] bits 7-0 Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp = pixel clock period Hardware Functional Specification Rev. 1.7 EPSON 113 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t2 FLMF t1 EISF t3 t4 RGB Data Line 1 Line 2 Last STRB OE CPV POLGMA (1H Inversion) Low set POLGMA (2H Inversion) Low set POLGMA (0.5H Inversion) t5 t6 Low set t7 t8 POLGMA (1V Inversion) Figure 7-45: EID Double Screen Panel Vertical Timing Table 7-54: EID Double Screen Panel Vertical Timing Symbol 114 Description t1 FLMF pulse width t2 Vertical Total (VSYNC period) t3 Vertical Display Period Start Position t4 Vertical Display Period t5 t6 t7 t8 POLGMA 1H Inversion high width POLGMA 2H Inversion high width POLGMA 0.5H Inversion low width POLGMA 1V Inversion active to STRB falling EPSON Nominal 1 REG[402Ah] bits 7-0, REG[402Bh] bits 3-0) +1 [(REG[402Eh] bits 7-0, REG[402Fh] bits 3-0) - 1 REG[402Ch] bits 7-0, REG[402Dh] bits 3-0) +1 1 2 1 1 Units line line line line line line line line Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Note 1. EISF rising edge to Data/DEXR toggle timing Table 7-55: EISF Rising Edge to Data/DEXR Toggle Timing Hsync Polarity (REG[4027h] bit 7) EID TCON Input Sync Polarity EISF Rise Edge to Data/Dexr (REG[4041h] bit 4) Toggle Timing (H Back Porch) 0b 1b 0b HDPS 1b (Reserved) — 0b (Reserved) — 1b HDPS Unit clk clk Hsync Polarity (REG[4027h] bit 7) should be the same as EID TCON Input Sync Polarity (REG[4041h bit 4) If Hsync Polarity is set to 0b (active-low), EID TCON Input Sync Polarity should be 0b (active-low). If Hsync Polarity is set to 1b (active-high), EID TCON Input Sync Polarity should be 1b (active-high). 2. FLMF rising edge to Data/DEXR toggle timing Table 7-56: FLMF Rising Edge to Data/DEXR Toggle Timing Vsync Polarity (REG[4031h] bit 7) EID TCON Input Sync Polarity (REG[4041h] bit 4) FLMF Rise Edge to Data/Dexr Toggle Timing (V Back Porch) Unit 0b VDPS - 1 line 1b (Reserved) — 0b (Reserved) — 1b VDPS - 1 0b 1b line Vsync Polarity (REG[4031h] bit 7) should be the same as EID TCON Input Sync Polarity (REG[4041h bit 4) If Vsync Polarity is set to 0b (active-low), EID TCON Input Sync Polarity should be 0b (active-low). If Vsync Polarity is set to 1b (active-high), EID TCON Input Sync Polarity should be 1b (active-high). 3. Horizontal Sync Pulse Width REG[4026h] should be greater than 1 (HPW minimum is 2clk width). Vertical Sync Pulse Width REG[4030h] should be greater than 0 (VPW minimum is 1 line width). Hardware Functional Specification Rev. 1.7 EPSON 115 Chapter 7 A.C. Characteristics S1D13515/S2D13515 Tp ODCK t2 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t3 STRB FLMF EISF POLGMA DEXR RGB Data CPV OE Figure 7-46: EID Double Screen Panel Timing 116 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Table 7-57: EID Double Screen Panel Timing Symbol Tp t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 1. Tp Parameter Pixel clock period Pixel clock pulse low Pixel clock pulse high STRB setup before CK rising edge STRB hold after CK rising edge FLMF setup before CK rising edge FLMF hold after CK rising edge EISF setup before CK rising edge EISF hold after CK rising edge POLGMA setup before CK rising edge POLGMA hold after CK rising edge DEXR setup before CK rising edge DEXR hold after CK rising edge Pixel Data setup before CK rising edge Pixel Data hold after CK rising edge CPV setup before CK rising edge CPV hold after CK rising edge OE setup before CK rising edge OE hold after CK rising edge Min 27.78 0.5Tp 0.5Tp 0.5Tp - 2ns 0.5Tp 0.5Tp - 1ns 0.5Tp - 1ns 0.5Tp - 1ns 0.5Tp - 1ns 0.5Tp - 3ns 0.5Tp 0.5Tp - 4ns 0.5Tp 0.5Tp - 4ns 0.5Tp 0.5Tp - 4ns 0.5Tp 0.5Tp - 4ns 0.5Tp Typ — — — 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 0.5Tp 0.5Tp+1.5ns 0.5Tp+1.5ns — — — — — — — — — — — — — — — — Units ns Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp = pixel clock period Hardware Functional Specification Rev. 1.7 EPSON 117 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.7 Camera Interface Timing t4 CMxVREF / CMxFIELD (or CxVSIN / CxDEIN) t1 t3 t2 CMxHREF (or CxHSIN) CMxDAT[7:0] (or CxRIN* / CxGIN* / CxBIN*) Line1 Line2 Last t5 t6 t7 t8 t9 CMxCLKIN (or CxPCLKIN) CMxDAT[7:0] (or CxRIN* / CxGIN* / CxBIN*) t10 t11 CMxVREF/CMxFIELD/CMxHREF (or CxVSIN / CxDEIN / CxHSIN) Note: x represents either 1 or 2 Figure 7-47: Camera Interface Timing Table 7-58: Camera Interface Timing Symbol Parameter Min Max t1 CMxVREF/CMxFIELD rising edge to CMxHREF rising edge 0 — t2 t3 t4 Horizontal blank period CMxHREF falling edge to CMxVREF falling edge Vertical blank period 1 0 1 — — — t5 Camera input clock period 1 (Note 3) — t6 t7 t8 t9 t10 t11 Camera input clock pulse width low Camera input clock pulse width high Data setup time Data hold time CMxVREF, CMxFIELD, CMxHREF setup time CMxVREF, CMxFIELD, CMxHREF hold time 4 4 2.4 3.8 2.4 3.8 — — — — — — Units Tc (Note 1) Tc Tc Line Ts (Note 2) ns ns ns ns ns ns 1. Tc = Camera block input clock period 2. Ts = System clock period 3. For RGB input streaming mode, REG[0D06h]/REG[0D46h] bits 2-1 = 10b, the minimum period is 2 Ts. 118 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.8 SDRAM Interface Timing t1 MEMCLK t2 t3 t4 t5 t6 t7 t8 t9 t11 t13 MEMA[12:0] MEMBA[1:0] MEMCS# MEMRAS# MEMCAS# MEMWE# MEMDQM[3:0] MEMDQ[31:0] (output data, write cycle) t10 t14 t12 t15 t16 t17 MEMCKE MEMDQ[31:0] (input data, read cycle) Figure 7-48: SDRAM Interface Timing Hardware Functional Specification Rev. 1.7 EPSON 119 Chapter 7 A.C. Characteristics S1D13515/S2D13515 Table 7-59: SDRAM Interface Timing (Clock Source is PLL1) Symbol Parameter Min Max Units t1 MEMCLK cycle time 10.0 — ns t2 MEMCLK low pulse width 3.4 — ns t3 MEMCLK high pulse width 4.6 — ns t4 MEMA[12:0] and MEMBA[1:0] setup before MEMCLK rising 2.5 — ns t5 MEMA[12:0] and MEMBA[1:0] hold after MEMCLK rising 2.5 — ns t6 MEMCS#,MEMRAS#,MEMCAS#,MEMWE# setup before MEMCLK rising 2.5 — ns t7 MEMCS#,MEMRAS#,MEMCAS#,MEMWE# hold after MEMCLK rising 2.5 — ns t8 MEMDQM[3:0] setup before MEMCLK rising 2.5 — ns t9 MEMDQM[3:0] hold after MEMCLK rising 2.5 — ns t10 MEMCLK rising to MEMDQ[31:0] low-Z for write (see Note 1) — 7.8 ns t11 MEMDQ[31:0] output data setup before MEMCLK rising for write 2.9 — ns t12 MEMCLK rising to MEMDQ[31:0] high-Z for write (see Note 2) 2.4 6.1 ns t13 MEMDQ[31:0] output data hold after MEMCLK rising for write 1.2 — ns t14 MEMCKE setup before MEMCLK rising 2.1 — ns t15 MEMCKE hold after MEMCLK rising 2.5 — ns t16 MEMDQ[31:0] input setup time for read 3.5 — ns t17 MEMDQ[31:0] input hold time for read 0 — ns 1. MEMDQ[31:0] goes low-Z at the beginning of a write cycle, 2 clock periods before output data is available. 2. MEMDQ[31:0] does not go high-Z at the end of a write cycle and only goes high-Z at the start of the next read cycle. 120 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.9 I2S Interface Timing MCLKO (8x SCKIO) t8 t1 t4 t2 t3 SCKIO (output) t9 t6 t7 WSIO (output) t5 t10 SDO t11 SDO Figure 7-49 I2S Timing when SCKIO/WSIO are Outputs Table 7-60 I2S Timing when SCKIO/WSIO are Outputs Symbol Description Min / Nominal Max Units t1 MCLKO period (see Note 1) M M+1 Tsdram t2 MCLKO high time (see Note 2) N N+1 Tsdram t3 MCLKO low time (see Note 2) N N+1 Tsdram t4 SCKIO output period 8 — t1 t5 WSIO output period 32 — t4 t6 WSIO output high time 16 — t4 t7 WSIO output low time 16 — t4 t8 MCLKO rising edge to SCKIO output rising/falling edge — 2.7 ns t9 MCLKO rising edge to WSIO output rising/falling edge — 2.5 ns t10 SCKIO output rising to SDO output valid (REG[0100h] bit 4 = 1b) — 3.3 ns t11 SCKIO output falling to SDO output valid (REG[0100h] bit 4 = 0b) — 4.1 ns 1. Tsdram is one clock cycle period of the SDRAM clock which is Ts÷2, where Ts is the System Clock period. The MCLKO clock generator is a phase accumulator circuit which generates an average MCLKO output period of t1 = [65536 ÷ (REG[010Eh] bits 14-0)] Tsdram cycles The period of MCLKO will jitter between M and M+1 Tsdram cycles to generate the average period for t1, where M is the quotient of [65536 ÷ (REG[010Eh] bits 14-0)]. 2. t2 and t3 will jitter between N and N+1 Tsdram clock cycles, where N is quotient of [32768 ÷ (REG[010Eh] bits 14-0)]. Hardware Functional Specification Rev. 1.7 EPSON 121 Chapter 7 A.C. Characteristics S1D13515/S2D13515 t1 SCKIO (input) t7 t8 t9 t10 t3 t4 WSIO (input) t2 t5 SDO t6 SDO Figure 7-50 I2S Timing when SCKIO/WSIO are Inputs Table 7-61 I2S Timing when SCKIO/WSIO are Inputs Symbol 122 Description Min / Nominal Max Units t1 SCKIO period — — — t2 WSIO period 32 — t1 t3 WSIO high time 16 — t1 t4 WSIO low time 16 — t1 t5 SCKIO rising to SDO output valid (REG[0100h] bit 4 = 1b) — 15.7 ns t6 SCKIO falling to SDO output valid (REG[0100h] bit 4 = 0b) — 15.3 ns t7 WSIO setup time before SCKIO rising (REG[0100h] bit 4 = 0b) 0 — ns t8 WSIO hold time after SCKIO rising (REG[0100h] bit 4 = 0b 1.4 — ns t9 WSIO setup time before SCKIO falling (REG[0100h] bit 4 = 1b) 0.4 — ns t10 WSIO hold time after SCKIO falling (REG[0100h] bit 4 = 1b) 1 — ns EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics 7.10 Keypad Interface Timing t1 KPDCLK (Internal Clock) (see Note 1) Sampling Clock Timing when REG[01C0h] bit 1 = 0b (Filter Disabled) (see Note 2) t2 (Internal Signal) Sampling Clock Timing when REG[01C0h] bit 1 = 1b (Filter Enabled) (see Note 2) t3 (Internal Signal) Figure 7-51: Keypad Interface Base Timing Note 1. KPDCLK is an internal clock used for the Keypad interface. Users cannot see this clock. 2. Sampling Clock is the internal input sampling clock for the Keypad interface. Users cannot see this clock. Hardware Functional Specification Rev. 1.7 EPSON 123 Chapter 7 A.C. Characteristics S1D13515/S2D13515 Sampling Clock (Internal Clock) t4 t4 KPC0 t4 KPC1 t4 KPC2 t4 KPC3 t4 KPC4 KPRx (Note) Figure 7-52: Keypad Interface Timing Note For Filter Disabled (REG[01C0h] bit 1 = 0b), KPRx are sampled/checked at the end of each KPCx pulse. For Filter Enabled (REG[01C0h] bit 1 = 1b), the filtered states of KPRx are sampled/checked at the end of each KPCx pulse. For details on filter input timing, see Figure 7-53: “Keypad Glitch Filter Input Timing,” on page 125. Table 7-62: Keypad Interface Timing Symbol Parameter t1 Keypad clock period (see Figure 7-51: on page 123) Sampling Clock pulse width (same as t1) (see Figure 7-51: on page t2 123) t3 Sampling Clock pulse width (see Figure 7-51: on page 123) t4 Key Driving Period Min Typ Note 1 Max Units tINCLK1 Note 1 tINCLK1 Note 2 4 (Note 3) t1 t2 or t3 1) t1 is specified by REG[01D4h] ~ REG[01D5h]. 2) t3 is specified by REG[01CCh] ~ REG[01CEh]. 3) If REG[01C0h] bit 1 = 0b, t4 = (4 x t2). If REG[01C0h] bit 1 = 1b, t4 = (4 x t3) 124 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 7 A.C. Characteristics Sampling Clock (Internal Clock) Filter Samples (see Note) KPRx t4 t4 KPC0 t4 KPC1 t4 KPC2 t4 KPC3 t4 KPC4 Filtered KPRx INT Generated in REG[01D0h] ~ [01D3] YES YES NO YES YES Note KPRx is internally sampled two times. The filtered KPRx only changes state if two consecutive samples are the same and opposite to the current filtered KPRx state. Figure 7-53: Keypad Glitch Filter Input Timing Note KPRx is internally sampled two times. The filtered KPRx only changes state if two consecutive samples are the same and opposite to the current filtered KPRx state. Hardware Functional Specification Rev. 1.7 EPSON 125 Chapter 7 A.C. Characteristics S1D13515/S2D13515 7.11 Serial Flash (SPI) Interface Timing SPICS# SPIDIO (MSB first) (output) D7 D6 D5 t4 t5 D4 D3 D2 D0 D1 t1 t6 SPICLK (PHA = 1, POL = 0) (PHA = 1, POL = 1) (PHA = 0, POL = 0) t3 t3 (PHA = 0, POL = 1) t2 t7 t8 SPIDIO (MSB first) (input) D7 D6 D5 D4 D3 D2 D1 D0 PHA: Serial Clock Phase (REG[0B04h] bit 2) POL: Serial Clock Polarity (REG[0B04h] bit 1) Figure 7-54: Serial Flash (SPI) Interface Timing Table 7-63: Serial Flash (SPI) Interface Timing Symbol Parameter t1 Chip select low setup time (see Note 2) t2 t3 t4 t5 t6 t7 t8 Serial clock period (see Note 3) Serial clock pulse width low/high (see Note 4) Data output setup time (see Note 4) Data output hold time (see Note 4) Chip select high hold time (see Note 5) Data input setup time Data input hold time Min Typ Max Tmincsl - 0.7ns — — — Thsckmin - 0.7ns Thsckmin - 1.6ns Thsckmin - 0.6ns Tmincsh + 0.3ns 13 0 Tsck — — — — — — — Thsckmax + 0.7ns — — — — — Units Tsdram (Note 1) Tsdram Tsdram Tsdram Tsdram Tsdram ns ns 1. 2. 3. 4. Tsdram = SDRAM clock period in ns. Tmincsl = ROUNDUP[(REG[0B04h] bits 5-3) ÷ 2] + (1 - (REG[0B04h] bit 3)) + 3 Tsck = [(REG[0B04h] bits 5-3) + 2] Thsckmin + Thsckmax = Tsck Thsckmin = ROUNDDOWN[Tsck ÷ 2] Thsckmax = ROUNDUP[Tsck ÷ 2] 5. Tmincsh = Thsckmin + 1 6. Tmincshb = Thsckmin + 1 126 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 8 Memory Map Chapter 8 Memory Map The memory, devices, and slaves on all S1D13515/S2D13515 busses are treated as a single 32-bit memory-mapped address space. Table 8-1: Memory Map Current Address Range Description 0400_0000h to 0400_7FFFh Internal SRAM1 (32K bytes) 0400_8000h to 0400_FFFFh Internal SRAM2 (32K bytes) 0401_0000h to 0401_7FFFh Internal SRAM3 (32K bytes) 0430_0000h to 0430_FFFFh Internal ROM (64K bytes) 1000_0000h to 1FFF_FFFFh External SDRAM (up to 256M bytes) 2000_0000h to 2FFF_FFFFh Serial Flash Read (up to 256M bytes) (see Note 1) 3800_0000h to 3800_FFFFh Registers / APB Bus (including Keypad Interface, PWM) 3801_0000h to 3801_FFFFh Reserved 4000_0000h to 4FFF_FFFFh Bit Per Pixel Converter (BPPC) Port 0 (see Note 2) 5000_0000h to 5FFF_FFFFh Bit Per Pixel Converter (BPPC) Port 1 (see Note 2) 6000_0000h to 6FFF_FFFFh Bit Per Pixel Converter (BPPC) Port 2 (see Note 2) 7000_0000h to 7FFF_FFFFh Bit Per Pixel Converter (BPPC) Port 3 (see Note 2) Note 1. When SPI is disabled (REG[0B04h] bit 4 = 0b), the Serial Flash read area must not be accessed. 2. The Bit Per Pixel Converter (BPPC) Ports cannot be accessed through the Host interface. Accesses to and from the BPPC ports must be in 32-bit units. 3. DMAC may not burst access across more than 1 SRAM bank. 4. Enable “non-burst” mode in the DMAC in REG[3C0C] bit 6 or REG[3C1C] bit 6, if the DMAC transfer will cross SRAM banks. 5. The Sprite Engine is not allowed to access SRAM. Hardware Functional Specification Rev. 1.7 EPSON 127 Chapter 9 Clocks S1D13515/S2D13515 Chapter 9 Clocks Audio Clock (for I2S Interface) Divider INCLK1 PLL1IN CLKI 0 OSCI 1 Divider REG[010Eh] ~ REG[010Fh] REG[0020h] ~ REG[0024h] Serial Flash Interface Logic (~100MHz) 1 PLL1 0 REG[003Eh] bits 2-1 1 External SDRAM Clock (~100MHz) 0 REG[003Eh] bit 0 CNF0 System Clock (~50MHz) ÷2 REG[003Ch] bit 1 Divider Divider PWMSRCCLK REG[0034h] ~ REG[0035h] REG[0D02h] bit 7 Timer Clock (LSCLK) Camera1 Clock Divider REG[0A80h] ~ REG[0A81h] REG[0D02h] bits 6-2 REG[0D42h] bit 7 Divider Camera2 Clock Divider Keypad Clock REG[0D42h] bits 6-2 REG[01D4h] ~ REG[01D5h] REG[0060h] REG[0061h] bit 0 0 Divider 0 1 1 Host SPI Interface Clock REG[0061h] bit 2 SPICLKISEL REG[0062h] REG[0063h] bit 0 0 Divider 1 0 1 REG[0063h] bit 2 LCD Clocks Source Divider Host I2C Interface Clock I2CCLKISEL LCD1 Pixel Clock INCLK2 PLL2IN REG[0028h] ~ REG[002Ah] 0 Divider REG[0030h] Divider 1 PLL2 1 0 REG[003Eh] bits 6-5 1 0 REG[0032h] Divider REG[003Eh] bit 4 REG[003Ch] bit 2 LCD1 Serial Interface Clock LCD2 Pixel Clock REG[0031h] REG[003Eh] bit 7 Divider LCD2 Serial Interface Clock REG[0033h] Figure 9-1: Clock Overview 128 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers Chapter 10 Registers This section discusses how and where to access the S1D13515/S2D13515 registers. It also provides detailed information about the layout and usage of each register. 10.1 Register Mapping The registers are memory-mapped. When the system decodes the input pins as CS# = 0 and M/R# = 0, the registers may be accessed. Table 10-1: Memory/Register Selection M/R# Address Size Function 1 000000h to 1FFFFFh 2M bytes Memory space 0 0000h to FFFFh 64Kbytes Register space The register space is decoded by AB[15:0] and is mapped as follows. Table 10-2: Register Mapping Address Type 0000h to 001Eh Synchronous 0020h to 004Fh Asynchronous 0050h to 007Fh Synchronous Function System Control Registers System Control Registers (same as 3800_xxxxh of Internal Space, accessible by both Host and internal C33 processor) Host Interface Registers (accessible by Host only) 0080h to 0081h Asynchronous MUADDR[31:16] - Internal Memory Space Upper Address Register 0082h Asynchronous MUMASK[20:16] - Internal Memory Space Upper Address Mask Register 0084h Asynchronous HOSTCTL[7:0] - Host Control Register 00A8h to 00ABh Synchronous MRWADDR[31:0] - Internal Memory Space Read/Write Address 00ACh to 00ADh Synchronous MRWDATA[15:0] - Internal Memory Space Read/Write Data Port Internal Registers 00B0h to FFFFh Synchronous Internal Registers (same as 3800_xxxxh of Internal Space, accessible by both Host and internal C33 processor) Note When Power Save Mode is enabled (REG[003Ch] bit 0 = 1b), only asynchronous registers may be accessed. Synchronous registers must not be accessed. Hardware Functional Specification Rev. 1.7 EPSON 129 Chapter 10 Registers S1D13515/S2D13515 10.2 Register Set The registers are listed in the following table. Table 10-3: Register Set Register Page Register Page System Control Registers REG[0000h] Product ID Register 0 140 REG[0001h] Product ID Register 1 140 REG[0002h] Product ID Register 2 140 REG[0003h] Product ID Register 3 140 REG[000Ch] through REG[000Fh] are Reserved 140 REG[0010h] C33 TTBR Remap Address Register 0 141 REG[0011h] C33 TTBR Remap Address Register 1 141 REG[0012h] C33 TTBR Remap Address Register 2 141 REG[0013h] C33 TTBR Remap Address Register 3 141 REG[001Ch] C33 Control Register 142 REG[001Dh] C33 Software Reset Register 142 REG[001Eh] C33 Status Register 143 REG[0020h] PLL1 Configuration Register 0 143 REG[0021h] PLL1 Configuration Register 1 144 REG[0022h] PLL1 Configuration Register 2 145 REG[0024h] PLL1 Control Register 145 REG[0028h] PLL2 Configuration Register 0 145 REG[0029h] PLL2 Configuration Register 1 146 REG[002Ah] PLL2 Configuration Register 2 147 REG[002Ch] PLL2 Control Register 147 REG[0030h] LCD1PCLK Configuration Register 147 REG[0031h] LCD2PCLK Configuration Register 148 REG[0032h] LCD1SCLK Configuration Register 149 REG[0033h] LCD2SCLK Configuration Register 150 REG[0034h] PWMSRCCLK Configuration Register 0 150 REG[0035h] PWMSRCCLK Configuration Register 1 150 REG[003Ch] Power Save Configuration Register 151 REG[003Dh] IO Drive Select Register 152 REG[003Eh] Input Clock Control Register 153 REG[0060h] Host SPI Clock Configuration Register 155 REG[0061h] Host SPI Enable Register 156 REG[0062h] Host I2C Clock Configuration Register 157 REG[0063h] Host I2C Enable Register 158 Host Interface Registers REG[0080h] Internal Memory Space Upper Address Register 0 159 REG[0081h] Internal Memory Space Upper Address Register 1 159 REG[0082h] Internal Memory Space Upper Address Mask Register 159 REG[0084h] Host Control Register 0 160 REG[0085h] Host Control Register 1 160 REG[008Ah] Host Control Register 2 161 REG[00A6h] Internal Memory Space Read/Write Control Register161 REG[00A8h] Internal Memory Space Read/Write Address Register 0 162 REG[00A9h] Internal Memory Space Read/Write Address Register 1 162 REG[00AAh] Internal Memory Space Read/Write Address Register 2 162 REG[00ABh] Internal Memory Space Read/Write Address Register 3 162 REG[00ACh] Internal Memory Space Read/Write Data Port Register 0 163 REG[00ADh] Internal Memory Space Read/Write Data Port Register 1 163 130 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers Table 10-3: Register Set (Continued) Register Page Register Page Bit Per Pixel Converter Configuration Registers REG[00B0h] BPPC Port 0 Mode Configuration Register 0 165 REG[00B1h] BPPC Port 0 Mode Configuration Register 1 165 REG[00B4h] BPPC Port 0 Base Register 0 166 REG[00B5h] BPPC Port 0 Base Register 1 166 REG[00B6h] BPPC Port 0 Base Register 2 166 REG[00B7h] BPPC Port 0 Base Register 3 166 REG[00B8h] BPPC Port 0 Mask Register 0 167 REG[00B9h] BPPC Port 0 Mask Register 1 167 REG[00BAh] BPPC Port 0 Mask Register 2 167 REG[00BBh] BPPC Port 0 Mask Register 3 167 REG[00BCh] BPPC Port 0 Target Base Register 0 168 REG[00BDh] BPPC Port 0 Target Base Register 1 168 REG[00BEh] BPPC Port 0 Target Base Register 2 168 REG[00BFh] BPPC Port 0 Target Base Register 3 168 REG[00C0h] BPPC Port 1 Mode Configuration Register 0 169 REG[00C1h] BPPC Port 1 Mode Configuration Register 1 169 REG[00C4h] BPPC Port 1 Base Register 0 170 REG[00C5h] BPPC Port 1 Base Register 1 170 REG[00C6h] BPPC Port 1 Base Register 2 170 REG[00C7h] BPPC Port 1 Base Register 3 170 REG[00C8h] BPPC Port 1 Mask Register 0 171 REG[00C9h] BPPC Port 1 Mask Register 1 171 REG[00CAh] BPPC Port 1 Mask Register 2 171 REG[00CBh] BPPC Port 1 Mask Register 3 171 REG[00CCh] BPPC Port 1 Target Base Register 0 172 REG[00CDh] BPPC Port 1 Target Base Register 1 172 REG[00CEh] BPPC Port 1 Target Base Register 2 172 REG[00CFh] BPPC Port 1 Target Base Register 3 172 REG[00D0h] BPPC Port 2 Mode Configuration Register 0 173 REG[00D1h] BPPC Port 2 Mode Configuration Register 1 173 REG[00D4h] BPPC Port 2 Base Register 0 174 REG[00D5h] BPPC Port 2 Base Register 1 174 REG[00D6h] BPPC Port 2 Base Register 2 174 REG[00D7h] BPPC Port 2 Base Register 3 174 REG[00D8h] BPPC Port 2 Mask Register 0 175 REG[00D9h] BPPC Port 2 Mask Register 1 175 REG[00DAh] BPPC Port 2 Mask Register 2 175 REG[00DBh] BPPC Port 2 Mask Register 3 175 REG[00DCh] BPPC Port 2 Target Base Register 0 176 REG[00DDh] BPPC Port 2 Target Base Register 1 176 REG[00DEh] BPPC Port 2 Target Base Register 2 176 REG[00DFh] BPPC Port 2 Target Base Register 3 176 REG[00E0h] BPPC Port 3 Mode Configuration Register 0 177 REG[00E1h] BPPC Port 3 Mode Configuration Register 1 177 REG[00E4h] BPPC Port 3 Base Register 0 178 REG[00E5h] BPPC Port 3 Base Register 1 178 REG[00E6h] BPPC Port 3 Base Register 2 178 REG[00E7h] BPPC Port 3 Base Register 3 178 REG[00E8h] BPPC Port 3 Mask Register 0 179 REG[00E9h] BPPC Port 3 Mask Register 1 179 REG[00EAh] BPPC Port 3 Mask Register 2 179 REG[00EBh] BPPC Port 3 Mask Register 3 179 REG[00ECh] BPPC Port 3 Target Base Register 0 180 REG[00EDh] BPPC Port 3 Target Base Register 1 180 REG[00EEh] BPPC Port 3 Target Base Register 2 180 REG[00EFh] BPPC Port 3 Target Base Register 3 180 I2S Control Registers REG[0100h] I2S Interface Control Register 0 181 REG[0101h] I2S Interface Control Register 1 182 REG[0104h] I2S FIFO Register 0 183 REG[0105h] I2S FIFO Register 1 184 REG[010Ah] I2S FIFO Status Register 0 185 REG[010Ch] I2S FIFO Status Register 1 185 REG[010Eh] I2S Audio Clock Control Register 0 186 REG[010Fh] I2S Audio Clock Control Register 1 186 Hardware Functional Specification Rev. 1.7 EPSON 131 Chapter 10 Registers S1D13515/S2D13515 Table 10-3: Register Set (Continued) Register Page Register Page I2S DMA Registers REG[0148h] I2S DMA Buffer 0 Address Register 0 187 REG[0149h] I2S DMA Buffer 0 Address Register 1 187 REG[014Ah] I2S DMA Buffer 0 Address Register 2 187 REG[014Bh] I2S DMA Buffer 0 Address Register 3 187 REG[014Ch] I2S DMA Buffer 1 Address Register 0 188 REG[014Dh] I2S DMA Buffer 1 Address Register 1 188 REG[014Eh] I2S DMA Buffer 1 Address Register 2 188 REG[014Fh] I2S DMA Buffer 1 Address Register 3 188 REG[0152h] I2S DMA Buffers Size Register 0 188 REG[0153h] I2S DMA Buffers Size Register 1 188 REG[0154h] I2S DMA Status Register 189 GPIO Registers REG[0180h] GPIO Configuration Register 0 190 REG[0181h] GPIO Configuration Register 1 190 REG[0182h] GPIO Status Register 0 190 REG[0183h] GPIO Status Register 1 190 REG[0184h] GPIO Pull-down Control Register 0 191 REG[0185h] GPIO Pull-down Control Register 1 191 REG[0186h] GPIO[15:8] / Keypad Configuration Register 191 REG[0188h] Miscellaneous Pull-up/Pull-down Register 0 192 REG[0189h] Miscellaneous Pull-up/Pull-down Register 1 193 Keypad Registers REG[01C0h] Keypad Control Register 196 REG[01C4h] Keypad Interrupt Enable Register 0 197 REG[01C5h] Keypad Interrupt Enable Register 1 197 REG[01C6h] Keypad Interrupt Enable Register 2 197 REG[01C7h] Keypad Interrupt Enable Register 3 197 REG[01C8h] Keypad Input Polarity Register 0 198 REG[01C9h] Keypad Input Polarity Register 1 198 REG[01CAh] Keypad Input Polarity Register 2 198 REG[01CBh] Keypad Input Polarity Register 3 198 REG[01CCh] Keypad Filter Sampling Period Register 0 199 REG[01CDh] Keypad Filter Sampling Period Register 1 199 REG[01CEh] Keypad Filter Sampling Period Register 2 199 REG[01D0h] Keypad Interrupt Raw Status/Clear Register 0 200 REG[01D1h] Keypad Interrupt Raw Status/Clear Register 1 200 REG[01D2h] Keypad Interrupt Raw Status/Clear Register 2 200 REG[01D3h] Keypad Interrupt Raw Status/Clear Register 3 200 REG[01D4h] Keypad Clock Configuration Register 0 201 REG[01D5h] Keypad Clock Configuration Register 1 201 REG[01D6h] Keypad GPI Function Enable Register 201 PWM Registers REG[0200h] PWM Control Register 202 REG[0201h] PWM1 Enable/On Register REG[0202h] PWM1 Off Register 204 REG[0203h] PWM1 Control Register 204 REG[0204h] PWM2 Enable/On Register 205 REG[0205h] PWM2 Off Register 205 REG[0206h] PWM2 Control Register 203 206 SDRAM Read/Write Buffer Registers REG[0240h] SDRAM Buffer 0 Configuration Register 207 REG[0244h] SDRAM Buffer 0 Read Bytes Register 209 REG[0242h] SDRAM Buffer 0 Control Register 208 209 REG[0248h] SDRAM Buffer 0 Target Address Register 0 209 REG[0249h] SDRAM Buffer 0 Target Address Register 1 REG[024Ah] SDRAM Buffer 0 Target Address Register 2 209 REG[024Bh] SDRAM Buffer 0 Target Address Register 3 209 REG[024Ch] SDRAM Buffer 0 Data Port Register 0 210 REG[024Dh] SDRAM Buffer 0 Data Port Register 1 210 REG[0250h] SDRAM Buffer 1 Configuration Register 210 REG[0252h] SDRAM Buffer 1 Control Register 211 REG[0254h] SDRAM Buffer 1 Read Bytes Register 212 REG[0258h] SDRAM Buffer 1 Target Address Register 0 212 REG[0259h] SDRAM Buffer 1 Target Address Register 1 212 REG[025Ah] SDRAM Buffer 1 Target Address Register 2 212 REG[025Bh] SDRAM Buffer 1 Target Address Register 3 212 REG[025Ch] SDRAM Buffer 1 Data Port Register 0 213 REG[025Dh] SDRAM Buffer 1 Data Port Register 1 213 REG[0260h] SDRAM Buffer 0 Rectangular Increment Register 0 213 REG[0261h] SDRAM Buffer 0 Rectangular Increment Register 1 213 REG[0262h] SDRAM Buffer 1 Rectangular Increment Register 0 214 REG[0263h] SDRAM Buffer 1 Rectangular Increment Register 1 214 REG[0264h] SDRAM Read/Write Buffer Internal Address Register 0 214 REG[0265h] SDRAM Read/Write Buffer Internal Address Register 1 214 REG[0266h] SDRAM Read/Write Buffer Internal Address Register 2 214 REG[0267h] SDRAM Read/Write Buffer Internal Address Register 3 214 REG[0300h] ~ REG[037Eh] (Even Addresses) Aliased SDRAM Buffer 0 Data Port REG[0301h] ~ REG[037Fh] (Odd Addresses) Aliased SDRAM Buffer 0 Data Port Register 0 215 Register 1 215 REG[0380h] ~ REG[03FEh] (Even Addresses) Aliased SDRAM Buffer 1 Data Port REG[0381h] ~ REG[03FFh] (Odd Addresses) Aliased SDRAM Buffer 1 Data Port Register 0 216 Register 1 216 132 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers Table 10-3: Register Set (Continued) Register Page Register Page Warp Logic Configuration Registers REG[0400h] Warp Logic Configuration Register 217 REG[0402h] Warp Logic Event Flag Register 218 REG[0404h] Warp Logic Event Enable Register 219 REG[0406h] Warp Logic Event Clear Register 220 REG[0408h] Warp Logic Frame Status Register 220 REG[040Ah] Warp Logic Frame Ready Set Register 221 REG[0410h] Warp Logic Input Width Register 0 222 REG[0411h] Warp Logic Input Width Register 1 222 REG[0412h] Warp Logic Input Height Register 0 222 REG[0413h] Warp Logic Input Height Register 1 222 REG[0414h] Warp Logic Output Width Register 0 223 REG[0415h] Warp Logic Output Width Register 1 223 REG[0416h] Warp Logic Output Height Register 0 223 REG[0417h] Warp Logic Output Height Register 1 223 REG[0420h] Warp Logic Frame Buffer 0 Start Address Register 0224 REG[0421h] Warp Logic Frame Buffer 0 Start Address Register 1224 REG[0422h] Warp Logic Frame Buffer 0 Start Address Register 2224 REG[0423h] Warp Logic Frame Buffer 0 Start Address Register 3224 REG[0424h] Warp Logic Frame Buffer 1 Start Address Register 0225 REG[0425h] Warp Logic Frame Buffer 1 Start Address Register 1225 REG[0426h] Warp Logic Frame Buffer 1 Start Address Register 2225 REG[0427h] Warp Logic Frame Buffer 1 Start Address Register 3225 REG[0430h] Warp Logic Background Color Blue Register 225 REG[0431h] Warp Logic Background Color Green Register 226 REG[0432h] Warp Logic Background Color Red Register 226 REG[0434h] Warp Logic Input X Offset Register 0 227 REG[0435h] Warp Logic Input X Offset Register 1 227 REG[0436h] Warp Logic Input Y Offset Register 0 227 REG[0437h] Warp Logic Input Y Offset Register 1 227 REG[0440h] Warp Logic Offset Table Configuration Register 228 REG[0444h] Warp Logic Offset Table SDRAM Start Address Register 0 REG[0445h] Warp Logic Offset Table SDRAM Start Address Register 1 229 229 REG[0446h] Warp Logic Offset Table SDRAM Start Address Register 2 REG[0447h] Warp Logic Offset Table SDRAM Start Address Register 3 229 229 REG[0450h] Warp Logic Luminance Table Configuration Register 0230 REG[0452h] Warp Logic Luminance Table Configuration Register 1 231 REG[0454h] Warp Logic Luminance Table SDRAM Start Address Register 0 232 REG[0455h] Warp Logic Luminance Table SDRAM Start Address Register 1 232 REG[0456h] Warp Logic Luminance Table SDRAM Start Address Register 2 232 REG[0457h] Warp Logic Luminance Table SDRAM Start Address Register 3 232 Blending Engine Configuration Registers REG[0900h] CH1OUT Control Register 233 REG[0904h] CH1OUT Writeback Frame Buffer 0 Address Register 0 234 REG[0905h] CH1OUT Writeback Frame Buffer 0 Address Register 1 234 REG[0906h] CH1OUT Writeback Frame Buffer 0 Address Register 2 234 REG[0907h] CH1OUT Writeback Frame Buffer 0 Address Register 3 234 REG[0908h] CH1OUT Writeback Frame Buffer 1 Address Register 0 235 REG[0909h] CH1OUT Writeback Frame Buffer 1 Address Register 1 235 REG[090Ah] CH1OUT Writeback Frame Buffer 1 Address Register 2 235 REG[090Bh] CH1OUT Writeback Frame Buffer 1 Address Register 3 235 REG[090Ch] Scratchpad Register 0 235 REG[090Dh] Scratchpad Register 1 235 REG[090Eh] Scratchpad Register 2 235 REG[090Fh] Scratchpad Register 3 235 REG[0920h] CH2OUT Control Register 236 237 REG[0930h] OSDOUT Control Register 236 REG[0940h] MAIN Window Control Register REG[0942h] MAIN Window Frame Control/Status Register 238 REG[0944h] MAIN Blank Color Blue Register 240 REG[0945h] MAIN Blank Color Green Register 240 REG[0946h] MAIN Blank Color Red Register 240 REG[0948h] MAIN Window Frame Buffer 0 Address Register 0 241 REG[0949h] MAIN Window Frame Buffer 0 Address Register 1 241 REG[094Ah] MAIN Window Frame Buffer 0 Address Register 2 241 REG[094Bh] MAIN Window Frame Buffer 0 Address Register 3 241 REG[094Ch] MAIN Window Frame Buffer 1 Address Register 0 242 REG[094Dh] MAIN Window Frame Buffer 1 Address Register 1 242 REG[094Eh] MAIN Window Frame Buffer 1 Address Register 2 242 REG[094Fh] MAIN Window Frame Buffer 1 Address Register 3 242 REG[0950h] MAIN Window Width Register 0 243 REG[0951h] MAIN Window Width Register 1 243 REG[0952h] MAIN Window Height Register 0 243 REG[0953h] MAIN Window Height Register 1 243 Hardware Functional Specification Rev. 1.7 EPSON 133 Chapter 10 Registers S1D13515/S2D13515 Table 10-3: Register Set (Continued) Register Page Register Page REG[0954h] MAIN Window Virtual Width Register 0 244 REG[0955h] MAIN Window Virtual Width Register 1 REG[095Ah] MAIN Input X Offset Register 0 244 REG[095Bh] MAIN Input X Offset Register 1 244 244 REG[095Ch] MAIN Input Y Offset Register 0 245 REG[095Dh] MAIN Input Y Offset Register 1 245 REG[0960h] AUX Window Control Register 245 REG[0962h] AUX Window Frame Control/Status Register 247 REG[0964h] AUX Blank Color Blue Register 248 REG[0965h] AUX Blank Color Green Register 248 REG[0966h] AUX Blank Color Red Register 248 REG[0968h] AUX Window Frame Buffer 0 Address Register 0 249 REG[0969h] AUX Window Frame Buffer 0 Address Register 1 249 REG[096Ah] AUX Window Frame Buffer 0 Address Register 2 249 REG[096Bh] AUX Window Frame Buffer 0 Address Register 3 249 REG[096Ch] AUX Window Frame Buffer 1 Address Register 0 250 REG[096Dh] AUX Window Frame Buffer 1 Address Register 1 250 REG[096Eh] AUX Window Frame Buffer 1 Address Register 2 250 REG[096Fh] AUX Window Frame Buffer 1 Address Register 3 250 REG[0970h] AUX Window Width Register 0 251 REG[0971h] AUX Window Width Register 1 251 REG[0972h] AUX Window Height Register 0 251 REG[0973h] AUX Window Height Register 1 251 REG[0974h] AUX Window Virtual Width Register 0 252 REG[0975h] AUX Window Virtual Width Register 1 252 REG[0976h] AUX Window X Offset Register 0 252 REG[0977h] AUX Window X Offset Register 1 252 REG[0978h] AUX Window Y Offset Register 0 253 REG[0979h] AUX Window Y Offset Register 1 253 REG[097Ah] AUX Input X Offset Register 0 253 REG[097Bh] AUX Input X Offset Register 1 253 REG[097Ch] AUX Input Y Offset Register 0 253 REG[097Dh] AUX Input Y Offset Register 1 253 REG[0980h] OSD Window Control Register 254 REG[0982h] OSD Window Frame Control/Status Register 256 REG[0984h] OSD Blank Color Blue Register 258 REG[0985h] OSD Blank Color Green Register 258 REG[0986h] OSD Blank Color Red Register 258 REG[0988h] OSD Window Frame Buffer 0 Address Register 0 259 REG[0989h] OSD Window Frame Buffer 0 Address Register 1 259 REG[098Ah] OSD Window Frame Buffer 0 Address Register 2 259 REG[098Bh] OSD Window Frame Buffer 0 Address Register 3 259 REG[098Ch] OSD Window Frame Buffer 1 Address Register 0 260 REG[098Dh] OSD Window Frame Buffer 1 Address Register 1 260 REG[098Eh] OSD Window Frame Buffer 1 Address Register 2 260 REG[098Fh] OSD Window Frame Buffer 1 Address Register 3 260 REG[0990h] OSD Window Width Register 0 260 REG[0991h] OSD Window Width Register 1 260 REG[0992h] OSD Window Height Register 0 261 REG[0993h] OSD Window Height Register 1 261 REG[0994h] OSD Window Virtual Width Register 0 261 REG[0995h] OSD Window Virtual Width Register 1 261 REG[0996h] OSD Window X Offset Register 0 262 REG[0997h] OSD Window X Offset Register 1 262 REG[0998h] OSD Window Y Offset Register 0 262 REG[0999h] OSD Window Y Offset Register 1 262 REG[099Ah] OSD Input X Offset Register 0 262 REG[099Bh] OSD Input X Offset Register 1 262 REG[099Ch] OSD Input Y Offset Register 0 263 REG[099Dh] OSD Input Y Offset Register 1 263 REG[09A0h] Blending Engine Control Register 263 REG[09A1h] OSD Alpha Blend Ratio Register 264 REG[09A2h] Camera I2C Data Register 265 REG[09A3h] Camera I2C Output Enable Register 265 REG[09A4h] OSD Transparency Color Blue Register 266 REG[09A5h] OSD Transparency Color Green Register 266 REG[09A6h] OSD Transparency Color Red Register 266 REG[09A7h] OSD Transparency Enable Register 267 134 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers Table 10-3: Register Set (Continued) Register Page Register Page Image Fetcher Configuration Registers REG[09AAh] Image Fetcher Input X Offset Register 0 268 REG[09ABh] Image Fetcher Input X Offset Register 1 268 REG[09ACh] Image Fetcher Input Y Offset Register 0 268 REG[09ADh] Image Fetcher Input Y Offset Register 1 268 REG[09B0h] Image Fetcher Control Register 268 REG[09B2h] Image Fetcher Frame Control/Status Register 270 REG[09B4h] Image Fetcher Blank Color Blue Register 271 REG[09B5h] Image Fetcher Blank Color Green Register 271 REG[09B6h] Image Fetcher Blank Color Red Register 271 REG[09B8h] Image Fetcher Frame Buffer 0 Address Register 0 272 REG[09B9h] Image Fetcher Frame Buffer 0 Address Register 1 272 REG[09BAh] Image Fetcher Frame Buffer 0 Address Register 2272 REG[09BBh] Image Fetcher Frame Buffer 0 Address Register 3272 REG[09BCh] Image Fetcher Frame Buffer 1 Address Register 0273 REG[09BDh] Image Fetcher Frame Buffer 1 Address Register 1273 REG[09BEh] Image Fetcher Frame Buffer 1 Address Register 2273 REG[09BFh] Image Fetcher Frame Buffer 1 Address Register 3 273 REG[09C0h] Image Fetcher Width Register 0 274 REG[09C1h] Image Fetcher Width Register 1 REG[09C2h] Image Fetcher Height Register 0 274 REG[09C3h] Image Fetcher Height Register 1 274 REG[09C4h] Image Fetcher Virtual Width Register 0 274 REG[09C5h] Image Fetcher Virtual Width Register 1 274 274 LCD Configuration Registers REG[09C8h] LCD Control A Register 275 REG[09CAh] LCD Control B Register 277 REG[09D0h] Warp Writeback Frame Buffer 0 Address Register 0278 REG[09D1h] Warp Writeback Frame Buffer 0 Address Register 1278 REG[09D2h] Warp Writeback Frame Buffer 0 Address Register 2278 REG[09D3h] Warp Writeback Frame Buffer 0 Address Register 3278 REG[09D4h] Warp Writeback Frame Buffer 1 Address Register 0279 REG[09D5h] Warp Writeback Frame Buffer 1 Address Register 1279 REG[09D6h] Warp Writeback Frame Buffer 1 Address Register 2279 REG[09D7h] Warp Writeback Frame Buffer 1 Address Register 3279 REG[09D8h] LCD Frame Control A Register 0 280 REG[09D9h] LCD Frame Control A Register 1 281 REG[09DAh] LCD Frame Control B Register 0 282 REG[09DBh] LCD Frame Control B Register 1 283 REG[09DCh] LCD Frame Control C Register 0 284 REG[09DDh] LCD Frame Control C Register 1 285 REG[09DEh] LCD Frame Control D Register 0 286 REG[09DFh] LCD Frame Control D Register 1 287 REG[09E0h] Camera1 Frame Buffer 0 Address Register 0 288 REG[09E1h] Camera1 Frame Buffer 0 Address Register 1 288 REG[09E2h] Camera1 Frame Buffer 0 Address Register 2 288 REG[09E3h] Camera1 Frame Buffer 0 Address Register 3 288 REG[09E4h] Camera1 Frame Buffer 1 Address Register 0 289 REG[09E5h] Camera1 Frame Buffer 1 Address Register 1 289 REG[09E6h] Camera1 Frame Buffer 1 Address Register 2 289 REG[09E7h] Camera1 Frame Buffer 1 Address Register 3 289 REG[09E8h] Camera2 Frame Buffer 0 Address Register 0 290 REG[09E9h] Camera2 Frame Buffer 0 Address Register 1 290 REG[09EAh] Camera2 Frame Buffer 0 Address Register 2 290 REG[09EBh] Camera2 Frame Buffer 0 Address Register 3 290 REG[09ECh] Camera2 Frame Buffer 1 Address Register 0 291 REG[09EDh] Camera2 Frame Buffer 1 Address Register 1 291 REG[09EEh] Camera2 Frame Buffer 1 Address Register 2 291 REG[09EFh] Camera2 Frame Buffer 1 Address Register 3 291 REG[09F0h] Camera1 Frame Buffer Width Register 0 292 REG[09F1h] Camera1 Frame Buffer Width Register 1 292 REG[09F2h] Camera1 Frame Buffer Height Register 0 292 REG[09F3h] Camera1 Frame Buffer Height Register 1 292 REG[09F4h] Camera1 Frame Buffer Virtual Width Register 0 292 REG[09F5h] Camera1 Frame Buffer Virtual Width Register 1 292 REG[09F6h] Camera1 Write Control Register 293 294 REG[09F8h] Camera2 Frame Buffer Width Register 0 294 REG[09F9h] Camera2 Frame Buffer Width Register 1 REG[09FAh] Camera2 Frame Buffer Height Register 0 294 REG[09FBh] Camera2 Frame Buffer Height Register 1 294 REG[09FCh] Camera2 Frame Buffer Virtual Width Register 0 294 REG[09FDh] Camera2 Frame Buffer Virtual Width Register 1 294 REG[09FEh] Camera2 Write Control Register 295 Hardware Functional Specification Rev. 1.7 EPSON 135 Chapter 10 Registers S1D13515/S2D13515 Table 10-3: Register Set (Continued) Register Page Register Page Interrupt Configuration Registers REG[0A00h] Interrupt Status Register 0 296 REG[0A02h] Interrupt Status Register 1 298 REG[0A04h] Interrupt Status Register 2 300 REG[0A06h] Host Interrupt Enable Register 0 303 REG[0A08h] Host Interrupt Enable Register 1 304 REG[0A0Ah] Host Interrupt Enable Register 2 306 REG[0A0Ch] Host Interrupt Control Register 307 REG[0A0Eh] C33PE Device Interrupt Enable Register 0 308 REG[0A10h] C33PE Device Interrupt Enable Register 1 309 REG[0A12h] C33PE Device Interrupt Enable Register 2 310 REG[0A20h] C33PE Interrupt 0 Control Register 0 311 REG[0A21h] C33PE Interrupt 0 Control Register 1 312 REG[0A22h] C33PE Interrupt 1 Control Register 0 312 REG[0A23h] C33PE Interrupt 1 Control Register 1 312 REG[0A24h] C33PE Interrupt 2 Control Register 0 312 REG[0A25h] C33PE Interrupt 2 Control Register 1 312 REG[0A26h] C33PE Interrupt 3 Control Register 0 312 REG[0A27h] C33PE Interrupt 3 Control Register 1 313 REG[0A28h] C33PE Interrupt 4 Control Register 0 313 REG[0A29h] C33PE Interrupt 4 Control Register 1 313 REG[0A2Ah] C33PE Interrupt 5 Control Register 0 313 REG[0A2Bh] C33PE Interrupt 5 Control Register 1 313 REG[0A2Ch] C33PE Interrupt 6 Control Register 0 313 REG[0A2Dh] C33PE Interrupt 6 Control Register 1 314 REG[0A2Eh] C33PE Interrupt 7 Control Register 0 314 REG[0A2Fh] C33PE Interrupt 7 Control Register 1 314 REG[0A40h] C33PE Manual Interrupt Trigger Register 314 REG[0A42h] C33PE Interrupt Enable Register 315 REG[0A43h] C33PE NMI Interrupt Enable Register 315 REG[0A44h] C33PE Interrupt Status Register 315 REG[0A46h] C33 to Host Interrupt Trigger Register 316 Timer Configuration Registers REG[0A80h] Timer Clock Configuration Register 0 317 REG[0A84h] Timer Control Register 317 REG[0A86h] Watchdog Timer Period Register 0 318 REG[0A87h] Watchdog Timer Period Register 1 318 REG[0A88h] Timer 0 Period Register 0 319 REG[0A89h] Timer 0 Period Register 1 319 REG[0A8Dh] Watchdog Timer Clear Register 1 320 REG[0A8Ah] Timer 1 Period Register 319 REG[0A8Ch] Watchdog Timer Clear Register 0 320 REG[0A81h] Timer Clock Configuration Register 1 317 SPI Flash Memory Interface Registers REG[0B00h] SPI Flash Read Data Register 321 REG[0B02h] SPI Flash Write Data Register 321 REG[0B03h] SPI Flash Data Control Register 321 REG[0B04h] SPI Flash Control Register 322 REG[0B06h] SPI Flash Status Register 323 REG[0B0Ah] SPI Flash Chip Select Control Register 324 Cache Control Register REG[0C00h] C33 Instruction Cache Control Register 325 Camera Interface Registers REG[0D00h] Camera1 Enable Register 326 REG[0D02h] Camera1 Clock Configuration Register 326 REG[0D04h] Camera1 Signal Polarity Register 327 REG[0D06h] Camera1 Configuration Register 0 327 REG[0D07h] Camera1 Configuration Register 1 329 REG[0D08h] Camera1 Input Frame Control Register 329 REG[0D0Ah] Camera1 Input Horizontal Size Register 0 330 REG[0D0Bh] Camera1 Input Horizontal Size Register 1 330 REG[0D0Ch] Camera1 Input Vertical Size Register 0 331 REG[0D0Dh] Camera1 Input Vertical Size Register 1 331 REG[0D0Eh] Camera1 Status Register 331 REG[0D10h] Camera1 Resizer X Start Position Register 0 333 REG[0D11h] Camera1 Resizer X Start Position Register 1 333 REG[0D12h] Camera1 Resizer Y Start Position Register 0 333 REG[0D13h] Camera1 Resizer Y Start Position Register 1 333 REG[0D14h] Camera1 Resizer X End Position Register 0 333 REG[0D15h] Camera1 Resizer X End Position Register 1 333 REG[0D16h] Camera1 Resizer Y End Position Register 0 334 REG[0D17h] Camera1 Resizer Y End Position Register 1 334 REG[0D18h] Camera1 Resizer Horizontal Scaling Rate Register334 REG[0D19h] Camera1 Resizer Vertical Scaling Rate Register 334 REG[0D1Ah] Camera1 Resizer Scaling Control Register 335 REG[0D1Ch] is Reserved REG[0D1Eh] Camera1 YRC Control Register 0 335 REG[0D1Fh] Camera1 YRC Control Register 1 336 REG[0D20h] Camera1 YRC U Fixed Data Register 337 REG[0D21h] Camera1 YRC V Fixed Data Register 337 136 EPSON 335 Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers Table 10-3: Register Set (Continued) Register Page Register Page REG[0D22h] is Reserved 337 REG[0D24h] Camera1 YRC X Size Register 0 337 REG[0D25h] Camera1 YRC X Size Register 1 337 REG[0D26h] Camera1 YRC Y Size Register 0 338 REG[0D27h] Camera1 YRC Y Size Register 1 338 REG[0D28h] is Reserved 338 REG[0D40h] Camera2 Enable Register 340 REG[0D42h] Camera2 Clock Configuration Register 340 REG[0D44h] Camera2 Signal Polarity Register 341 REG[0D46h] Camera2 Configuration Register 0 341 REG[0D47h] Camera2 Configuration Register 1 342 REG[0D48h] Camera2 Input Frame Control Register 343 REG[0D4Ah] Camera2 Input Horizontal Size Register 0 344 REG[0D4Bh] Camera2 Input Horizontal Size Register 1 344 REG[0D4Ch] Camera2 Input Vertical Size Register 0 345 REG[0D4Dh] Camera2 Input Vertical Size Register 1 345 REG[0D4Eh] Camera2 Status Register 0 345 REG[0D50h] Camera2 Resizer X Start Position Register 0 346 REG[0D51h] Camera2 Resizer X Start Position Register 1 346 REG[0D52h] Camera2 Resizer Y Start Position Register 0 347 REG[0D53h] Camera2 Resizer Y Start Position Register 1 347 REG[0D54h] Camera2 Resizer X End Position Register 0 347 REG[0D55h] Camera2 Resizer X End Position Register 1 347 REG[0D56h] Camera2 Resizer Y End Position Register 0 347 REG[0D57h] Camera2 Resizer Y End Position Register 1 347 REG[0D58h] Camera2 Resizer Horizontal Scaling Rate Register348 REG[0D5Ah] Camera2 Resizer Scaling Control Register REG[0D59h] Camera2 Resizer Vertical Scaling Rate Register 348 348 REG[0D5Eh] Camera2 YRC Control Register 0 349 REG[0D5Fh] Camera2 YRC Control Register 1 350 REG[0D60h] Camera2 YRC U Fixed Data Register 350 REG[0D61h] Camera2 YRC V Fixed Data Register 350 REG[0D62h] is Reserved 351 REG[0D64h] Camera2 YRC X Size Register 0 351 REG[0D65h] Camera2 YRC X Size Register 1 351 REG[0D66h] Camera2 YRC Y Size Register 0 351 REG[0D67h] Camera2 YRC Y Size Register 1 351 REG[0D68h] is Reserved 352 DMA Controller Registers REG[3C00h] DMA Channel 0 Source Address Register 0 354 REG[3C01h] DMA Channel 0 Source Address Register 1 354 REG[3C02h] DMA Channel 0 Source Address Register 2 354 REG[3C03h] DMA Channel 0 Source Address Register 3 354 REG[3C04h] DMA Channel 0 Destination Address Register 0 355 REG[3C05h] DMA Channel 0 Destination Address Register 1 355 REG[3C06h] DMA Channel 0 Destination Address Register 2 355 REG[3C07h] DMA Channel 0 Destination Address Register 3 355 REG[3C08h] DMA Channel 0 Transfer Count Register 0 356 REG[3C09h] DMA Channel 0 Transfer Count Register 1 356 REG[3C0Ah] DMA Channel 0 Transfer Count Register 2 356 REG[3C0Ch] DMA Channel 0 Control Register 0 356 REG[3C0Dh] DMA Channel 0 Control Register 1 358 REG[3C10h] DMA Channel 1 Source Address Register 0 359 REG[3C11h] DMA Channel 1 Source Address Register 1 359 REG[3C12h] DMA Channel 1 Source Address Register 2 359 REG[3C13h] DMA Channel 1 Source Address Register 3 359 REG[3C14h] DMA Channel 1 Destination Address Register 0 360 REG[3C15h] DMA Channel 1 Destination Address Register 1 360 REG[3C16h] DMA Channel 1 Destination Address Register 2 360 REG[3C17h] DMA Channel 1 Destination Address Register 3 360 REG[3C18h] DMA Channel 1 Transfer Count Register 0 361 REG[3C19h] DMA Channel 1 Transfer Count Register 1 361 REG[3C1Ah] DMA Channel 1 Transfer Count Register 2 361 REG[3C1Ch] DMA Channel 1 Control Register 0 361 REG[3C1Dh] DMA Channel 1 Control Register 1 363 REG[3C20h] DMA Status Register 364 REG[3C22h] DMA Start Register 364 SDRAM Controller Configuration Registers REG[3C40h] SDRAM Control Register 366 REG[3C42h] SDRAM Refresh Period Register 0 367 REG[3C43h] SDRAM Refresh Period Register 1 367 REG[3C44h] SDRAM Clock Control Register 368 Hardware Functional Specification Rev. 1.7 EPSON 137 Chapter 10 Registers S1D13515/S2D13515 Table 10-3: Register Set (Continued) Register Page Register Page LCD Panel Configuration Registers REG[4000h] LCD Panel Type Select Register 0 369 REG[4001h] LCD Panel Type Select Register 1 371 REG[4002h] LCD1 Horizontal Total Register 0 372 REG[4003h] LCD1 Horizontal Total Register 1 372 REG[4004h] LCD1 Horizontal Display Period Register 0 372 REG[4005h] LCD1 Horizontal Display Period Register 1 372 REG[4006h] LCD1 Horizontal Display Period Start Position Register 0 373 REG[4007h] LCD1 Horizontal Display Period Start Position Register 1 373 REG[4008h] LCD1 Horizontal Pulse Width Register 0 373 REG[4009h] LCD1 Horizontal Pulse Width Register 1 REG[400Ah] LCD1 Horizontal Pulse Start Position Register 0 374 REG[400Bh] LCD1 Horizontal Pulse Start Position Register 1 374 REG[400Ch] LCD1 Vertical Total Register 0 374 REG[400Dh] LCD1 Vertical Total Register 1 374 REG[400Eh] LCD1 Vertical Display Period Register 0 375 REG[400Fh] LCD1 Vertical Display Period Register 1 375 373 REG[4010h] LCD1 Vertical Display Period Start Position Register 0375 REG[4011h] LCD1 Vertical Display Period Start Position Register 1375 REG[4012h] LCD1 Vertical Pulse Width Register 1 375 REG[4013h] LCD1 Vertical Pulse Polarity Register REG[4014h] LCD1 Vertical Pulse Start Position Register 0 376 REG[4015h] LCD1 Vertical Pulse Start Position Register 1 376 376 REG[4016h] LCD1 Serial Interface Configuration Register 377 REG[4017h] LCD1 Serial Interface Status Register 378 REG[4018h] LCD1 Interface Status Register 378 REG[4019h] LCD1 VSYNC Register 379 REG[401Ah] LCD1 VSYNC Interrupt Delay Register 0 380 REG[401Bh] LCD1 VSYNC Interrupt Delay Register 1 380 REG[401Ch] LCD1 Serial Data Register 0 380 REG[401Dh] LCD1 Serial Data Register 1 380 REG[401Fh] LCD1 Serial Data Register 2 380 REG[4020h] LCD2 Horizontal Total Register 0 381 REG[4021h] LCD2 Horizontal Total Register 1 381 REG[4022h] LCD2 Horizontal Display Period Register 0 381 REG[4023h] LCD2 Horizontal Display Period Register 1 381 REG[4024h] LCD2 Horizontal Display Period Start Position Register 0 382 REG[4025h] LCD2 Horizontal Display Period Start Position Register 1 382 REG[4026h] LCD2 Horizontal Pulse Width Register 0 382 REG[4027h] LCD2 Horizontal Pulse Width Register 1 REG[4028h] LCD2 Horizontal Pulse Start Position Register 0 383 REG[4029h] LCD2 Horizontal Pulse Start Position Register 1 383 REG[402Ah] LCD2 Vertical Total Register 0 383 REG[402Bh] LCD2 Vertical Total Register 1 383 REG[402Ch] LCD2 Vertical Display Period Register 0 384 REG[402Dh] LCD2 Vertical Display Period Register 1 384 382 REG[402Eh] LCD2 Vertical Display Period Start Position Register 0384 REG[402Fh] LCD2 Vertical Display Period Start Position Register 1384 REG[4030h] LCD2 Vertical Pulse Width Register 384 REG[4031h] LCD2 Vertical Pulse Polarity Register 385 REG[4032h] LCD2 Vertical Pulse Start Position Register 0 385 REG[4033h] LCD2 Vertical Pulse Start Position Register 1 385 REG[4034h] LCD2 Serial Interface Configuration Register 386 REG[4035h] LCD2 Serial Interface Status Register 387 REG[4036h] LCD2 Interface Status Register 388 REG[4037h] LCD2 VSYNC Register 389 REG[4038h] LCD2 VSYNC Interrupt Delay Register 0 389 REG[4039h] LCD2 VSYNC Interrupt Delay Register 1 389 REG[403Ah] LCD2 Serial Data Register 0 390 REG[403Bh] LCD2 Serial Data Register 1 390 REG[403Dh] LCD2 Serial Data Register 2 390 REG[4040h] EID Double Screen Panel Configuration Register 0391 REG[4041h] EID Double Screen Panel Configuration Register 1391 REG[4042h] EID Double Screen Panel REV Signal Register 0 392 REG[4043h] EID Double Screen Panel REV Signal Register 1 393 REG[4044h] EID Double Screen Panel Data Out Mode Register394 REG[4046h] EID Double Screen Panel OE Signal Register 0 REG[4047h] EID Double Screen Panel OE Signal Register 1 REG[4048h] EID Double Screen Panel Drive Mode Register 0 397 396 396 REG[4049h] EID Double Screen Panel Drive Mode Register 1 397 REG[404Ah] EID Double Screen Panel POLGMA Timing Register398 REG[404Ch] is Reserved REG[404Eh] EID Double Screen Panel Backlight LED Control Register 0 398 398 REG[404Fh] EID Double Screen Panel Backlight LED Control Register 1 398 REG[4050h] Sharp DualView Panel Mirror Mode Register 398 REG[4052h] Sharp DualView Panel CLS Pulse Width Register 0399 REG[4053h] Sharp DualView Panel CLS Pulse Width Register 1399 REG[4054h] Sharp DualView Panel VCOM Toggle Point Register399 REG[4056h] Sharp DualView Panel LS Delay Register 400 REG[4060h] LCD1 Display Mode Register 0 400 REG[4062h] LCD1 Display Mode Register 1 401 REG[4064h] CH1IN FIFO Threshold Register 402 138 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers Table 10-3: Register Set (Continued) Register Page Register Page REG[4065h] CH1IN FIFO Empty Status Register 402 REG[4070h] LCD2 Display Mode Register 0 402 REG[4072h] LCD2 Display Mode Register 1 404 REG[4073h] LCD2 Display Mode Register 2 405 REG[4074h] CH2IN FIFO Threshold Register 405 REG[4075h] CH2IN FIFO Empty Status Register 406 REG[4076h] OSDIN FIFO Threshold Register 406 REG[4077h] OSDIN FIFO Empty Status Register 406 407 REG[4078h] through REG[407Fh] are Reserved 406 REG[4080h] LCD1 Bias/Gain Control Register 407 REG[4082h] LCD1 Bias Red Register 0 REG[4083h] LCD1 Bias Red Register 1 407 REG[4084h] LCD1 Bias Green Register 0 407 REG[4085h] LCD1 Bias Green Register 1 407 REG[4086h] LCD1 Bias Blue Register 0 408 REG[4087h] LCD1 Bias Blue Register 1 408 REG[4088h] LCD1 Gain Red Register 408 REG[408Ah] LCD1 Gain Green Register 408 REG[408Ch] LCD1 Gain Blue Register 408 REG[4090h] LCD2 Bias/Gain Control Register 409 REG[4092h] LCD2 Bias Red Register 0 409 REG[4093h] LCD2 Bias RED Register 1 409 REG[4094h] LCD2 Bias Green Register 0 409 REG[4095h] LCD2 Bias Green Register 1 409 REG[4096h] LCD2 Bias Blue Register 0 410 REG[4097h] LCD2 Bias Blue Register 1 410 REG[4098h] LCD2 Gain Red Register 410 REG[409Ah] LCD2 Gain Green Register 410 REG[409Ch] LCD2 Gain Blue Register 410 REG[40A0h] LCD2 Gamma LUT Data Port 411 REG[40A2h] LCD2 Gamma LUT Configuration Register 0 411 REG[40A3h] LCD2 Gamma LUT Configuration Register 1 412 REG[40B0h] LCD1 Power Save Register 413 REG[40B1h] LCD2 Power Save Register 413 Sprite Registers REG[5000h] Sprite Control Register 414 REG[5001h] Sprite Software Reset Register 415 REG[5002h] Sprite SDRAM Registers Busy Register 416 REG[5003h] Sprite Engine Status Register 416 REG[5004h] Sprite Frame Trigger Control Register 417 REG[5006h] Sprite Interrupt Control Register 417 REG[5008h] Sprite Interrupt Status Register 417 REG[5020h] Sprite Frame Buffer 0 Start Address Register 0 418 REG[5021h] Sprite Frame Buffer 0 Start Address Register 1 418 REG[5022h] Sprite Frame Buffer 0 Start Address Register 2 418 REG[5023h] Sprite Frame Buffer 0 Start Address Register 3 418 REG[5024h] Sprite Frame Buffer 1 Start Address Register 0 419 REG[5025h] Sprite Frame Buffer 1 Start Address Register 1 419 REG[5026h] Sprite Frame Buffer 1 Start Address Register 2 419 REG[5027h] Sprite Frame Buffer 1 Start Address Register 3 419 REG[5028h] Sprite SDRAM Based Registers Start Address Register 0 REG[5029h] Sprite SDRAM Based Registers Start Address Register 1 420 420 REG[502Ah] Sprite SDRAM Based Registers Start Address Register 2 REG[502Bh] Sprite SDRAM Based Registers Start Address Register 3 420 420 Sprite Memory Based Registers SDRAM[**000h] Sprite #n General Control Register 0 422 SDRAM[**001h] Sprite #n General Control Register 1 422 SDRAM[**004h] Sprite #n Image Start Address Register 0 423 SDRAM[**005h] Sprite #n Image Start Address Register 1 423 SDRAM[**006h] Sprite #n Image Start Address Register 2 423 SDRAM[**007h] Sprite #n Image Start Address Register 3 423 SDRAM[**008h] Sprite #n Rotated Image Start Address Register 0424 SDRAM[**009h] Sprite #n Rotated Image Start Address Register 1424 SDRAM[**00Ah] Sprite #n Rotated Image Start Address Register 2424 SDRAM[**00Bh] Sprite #n Rotated Image Start Address Register 3424 SDRAM[**00Ch] Sprite #n X Position Register 0 425 SDRAM[**00Dh] Sprite #n X Position Register 1 SDRAM[**00Eh] Sprite #n Y Position Register 0 426 SDRAM[**00Fh] Sprite #n Y Position Register 1 425 426 SDRAM[**010h] Sprite #n Frame Width Register 0 427 SDRAM[**011h] Sprite #n Frame Width Register 1 427 SDRAM[**012h] Sprite #n Frame Height Register 0 427 SDRAM[**013h] Sprite #n Frame Height Register 1 427 SDRAM[**014h] Sprite #n Reference Point X Offset Register 0 428 SDRAM[**015h] Sprite #n Reference Point X Offset Register 1 428 SDRAM[**016h] Sprite #n Reference Point Y Offset Register 0 429 SDRAM[**017h] Sprite #n Reference Point Y Offset Register 1 429 SDRAM[**018h] Sprite #n Transparency Color / Texture Alpha Register 0 430 SDRAM[**019h] Sprite #n Transparency Color / Texture Alpha Register 1 430 SDRAM[**01Ah] Sprite #n Color Format Register Hardware Functional Specification Rev. 1.7 431 EPSON 139 Chapter 10 Registers S1D13515/S2D13515 10.3 Register Restrictions All reserved bits must be set to 0b unless otherwise specified. Writing a value to a reserved bit may produce undefined results. Bits marked as n/a have no hardware effect. 10.4 Register Descriptions 10.4.1 System Control Registers REG[0000h] Product ID Register 0 Default = 00h Read Only Reserved 7 6 bits 7-0 5 4 3 2 1 0 Reserved These bits always return 0000_0000b (00h). REG[0001h] Product ID Register 1 Default = 00h Read Only Revision Code bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 Revision Code bits [7:0] These bits indicate the revision code. The revision code for the S2D13515 is 00h. REG[0002h] Product ID Register 2 Default = 45h Read Only Product Code bits 7-0 7 6 5 4 3 2 1 REG[0003h] Product ID Register 3 Default = 00h 0 Read Only Product Code bits 15-8 7 REG[0003h] bits 7-0 REG[0002h] bits 7-0 6 5 4 3 2 1 0 Product Code bits [15:0] These bits indicate the product code. The product code is 0045h. REG[000Ch] through REG[000Fh] are Reserved These registers are Reserved and should not be written. 140 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0010h] C33 TTBR Remap Address Register 0 Default = 00h Read/Write n/a 7 6 5 4 3 2 1 REG[0011h] C33 TTBR Remap Address Register 1 Default = 00h Read/Write C33 TTBR Remap Address bits 15-8 7 6 5 4 0 n/a 3 2 1 REG[0012h] C33 TTBR Remap Address Register 2 Default = 00h 0 Read/Write C33 TTBR Remap Address bits 23-16 7 6 5 4 3 2 1 REG[0013h] C33 TTBR Remap Address Register 3 Default = 00h 0 Read/Write C33 TTBR Remap Address bits 31-24 7 REG[0013h] bits 7-0 REG[0012h] bits 7-0 REG[0011h] bits 7-0 REG[0010h] bits 7-0 6 5 4 3 2 1 0 C33 TTBR Remap Address bits [31:10] These bits specify the address (on a 1K boundary) where the C33 TTBR (exception vector table) will be remapped. REG[0011h] bits 1-0 and REG[0010h] bits 7-0 are always 0. These registers are read by the boot monitor code at boot-up. If the value of these registers is not 0, the boot monitor reprograms the TTBR address according to the address specified. Note SRAM region 0400_0200h ~ 0400_0D28h is cleared by the ROM monitor and must not be used by the TTBR function (00A0_0200h ~ 00A0_0D28h from the C33 memory map). Hardware Functional Specification Rev. 1.7 EPSON 141 Chapter 10 Registers S1D13515/S2D13515 REG[001Ch] C33 Control Register Default =C0h Reserved C33 Enable 7 6 Read/Write n/a 5 4 3 2 1 0 bit 7 Reserved This bit MUST be set to 0b. bit 6 C33 Enable This bit controls the C33. The C33 cannot be enabled when power save mode is enabled (REG[003Ch] bit 0 = 1b). When this bit = 0b, the C33 is disabled. When this bit = 1b, the C33 is enabled. (default) Note 1. The C33 should be reset before entering power save mode (REG[003Ch] bit 0) and reset disabled if necessary after exiting power save mode. 2.For minimum current consumption of the C33 when not used, REG[001Dh] bit 0 and REG[001Ch] bits 7 and 6 should be set to 0b. REG[001Dh] C33 Software Reset Register Default =00h Read/Write C33 Software Reset n/a 7 bit 0 6 5 4 3 2 1 0 C33 Software Reset This bit is used to perform a software reset of the C33. This is done by writing a 1b then a 0b to this bit. When this bit = 0b, the C33 is released from reset. (default) When this bit = 1b, the C33 is held in reset. Note For minimum current consumption of the C33 when not used, REG[001Dh] bit 0 and REG[001Ch] bits 7 and 6 should be set to 0b. 142 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[001Eh] C33 Status Register Default = 00h Read Only n/a 7 6 5 4 3 C33 Sleep Status C33 Halt Status 1 0 2 bit 1 C33 Sleep Status (Read Only) This bit indicates the status of the C33 internal sleep bit. When this bit = 0b, the C33 is not in a sleep state. When this bit = 1b, the C33 is in a sleep state. bit 0 C33 Halt Status (Read Only) This bit indicates the status of the C33 internal halt bit. When this bit = 0b, the C33 is not in a halt state. When this bit = 1b, the C33 is in a halt state. REG[0020h] PLL1 Configuration Register 0 Default = 11h n/a 7 bits 5-4 Read/Write PLL1V[1:0] 6 5 PLL1N[3:0] 4 3 2 1 0 PLL1V[1:0] These bits are used to configure the VCO frequency which must be set between 100MHz and 400MHz. These bits should be set using the following formula. fVCO = fPLL1OUT x VV Where: fVCO is the frequency of VCO, in MHz fPLL1OUT is the desired PLL1 output frequency, in MHz (see N Multiplier bits) VV is the value based on the V Divider bits as follows. Table 10-4: VV Value REG[0020h] bits 5-4 VV Value 00b Reserved 01b 2 10b 4 11b 8 Note Normally VV is set to 2. When fPLL1OUT is lower than 50MHz, stabilize VCO by setting VV = 4 or 8. Also, the PLL1 VC bits (REG[0021h] bits 3-0) must be set according to the resulting fVCO. The frequency of VCO (fVCO) must always be within 100MHz ~ 400MHz. Hardware Functional Specification Rev. 1.7 EPSON 143 Chapter 10 Registers S1D13515/S2D13515 bits 3-0 PLL1N[3:0] These bits are used to determine the output frequency of PLL1 according to the following formula. fPLL1OUT = fPLL1REFCLK x NN Where: fPLL1OUT is the desired PLL1 output frequency, in MHz fPLL1REFCLK is the PLL1 reference clock input frequency, in MHz NN is the N Multiplier value + 1 REG[0021h] PLL1 Configuration Register 1 Default = 83h Read/Write PLL1RS[3:0] 7 bits 7-4 6 PLL1VC[3:0] 5 4 3 2 1 0 PLL1RS[3:0] These bits are used to configure the Low Pass Filter (LPF) resistance and should be set based on the frequency of the PLL1 reference clock. Table 10-5: PLL1 RS Configuration bits 3-0 REG[0021h] bits 7-4 PLL1 Reference Clock Frequency 0000b ~ 0111b Reserved 1000b 20MHz ≤ fPLL1REFCLK ≤ 150MHz 1001b Reserved 1010b 5MHz ≤ fPLL1REFCLK ≤ 20MHz 1011b ~ 1111b Reserved PLL1VC[3:0] These bits set the analog adjustment pins for PLL1 and should be set according to the VCO frequency. Table 10-6: PLL1 VC Configuration 144 REG[0021h] bits 3-0 PLL1 VCO Frequency 0000b Reserved 0001b 100MHz ≤ fVCO ≤ 120MHz 0010b 120MHz < fVCO ≤ 160MHz 0011b 160MHz < fVCO ≤ 200MHz 0100b 200MHz < fVCO ≤ 240MHz 0101b 240MHz < fVCO ≤ 280MHz 0110b 280MHz < fVCO ≤ 320MHz 0111b 320MHz < fVCO ≤ 360MHz 1000b 360MHz < fVCO ≤ 400MHz 1001b ~ 1111b Reserved EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0022h] PLL1 Configuration Register 2 Default = 40h Read/Write PLL1 Configuration 2 bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 PLL1 Configuration 2 bits [7:0] These bits are used to configure PLL1 and should be set to the recommended value of 40h. REG[0024h] PLL1 Control Register Default = 00h Read/Write n/a 7 6 bit 0 5 PLL1 Enable 4 3 2 1 0 PLL1 Enable This bit controls PLL1. PLL1 must be disabled before changing the PLL1 Configuration registers, REG[0020h] ~ REG[0022h]. When this bit = 0b, PLL1 is disabled. (default) When this bit = 1b, PLL1 is enabled. REG[0028h] PLL2 Configuration Register 0 Default = 11h n/a 7 bits 5-4 Read/Write PLL2V[1:0] 6 5 PLL2N[3:0] 4 3 2 1 0 PLL2V[1:0] These bits are used to configure the VCO frequency which must be set between 100MHz and 400MHz. These bits should be set using the following formula. fVCO = fPLL1OUT x VV Where: fVCO is the frequency of VCO, in MHz fPLL2OUT is the desired PLL2 output frequency, in MHz (see N Multiplier bits) VV is the value based on the V Divider bits as follows. Table 10-7: VV Value REG[0028h] bits 5-4 VV Value 00b Reserved 01b 2 10b 4 11b 8 Note Normally VV is set to 2. When fPLL2OUT is lower than 50MHz, stabilize VCO by setting VV = 4 or 8. Also, the PLL2 VC bits (REG[0029h] bits 3-0) must be set according to the resulting fVCO. The frequency of VCO (fVCO) must always be within 100MHz ~ 400MHz. Hardware Functional Specification Rev. 1.7 EPSON 145 Chapter 10 Registers S1D13515/S2D13515 bits 3-0 PLL2N[3:0] These bits are used to determine the output frequency of PLL2 according to the following formula. fPLL2OUT = fPLL2REFCLK x NN Where: fPLL2OUT is the desired PLL2 output frequency, in MHz fPLL2REFCLK is the PLL2 reference clock input frequency, in MHz NN is the N Multiplier value + 1 REG[0029h] PLL2 Configuration Register 1 Default = 83h Read/Write PLL2RS[3:0] 7 bits 7-4 6 PLL2VC[3:0] 5 4 3 2 1 0 PLL2RS[3:0] These bits are used to configure the Low Pass Filter (LPF) resistance and should be set based on the frequency of the PLL2 reference clock. Table 10-8: PLL2 RS Configuration bits 3-0 REG[0029h] bits 7-4 PLL2 Reference Clock Frequency 0000b ~ 0111b Reserved 1000b 20MHz ≤ fPLL2REFCLK ≤ 150MHz 1001b Reserved 1010b 5MHz ≤ fPLL2REFCLK ≤ 20MHz 1011b ~ 1111b Reserved PLL2VC[3:0] These bits set the analog adjustment pins for PLL2 and should be set according to the VCO frequency. Table 10-9: PLL2 VC Configuration 146 REG[0029h] bits 3-0 PLL2 VCO Frequency 0000b Reserved 0001b 100MHz ≤ fVCO ≤ 120MHz 0010b 120MHz < fVCO ≤ 160MHz 0011b 160MHz < fVCO ≤ 200MHz 0100b 200MHz < fVCO ≤ 240MHz 0101b 240MHz < fVCO ≤ 280MHz 0110b 280MHz < fVCO ≤ 320MHz 0111b 320MHz < fVCO ≤ 360MHz 1000b 360MHz < fVCO ≤ 400MHz 1001b ~ 1111b Reserved EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[002Ah] PLL2 Configuration Register 2 Default = 40h Read/Write PLL2 Configuration 2 bits 7-0 7 6 bits 7-0 5 4 3 2 1 PLL2 Configuration 2 bits [7:0] These bits are used to configure PLL2 and should be set to the recommended value of 40h. REG[002Ch] PLL2 Control Register Default = 00h Read/Write n/a 7 0 6 bit 0 5 PLL2 Enable 4 3 2 1 0 PLL2 Enable This bit controls PLL2. PLL2 must be disabled before changing the PLL2 Configuration registers, REG[0028h] ~ REG[002Ah]. When this bit = 0b, PLL2 is disabled. (default) When this bit = 1b, PLL2 is enabled. REG[0030h] LCD1PCLK Configuration Register Default = 05h Read/Write n/a 7 bits 4-0 LCD1PCLK Divide Select bits 4-0 6 5 4 3 2 1 0 LCD1PCLK Divide Select bits [4:0] These bits specify the divide ratio for the LCD1 pixel clock (LCD1PCLK). LCD1PCLK is derived from LCDCLK. Table 10-10 LCD1PCLK Divide Ratio Selection REG[0030h] bits 4-0 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b LCD1PCLK Divide Ratio 1:1 1:2 1:4 1:6 1:8 1:10 1:12 1:14 1:16 1:18 1:20 1:22 1:24 1:26 1:28 1:30 Hardware Functional Specification Rev. 1.7 EPSON REG[0030h] bits 4-0 10000b 10001b 10010b 10011b 10100b 10101b 10110b 10111b 11000b 11001b 11010b 11011b 11100b 11101b 11110b 11111b LCD1PCLK Divide Ratio 1:32 1:34 1:36 1:38 1:40 1:42 1:44 1:46 1:48 1:50 1:52 1:54 1:56 1:58 1:60 1:62 147 Chapter 10 Registers S1D13515/S2D13515 REG[0031h] LCD2PCLK Configuration Register Default = 02h Read/Write n/a 7 bits 4-0 LCD2PCLK Divide Select bits 4-0 6 5 4 3 2 1 0 LCD2PCLK Divide Select bits [4:0] These bits specify the divide ratio for the LCD2 pixel clock (LCD2PCLK). LCD2PCLK is derived from LCDCLK. Table 10-11 LCD2PCLK Divide Ratio Selection REG[0031h] bits 4-0 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b 148 LCD2PCLK Divide Ratio 1:1 1:2 1:4 1:6 1:8 1:10 1:12 1:14 1:16 1:18 1:20 1:22 1:24 1:26 1:28 1:30 EPSON REG[0031h] bits 4-0 10000b 10001b 10010b 10011b 10100b 10101b 10110b 10111b 11000b 11001b 11010b 11011b 11100b 11101b 11110b 11111b LCD2PCLK Divide Ratio 1:32 1:34 1:36 1:38 1:40 1:42 1:44 1:46 1:48 1:50 1:52 1:54 1:56 1:58 1:60 1:62 Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0032h] LCD1SCLK Configuration Register Default = 05h Read/Write n/a 7 bits 4-0 LCD1SCLK Divide Select bits 4-0 6 5 4 3 2 1 0 LCD1SCLK Divide Select bits [4:0] These bits specify the divide ratio for the LCD1 serial clock (LCD1SCLK). LCD1SCLK is derived from LCDCLK. Table 10-12 LCD1SCLK Divide Ratio Selection REG[0032h] bits 4-0 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b LCD1SCLK Divide Ratio Reserved 1:2 1:4 1:6 1:8 1:10 1:12 1:14 1:16 1:18 1:20 1:22 1:24 1:26 1:28 1:30 Hardware Functional Specification Rev. 1.7 EPSON REG[0032h] bits 4-0 10000b 10001b 10010b 10011b 10100b 10101b 10110b 10111b 11000b 11001b 11010b 11011b 11100b 11101b 11110b 11111b LCD1SCLK Divide Ratio 1:32 1:34 1:36 1:38 1:40 1:42 1:44 1:46 1:48 1:50 1:52 1:54 1:56 1:58 1:60 1:62 149 Chapter 10 Registers S1D13515/S2D13515 REG[0033h] LCD2SCLK Configuration Register Default = 05h Read/Write n/a 7 LCD2SCLK Divide Select bits 4-0 6 5 bits 4-0 4 3 2 1 0 LCD2SCLK Divide Select bits [4:0] These bits specify the divide ratio for the LCD2 serial clock (LCD2SCLK). LCD2SCLK is derived from LCDCLK. Table 10-13 LCD2SCLK Divide Ratio Selection REG[0033h] bits 4-0 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b LCD2SCLK Divide Ratio Reserved 1:2 1:4 1:6 1:8 1:10 1:12 1:14 1:16 1:18 1:20 1:22 1:24 1:26 1:28 1:30 REG[0033h] bits 4-0 10000b 10001b 10010b 10011b 10100b 10101b 10110b 10111b 11000b 11001b 11010b 11011b 11100b 11101b 11110b 11111b LCD2SCLK Divide Ratio 1:32 1:34 1:36 1:38 1:40 1:42 1:44 1:46 1:48 1:50 1:52 1:54 1:56 1:58 1:60 1:62 REG[0034h] PWMSRCCLK Configuration Register 0 Default = 00h Read/Write PWMSRCCLK Divide Select bits 7-0 7 6 5 4 3 2 1 REG[0035h] PWMSRCCLK Configuration Register 1 Default = 00h Read/Write n/a 7 REG[0035h] bits 3-0 REG[0034h] bits 7-0 150 6 0 PWMSRCCLK Divide Select bits 11-8 5 4 3 2 1 0 PWMSRCCLK Divide Select bits [11:0] These bits specify the divide ratio for the PWM source clock (PWMSRCCLK). PWMSRCCLK is derived from the system clock. The divide ratio is calculated using the following formula. PWMSRCCLK Divide Ratio = 1:(REG[0035h] bits 3-0, REG[0034h] bits 7-0 + 1) EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[003Ch] Power Save Configuration Register Default = 00h Read/Write n/a 7 6 5 4 3 LCD Clock Source Select SDRAM Clock Source Select Power Save Mode Enable 2 1 0 bit 2 LCD Clock Source Select This bit selects whether PLL2 is the source for the LCD clocks. For details on the clock structure, see Section Chapter 9, “Clocks” on page 128. When this bit = 0b, the LCD clocks source is PLL2IN which can be derived from either CLKI or OSCI as determined by the Input Clock 2 Source Select bit, REG[003Eh] bit 7. When this bit = 1b, the LCD clocks source is PLL2. bit 1 SDRAM Clock Source Select This bit selects whether PLL1 is the source for the SDRAM Clock. For details on the clock structure, see Section Chapter 9, “Clocks” on page 128. When this bit = 0b, the SDRAM clock source is PLL1IN which can be derived from either CLKI or OSCI as determined by the CNF0 pin (see Section 5.4, “Configuration Pins” on page 32). When this bit = 1b, the SDRAM clock source is PLL1. bit 0 Power Save Mode Enable The S1D13515/S2D13515 features dynamic internal clocking which enables internal clocks only when required. If all internal clocks must be stopped, this bit may be used to override dynamic clocking and stop all internal clocks. When this bit = 0b, all internal clocks are dynamically controlled as required. When this bit = 1b, all internal clocks are stopped. Note 1. When Power Save Mode is enabled (REG[003Ch] bit 0 = 1b), only asynchronous registers may be accessed. Synchronous registers must not be accessed. To confirm whether registers are asynchronous or synchronous, refer to Section 10.1, “Register Mapping” on page 129. 2. To achieve the lowest power consumption, PLL1 and PLL2 should be disabled in REG[0024h] bit 0 and REG[002Ch] bit 0, respectively, and REG[003Ch] bits 2-0 should be set to 111b. 3. Before entering power save mode, the I2S Audio Interface must be disabled in REG[0104h] bit 0 and REG[010Fh] bit 7. 4. Before entering power save mode, the C33 must be placed in HALT or SLEEP mode (through instruction code), or placed in reset (REG[001Dh] bit 0). To maintain DRAM contents while in powersave mode, place the DRAM controller in self-refresh mode in REG[3C44h] bit 6 before entering power save mode. 5. After exiting powersave mode, if self refresh mode is enabled, exit self refresh mode in REG[3C44h] bit 6 before enabling any accesses to DRAM. 6. After exiting power save mode, the DRAM controller must be re-initialized by writing a 1b to REG[3C40h] bit 0 and waiting for the bit to return a 0b before enabling any accesses to DRAM. 7. After exiting power save mode, Note 5 or 6 must be met before the C33 can safely exit HALT or SLEEP mode, or be released from reset (REG[001Dh] bit 0). Hardware Functional Specification Rev. 1.7 EPSON 151 Chapter 10 Registers S1D13515/S2D13515 REG[003Dh] IO Drive Select Register Default = 1Fh Read/Write Reserved Reserved Miscellaneous IO Drive Select SDRAM IO Drive Select Camera IO Drive Select Panel2 IO Drive Select Panel1 IO Drive Select Host IO Drive Select 7 6 5 4 3 2 1 0 bit 7 Reserved This bit must be set to 0b. bit 6 Reserved This bit must be set to 0b. bit 5 Miscellaneous IO Drive Select This bit determines the drive level, in mA, for the Miscellaneous IO interface output pins. When this bit = 0b, the Miscellaneous IO drive level is set to 2mA. When this bit = 1b, the Miscellaneous IO drive level is set to 4mA (default). bit 4 SDRAM IO Drive Select This bit determines the drive level, in mA, for the Miscellaneous IO interface output pins. When this bit = 0b, the SDRAM IO drive level is set to 2mA. When this bit = 1b, the SDRAM IO drive level is set to 4mA (default). bit 3 Camera IO Drive Select This bit determines the drive level, in mA, for the Camera IO interface output pins (CM1CLKOUT, SCL, and SDA). When this bit = 0b, the Camera IO drive level is set to 2mA. When this bit = 1b, the Camera IO drive level is set to 4mA (default). bit 2 Panel2 IO Drive Select This bit determines the drive level, in mA, for the Panel2 IO interface output pins. When this bit = 0b, the Panel2 IO drive level is set to 2mA. When this bit = 1b, the Panel2 IO drive level is set to 4mA (default). bit 1 Panel1 IO Drive Select This bit determines the drive level, in mA, for the Panel1 IO interface output pins. When this bit = 0b, the Panel1 IO drive level is set to 2mA. When this bit = 1b, the Panel1 IO drive level is set to 4mA (default). bit 0 Host IO Drive Select This bit determines the drive level, in mA, for the Host IO interface output pins. When this bit = 0b, the Host IO drive level is set to 2mA. When this bit = 1b, the Host IO drive level is set to 4mA (default). 152 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[003Eh] Input Clock Control Register Default = 0Xh Input Clock 2 Source Select 7 PLL2 Input Divide Select bits 1-0 6 Read/Write PLL2 Input Divide Enable Input Clock 1 Source (RO) 4 3 5 PLL1 Input Divide Select bits 1-0 2 1 PLL1 Input Divide Enable 0 bit 7 Input Clock 2 Source Select This bit selects whether CLKI or OSCI is the source for Input Clock 2 (INCLK2). For details on the clock structure, see Section Chapter 9, “Clocks” on page 128. When this bit = 0b, the Input Clock 2 source is CLKI. When this bit = 1b, the Input Clock 2 source is OSCI. bits 6-5 PLL2 Input Divide Select bits [1:0] If the PLL2 Input Divide Enable bit is set to 1b (REG[003Eh] bit 4 = 1b), these bits select the divide ratio applied to Input Clock 2 (INCLK2) before it goes to PLL2. If the PLL2 Input Divide Enable bit is set to 0b (REG[003Eh] bit 4 = 0b), Input Clock 2 is not divided (1:1). Table 10-14: PLL2 Input Divide Ratio Selection REG[003Eh] bits 6-5 PLL2 Input Divide Ratio 00b 2:1 01b 4:1 10b 6:1 11b 8:1 Note If the system is already operating with a divided clock and the divide ratio needs to be switched to a different ratio, the following sequence must be used. 1. Disable the PLL2 input divider (REG[003Eh] bit 4 = 0b) 2. Change the PLL2 input divide ratio (REG[003Eh] bits 6-5) 3. Enable the PLL2 input divider (REG[003Eh] bit 4 = 1b) bit 4 PLL2 Input Divide Enable This bit determines whether Input Clock 2 (INCLK2) which is used to derive the PLL2 input clock (PLL2IN) is divided or not. For details on the clock structure, see Section Chapter 9, “Clocks” on page 128. When this bit = 0b, Input Clock 2 is not divided (1:1). When this bit = 1b, Input Clock 2 is divided according to the setting of the PLL2 Input Divide Select bits, REG[003Eh] bits 6-5. bit 3 Input Clock 1 Source (Read Only) This bit indicates the Input Clock 1 (INCLK1) source which is controlled by the state of the CNF0 pin. When this bit = 0b, the Input Clock 1 source is CLKI. When this bit = 1b, the Input Clock 1 source is OSCI. Hardware Functional Specification Rev. 1.7 EPSON 153 Chapter 10 Registers bits 2-1 S1D13515/S2D13515 PLL1 Input Divide Select bits [1:0] If the PLL1 Input Divide Enable bit is set to 1b (REG[003Eh] bit 0 = 1b), these bits select the divide ratio applied to Input Clock 1 (INCLK1) before it goes to PLL1. If the PLL1 Input Divide Enable bit is set to 0b (REG[003Eh] bit 0 = 0b), Input Clock 1 is not divided (1:1). Table 10-15: PLL1 Input Divide Ratio Selection REG[003Eh] bits 2-1 PLL1 Input Divide Ratio 00b 2:1 01b 4:1 10b 6:1 11b 8:1 Note If the system is already operating with a divided clock and the divide ratio needs to be switched to a different ratio, the following sequence must be used. 1. Disable the PLL1 input divider (REG[003Eh] bit 0 = 0b) 2. Change the PLL1 input divide ratio (REG[003Eh] bits 2-1) 3. Enable the PLL1 input divider (REG[003Eh] bit 0 = 1b) bit 0 PLL1 Input Divide Enable This bit determines whether Input Clock 1 (INCLK1) which is used to derive the PLL1 input clock (PLL1IN) is divided or not. For details on the clock structure, see Section Chapter 9, “Clocks” on page 128. When this bit = 0b, Input Clock 1 is not divided (1:1). When this bit = 1b, Input Clock 1 is divided according to the setting of the PLL1 Input Divide Select bits, REG[003Eh] bits 2-1. REG[0040h] through REG[0041h] are Reserved These registers are Reserved and should not be written. 154 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0060h] Host SPI Clock Configuration Register Default = 00h Read/Write n/a 7 SPI Clock Divide Select bits 3-0 6 bits 3-0 5 4 3 2 1 0 SPI Clock Divide Select bits [3:0] These bits specify the divide ratio for the clock used for the Host SPI interface. The clock source for this divider is the system clock. This setting is used only when the SPI clock is generated from the system clock (REG[0061h] bit 0 = 1b). Table 10-16: SPI Clock Divide Ratio Selection REG[0060h] bits 3-0 SPI Clock Divide Ratio REG[0060h] bits 3-0 SPI Clock Divide Ratio 0000b 1:1 1000b 9:1 0001b 2:1 1001b 10:1 0010b 3:1 1010b 11:1 0011b 4:1 1011b 12:1 0100b 5:1 1100b 13:1 0101b 6:1 1101b 14:1 0110b 7:1 1110b 15:1 0111b 8:1 1111b 16:1 Note SPI Clock = System Clock frequency / Divide Ratio > HSCK frequency. Hardware Functional Specification Rev. 1.7 EPSON 155 Chapter 10 Registers S1D13515/S2D13515 REG[0061h] Host SPI Enable Register Default = 00h or 10h if SPI Enabled n/a 7 6 5 Read/Write SPICLKEN Pin Status (RO) n/a SPI Clock Source Select n/a SPI Clock Enable 4 3 2 1 0 bit 4 SPICLKEN Pin Status (Read Only) This bit indicates the status of the SPICLKEN (AB5) pin. When this bit = 0b, the SPICLKEN (AB5) pin is low. When this bit = 1b, the SPICLKEN (AB5) pin is high. bit 2 SPI Clock Source Select When the host is configured for SPI (see Section 5.4, “Configuration Pins” on page 32), the SPICLKSEL input pin (pin AB5) determines how the source for the Host SPI clock is selected. For details on the clock structure, see Section Chapter 9, “Clocks” on page 128. When SPICLKSEL is 0, this bit is used to select the source for the Host SPI clock between Input Clock 1 (INCLK1) and the system clock (SYSCLK) as follows. When this bit = 0b, the source for the Host SPI clock is the system clock. It can be further divided using the SPI Clock Divide Select bits (REG[0060h] bits 3-0) and can be controlled by the SPI Clock Enable bit (REG[0061h] bit 0). When this bit = 1b, the source for the Host SPI clock is Input Clock 1 (INCLK1). It cannot be further divided and is not controlled by the SPI Clock Enable bit. When SPICLKSEL is 1, this bit is ignored and the source for the Host SPI clock is Input Clock 1 (INCLK1). bit 0 156 SPI Clock Enable This bit enables/disables the Host SPI clock when the clock source is the divided down system clock. When this bit = 0b, the Host SPI clock is disabled. When this bit = 1b, the Host SPI clock is enabled. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0062h] Host I2C Clock Configuration Register Default = 00h Read/Write n/a 7 I2C Clock Divide Select bits 4-0 6 bits 3-0 5 4 3 2 1 0 I2C Clock Divide Select bits [3:0] These bits specify the divide ratio for the clock used for the Host I2C interface. The clock source for this divider is the system clock. This setting is used only when I2C clock is generated from the system clock (REG[0063h] bit 0 = 1b). Table 10-17: I2C Clock Divide Ratio Selection REG[0062h] bits 3-0 I2C Clock Divide Ratio REG[0062h] bits 3-0 I2C Clock Divide Ratio 0000b 1:1 1000b 9:1 0001b 2:1 1001b 10:1 0010b 3:1 1010b 11:1 0011b 4:1 1011b 12:1 0100b 5:1 1100b 13:1 0101b 6:1 1101b 14:1 0110b 7:1 1110b 15:1 0111b 8:1 1111b 16:1 Note For fast mode (400kbps) I2C Clock = System Clock frequency / Divide Ratio > 24MHz frequency. For standard mode (100kbps) I2C Clock = System Clock frequency / Divide Ratio > 5.4MHz frequency. Hardware Functional Specification Rev. 1.7 EPSON 157 Chapter 10 Registers S1D13515/S2D13515 REG[0063h] Host I2C Enable Register Default = 00h n/a 7 6 5 Read/Write I2CCLKEN Pin Status (RO) n/a I2C Clock Source Select n/a I2C Clock Enable 4 3 2 1 0 bit 4 I2CCLKEN Pin Status (Read Only) This bit indicates the status of the I2CCLKEN (AB5) pin. When this bit = 0b, the I2CCLKEN (AB5) pin is low. When this bit = 1b, the I2CCLKEN (AB5) pin is high. bit 2 I2C Clock Source Select When the host is configured for I2C (see Section 5.4, “Configuration Pins” on page 32), the I2CCLKSEL input pin (pin AB5) determines how the source for the Host I2C clock is selected. For details on the clock structure, see Section Chapter 9, “Clocks” on page 128. When I2CCLKSEL is 0, this bit is used to select the source for the Host I2C clock between Input Clock 1 (INCLK1) and the system clock (SYSCLK) as follows. When this bit = 0b, the source for the Host I2C clock is the system clock. It can be further divided using the I2C Clock Divide Select bits (REG[0062h] bits 3-0) and can be controlled by the I2C Clock Enable bit (REG[0063h] bit 0). When this bit = 1b, the source for the Host I2C clock is Input Clock 1 (INCLK1). It cannot be further divided and is not controlled by the I2C Clock Enable bit. When I2CCLKSEL is 1, this bit is ignored and the source for the Host I2C clock is Input Clock 1 (INCLK1). bit 0 158 I2C Clock Enable This bit enables/disables the Host I2C clock when the clock source is the divided down system clock. When this bit = 0b, the Host I2C clock is disabled. When this bit = 1b, the Host I2C clock is enabled. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.2 Host Interface Registers REG[0080h] Internal Memory Space Upper Address Register 0 Default = 00h Read/Write Internal Memory Space Upper Address bits 23-16 7 6 5 4 3 2 1 REG[0081h] Internal Memory Space Upper Address Register 1 Default = 00h 0 Read/Write Internal Memory Space Upper Address bits 31-24 7 6 REG[0081h] bits 7-0 REG[0080h] bits 7-0 5 4 3 2 1 0 Internal Memory Space Upper Address bits [31:16] These bits contain the upper 16 bits of the address to concatenate to the Host address for Parallel Direct mode access to Memory Space. The internal Memory Space has a 32-bit address and the Host interface only has up to 21 bits of address lines. This register serves as a “page” register to the internal 32-bit Memory Space. Bits 31-21 of the internal address use MUADDR[31:21]. Each of bits 20-16 of the internal address can use either MUADDR[x] or the corresponding Host input address line. The selection between MUADDR[x] and input address line is determined by the MUMASK[x] register bits. Bits 15-0 of the internal address use the lower 16 bits of the Host input address lines. REG[0082h] Internal Memory Space Upper Address Mask Register Default = 00h n/a 7 bits 4-0 Read/Write Internal Memory Space Upper Address Mask bits 20-16 6 5 4 3 2 1 0 Internal Memory Space Upper Address Mask bits [20:16] These bits select the source of the internal address bits 20-16 for Parallel Direct access to Memory Space. When MUMASK[x]=0b, the corresponding Host input address line is used. When MUMASK[x]=1b, MUADDR[x] is used. Hardware Functional Specification Rev. 1.7 EPSON 159 Chapter 10 Registers S1D13515/S2D13515 REG[0084h] Host Control Register 0 Default = 00h Read/Write Asynchronous System Control Registers Host Access n/a 7 6 bit 0 5 4 3 2 1 0 Asynchronous System Control Registers Host Access This bit controls write accesses to the asynchronous registers REG[0020h] ~ REG[003Fh]. This bit has no effect on read accesses from REG[0020h] ~ REG[003Fh] or read/write accesses for all other registers. When this bit = 0b, REG[0020h] ~ REG[003Fh] are accessed synchronously by the internal VBUS and cannot be directly written by the Host. In this mode, the Host can still indirectly write to REG[0020h] ~ REG[003Fh] using the Internal Memory Space Data Port (REG[00ACh] ~ REG[00ADh]) at the internal memory space 3800_xxxxh (see REG[00A8h] ~ REG[00ABh]). When this bit = 1b, REG[0020h] ~ REG[003Fh] are accessed asynchronously by the Host and cannot be written by the internal VBUS. REG[0085h] Host Control Register 1 Default = 04h n/a 7 6 5 Read/Write Reserved n/a 4 3 Read Data Setup Cycles bits 2-0 2 1 0 bit 4 Reserved The default value of this bit is 0b. bits 2-0 Read Data Setup Cycles bits [2:0] When the Marvell PXA3xx host interface is used, a read data setup time of 30ns is required. These bits specify the read data setup cycles before rising edge of RDY (WAIT#). Read data setup cycles must be set based on system clock cycle as follows. read data setup = (value of these bits) x (system clock period). 160 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[008Ah] Host Control Register 2 Default = 00h Write Only n/a 7 6 5 4 3 2 FP2IO C33PE Debugger Pins Enable S1D13515/ S2D13515 Software Reset 1 0 bit 4 C33PE Debugger Pins Enable This bit controls the function of the FP2IO10, FP2IO11, FP2IO13, FP2IO14, FP2IO16, and FP2IO17 pins when the host select is Direct 16-bit and not Marvell PXA3xx. When this bit = 0b, the FP2IOx pins are used for pixel data. When this bit = 1b, the FP2IOx pins are used for the C33PE Debugger interface. bit 0 S1D13515/S2D13515 Software Reset This bit controls the S1D13515/S2D13515 software reset. When this bit = 0b, the S1D13515/S2D13515 systems are released from reset. When this bit = 1b, all S1D13515/S2D13515 systems except the Host Interface are held in reset. The following sequence must be used to correctly execute a software reset. 1. Set software reset, REG[008Ah] bit 0 = 1b. 2. Disable software reset, REG[008Ah] bit 0 = 0b. 3. Set Async Register Write Access to Host, REG[0084h] bit 0 = 1b. 4. Enable PLL1, set REG[0024h] bit 0 = 1b. 5. Set Async Register Write Access to internal VBUS, REG[0084h] bit 0 = 0b. REG[00A6h] Internal Memory Space Read/Write Control Register Default = 00h Read/Write Internal Memory Space Auto-Increment Enable n/a 7 bit 0 6 5 4 3 2 1 0 Internal Memory Space Auto-Increment Enable This bit controls auto-increment of the Internal Memory Space Read/Write Address registers (REG[00A8h] ~ REG[00ABh]) for host accesses to the internal memory space through the Internal Memory Space Read/Write Data Port (REG[00ACh] ~ REG[00ADh]). When this bit = 0b, the internal memory space address is not auto-incremented. When this bit = 1b, the internal memory space address is auto-incremented. Hardware Functional Specification Rev. 1.7 EPSON 161 Chapter 10 Registers S1D13515/S2D13515 REG[00A8h] Internal Memory Space Read/Write Address Register 0 Default = 00h Read/Write Internal Memory Space Read/Write Address bits 7-0 7 6 5 4 3 2 1 REG[00A9h] Internal Memory Space Read/Write Address Register 1 Default = 00h 0 Read/Write Internal Memory Space Read/Write Address bits 15-8 7 6 5 4 3 2 1 REG[00AAh] Internal Memory Space Read/Write Address Register 2 Default = 00h 0 Read/Write Internal Memory Space Read/Write Address bits 23-16 7 6 5 4 3 2 1 REG[00ABh] Internal Memory Space Read/Write Address Register 3 Default = 00h 0 Read/Write Internal Memory Space Read/Write Address bits 31-24 7 6 5 4 3 2 1 0 REG[00ABh] bits 7-0 REG[00AAh] bits 7-0 REG[00A9h] bits 7-0 REG[00A8h] bits 7-0 Internal Memory Space Read/Write Address bits [31:0] These bits specify the internal memory space address to read/write when the Host accesses the Internal Memory Space Read/Write Data Port (REG[00ACh] ~ REG[00ADh]). These bits are auto-incremented when REG[00A6h] bit 0 = 1b. See Chapter 8, “Memory Map” on page 127 for address information. Note When using SPI, I2C, or any interface without WAIT, SDRAM must be accessed using the SDRAM Read/Write Buffers (see Section 10.4.9, “SDRAM Read/Write Buffer Registers” on page 207). 162 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00ACh] Internal Memory Space Read/Write Data Port Register 0 Default = 00h Read/Write Internal Memory Space Read/Write Data Port bits 7-0 7 6 5 4 3 2 1 REG[00ADh] Internal Memory Space Read/Write Data Port Register 1 Default = 00h 0 Read/Write Internal Memory Space Read/Write Data Port bits 15-8 7 6 5 4 3 2 1 0 REG[00ADh] bits 7-0 REG[00ACh] bits 7-0 Internal Memory Space Read/Write Data Port bits [15:0] These bits are the data port where the Host can access the internal memory space. The address that will be written to or read from is specified in REG[00A8h] ~ REG[00ABh]. Note 1. When using SPI, I2C, or any interface without WAIT, SDRAM must be accessed using the SDRAM Read/Write Buffers (see Section 10.4.9, “SDRAM Read/Write Buffer Registers” on page 207). 2. When using SPI for non-SDRAM read accesses, the Internal Memory Space Read/Write Address bits (REG[00A8h] ~ REG[00ABh]) must be set before read accesses from this port. Hardware Functional Specification Rev. 1.7 EPSON 163 Chapter 10 Registers S1D13515/S2D13515 10.4.3 Bit Per Pixel Converter Configuration Registers The Bit-Per-Pixel Converter (BPPC) can be used to up-convert or down-convert image data between 32 bpp unpacked and 8/16 bpp as shown below. See Chapter 12, “Bit-Per-Pixel Converter Functional Description” on page 440 for further information. BPPC Port 4 bytes per pixel Example Conversion 16-bit data 32-bit data BPPC SDRAM 2 bytes per pixel (see Note) or BPPC Port 4 bytes per pixel Example Conversion 8-bit data 32-bit data BPPC SDRAM 1 byte per pixel (see Note) Note The data size is based on the selected conversion mode for the specified BPPC Port (see REG[00B0h], REG[00C0h], REG[00D0h], or REG[00E0h]). Figure 10-1: BPPC Conversion Example Note The Bit Per Pixel Converter (BPPC) Ports cannot be accessed through the Host interface. Accesses to and from the BPPC ports must be in 32-bit units. 164 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00B0h] BPPC Port 0 Mode Configuration Register 0 Default = 00h Read/Write n/a 7 BPPC Port 0 Conversion Mode bits 3-0 6 bits 3-0 5 4 3 2 1 0 BPPC Port 0 Conversion Mode bits [3:0] These bits determine the address and data conversion mode as shown in the following table. Table 10-18: BPPC Port 0 Conversion Modes REG[00B0h] bits 3-0 Data Conversion Mode 0000b No change 0001b 8 bpp conversion, [A8,R8,G8,B8] Æ R3G3B2, [FFh,R8,G8,B8] Å R3G3B2 0010b 16 bpp conversion, [A8,R8,G8,B8] Æ R5G6B5, [FFh,R8,G8,B8] Å R5G6B5 0011b 8 bpp conversion for reads only, [FFh, Lum8, Lum8, Lum8] Å Lum8 0100b Reserved 0101b 8 bpp conversion for reads only, [Alpha8, 00h, 00h, 00h] Å Alpha8 0110b 16 bpp conversion for reads only, [{A4,A4}, {R4,R4}, {G4,G4}, {B4,B4}] Å R4G4B4A4 0111b 8 bpp conversion for reads only, [{Alpha4,Alpha4}, {Lum4,Lum4}, {Lum4,Lum4}, {Lum4,Lum4}] Å [Lum4, Alpha4] 1000b ~ 1001b Reserved 1010b 16 bpp conversion for reads only, [Alpha8, Lum8, Lum8, Lum8] Å [Lum8, Alpha8] 1011b ~ 1111b Reserved REG[00B1h] BPPC Port 0 Mode Configuration Register 1 Default = 00h Read/Write BPPC Port 0 ARGB Byte Arrangement bits 1-0 n/a 7 6 bits 1-0 5 4 3 2 1 0 BPPC Port 0 ARGB Byte Arrangement bits [1:0] These bits configure the expected ARGB data arrangement in 32-bit WORD. Table 10-19: Expected BPPC Port 0 ARGB Data Arrangement REG[00B1h] bits 1-0 32-bit WORD Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0] Alpha Red Green Blue 01b Red Green Blue Alpha 10b Alpha Blue Green Red 11b Blue Green Red Alpha 00b Hardware Functional Specification Rev. 1.7 EPSON 165 Chapter 10 Registers S1D13515/S2D13515 REG[00B4h] BPPC Port 0 Base Register 0 Default = 00h Read Only BPPC Port 0 Base bits 7-0 7 6 5 4 3 2 1 REG[00B5h] BPPC Port 0 Base Register 1 Default = 00h 0 Read Only BPPC Port 0 Base bits 15-8 7 6 5 4 3 2 1 REG[00B6h] BPPC Port 0 Base Register 2 Default = 00h 0 Read Only BPPC Port 0 Base bits 23-16 7 6 5 4 3 2 1 REG[00B7h] BPPC Port 0 Base Register 3 Default = 40h 0 Read Only BPPC Port 0 Base bits 31-24 7 REG[00B7h] bits 7-0 REG[00B6h] bits 7-0 REG[00B5h] bits 7-0 REG[00B4h] bits 7-0 166 6 5 4 3 2 1 0 BPPC Port 0 Base bits [31:0] (Read Only) These bits indicate the base address for Port 0 of the BPPC. These bits are read only and have a value of 4000_0000h. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00B8h] BPPC Port 0 Mask Register 0 Default = 00h Read/Write BPPC Port 0 Mask bits 7-0 7 6 5 4 3 2 1 REG[00B9h] BPPC Port 0 Mask Register 1 Default = 00h 0 Read/Write BPPC Port 0 Mask bits 15-8 7 6 5 4 3 2 1 REG[00BAh] BPPC Port 0 Mask Register 2 Default = 00h 0 Read/Write BPPC Port 0 Mask bits 23-16 7 6 5 4 3 2 1 REG[00BBh] BPPC Port 0 Mask Register 3 Default = 00h Read/Write n/a 7 REG[00BBh] bits 3-0 REG[00BAh] bits 7-0 REG[00B9h] bits 7-0 REG[00B8h] bits 7-0 6 0 BPPC Port 0 Mask bits 27-24 5 4 3 2 1 0 BPPC Port 0 Mask bits [27:0] These bits are used in combination with the BPPC Port 0 Target Base bits (see REG[00BCh] ~ REG[00BFh]) and specify the mask to validate the port address to a specific range for Port 0 of the BPPC. These bits must be byte, 2 byte, or 4 byte aligned based on the selected BPPC Port 0 Conversion Mode (see REG[00B0h] bits 3-0). For example, if 8 bpp conversion is selected, the bits must be byte aligned. For 16 bpp conversion, the bits must be 2 byte aligned. The lower 28 bits of the port address is ANDed with the compliment of the Mask Register and the result is then added to the Target Base Register. Refer to the BPPC Port 0 Target Base register description (REG[00BCh] ~ REG[00BFh]) for the required equations. Hardware Functional Specification Rev. 1.7 EPSON 167 Chapter 10 Registers S1D13515/S2D13515 REG[00BCh] BPPC Port 0 Target Base Register 0 Default = 00h Read/Write BPPC Port 0 Target Base bits 7-0 7 6 5 4 3 2 1 REG[00BDh] BPPC Port 0 Target Base Register 1 Default = 00h 0 Read/Write BPPC Port 0 Target Base bits 15-8 7 6 5 4 3 2 1 REG[00BEh] BPPC Port 0 Target Base Register 2 Default = 00h 0 Read/Write BPPC Port 0 Target Base bits 23-16 7 6 5 4 3 2 1 REG[00BFh] BPPC Port 0 Target Base Register 3 Default = 00h 0 Read/Write BPPC Port 0 Target Base bits 31-24 7 REG[00BFh] bits 7-0 REG[00BEh] bits 7-0 REG[00BDh] bits 7-0 REG[00BCh] bits 7-0 6 5 4 3 2 1 0 BPPC Port 0 Target Base bits [31:0] These bits are used in combination with the BPPC Port 0 Mask bits (see REG[00B8h] ~ REG[00BBh]) and specify the target base address which determines the memory target address for Port 0 of the BPPC. These bits must be byte, 2 byte, or 4 byte aligned based on the selected BPPC Port 0 Conversion Mode (see REG[00B0h] bits 3-0). For example, if 8 bpp conversion is selected, the bits must be byte aligned. For 16 bpp conversion, the bits must be 2 byte aligned. The target address is generated according to the following equations: MaskedAddr[27:0] = PortAddr[27:0] & ~Mask[27:0] if (8 bpp format) ConvertedAddr[27:0] = {00, MaskedAddr[27:2]} else if (16 bpp format) ConvertedAddr[27:0] = {0, MaskedAddr[27:1]} else ConvertedAddr[27:0] = MaskedAddr[27:0] TargetAddr[31:0] = TargetBase[31:0] + {0000, ConvertedAddr[27:0]} 168 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00C0h] BPPC Port 1 Mode Configuration Register 0 Default = 00h Read/Write n/a 7 BPPC Port 1 Conversion Mode bits 3-0 6 bits 3-0 5 4 3 2 1 0 BPPC Port 1 Conversion Mode bits [3:0] These bits determine the address and data conversion mode as follows. Table 10-20: BPPC Port 1 Conversion Modes REG[00C0h] bits 3-0 Data Conversion Mode 0000b No change 0001b 8 bpp conversion, [A8,R8,G8,B8] Æ R3G3B2, [FFh,R8,G8,B8] Å R3G3B2 0010b 16 bpp conversion, [A8,R8,G8,B8] Æ R5G6B5, [FFh,R8,G8,B8] Å R5G6B5 0011b 8 bpp conversion for reads only, [FFh, Lum8, Lum8, Lum8] Å Lum8 0100b Reserved 0101b 8 bpp conversion for reads only, [Alpha8, 00h, 00h, 00h] Å Alpha8 0110b 16 bpp conversion for reads only, [{A4,A4}, {R4,R4}, {G4,G4}, {B4,B4}] Å R4G4B4A4 0111b 8 bpp conversion for reads only, [{Alpha4,Alpha4}, {Lum4,Lum4}, {Lum4,Lum4}, {Lum4,Lum4}] Å [Lum4, Alpha4] 1000b ~ 1001b Reserved 1010b 16 bpp conversion for reads only, [Alpha8, Lum8, Lum8, Lum8] Å [Lum8, Alpha8] 1011b ~ 1111b Reserved REG[00C1h] BPPC Port 1 Mode Configuration Register 1 Default = 00h Read/Write BPPC Port 1 ARGB Byte Arrangement bits 1-0 n/a 7 6 bits 1-0 5 4 3 2 1 0 BPPC Port 1 ARGB Byte Arrangement bits [1:0] These bits configure the expected ARGB data arrangement in 32-bit WORD. Table 10-21: Expected BPPC Port 1 ARGB Data Arrangement REG[00C1h] bits 1-0 32-bit WORD Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0] 00b Alpha Red Green Blue 01b Red Green Blue Alpha 10b Alpha Blue Green Red 11b Blue Green Red Alpha Hardware Functional Specification Rev. 1.7 EPSON 169 Chapter 10 Registers S1D13515/S2D13515 REG[00C4h] BPPC Port 1 Base Register 0 Default = 00h Read Only BPPC Port 1 Base bits 7-0 7 6 5 4 3 2 1 REG[00C5h] BPPC Port 1 Base Register 1 Default = 00h 0 Read Only BPPC Port 1 Base bits 15-8 7 6 5 4 3 2 1 REG[00C6h] BPPC Port 1 Base Register 2 Default = 00h 0 Read Only BPPC Port 1 Base bits 23-16 7 6 5 4 3 2 1 REG[00C7h] BPPC Port 1 Base Register 3 Default = 50h 0 Read Only BPPC Port 1 Base bits 31-24 7 REG[00C7h] bits 7-0 REG[00C6h] bits 7-0 REG[00C5h] bits 7-0 REG[00C4h] bits 7-0 170 6 5 4 3 2 1 0 BPPC Port 1 Base bits [31:0] (Read Only) These bits indicate the base address for Port 1 of the BPPC. These bits are read only and have a value of 5000_0000h. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00C8h] BPPC Port 1 Mask Register 0 Default = 00h Read/Write BPPC Port 1 Mask bits 7-0 7 6 5 4 3 2 1 REG[00C9h] BPPC Port 1 Mask Register 1 Default = 00h 0 Read/Write BPPC Port 1 Mask bits 15-8 7 6 5 4 3 2 1 REG[00CAh] BPPC Port 1 Mask Register 2 Default = 00h 0 Read/Write BPPC Port 1 Mask bits 23-16 7 6 5 4 3 2 1 REG[00CBh] BPPC Port 1 Mask Register 3 Default = 00h Read/Write n/a 7 REG[00CBh] bits 3-0 REG[00CAh] bits 7-0 REG[00C9h] bits 7-0 REG[00C8h] bits 7-0 6 0 BPPC Port 1 Mask bits 27-24 5 4 3 2 1 0 BPPC Port 1 Mask bits [27:0] These bits are used in combination with the BPPC Port 1 Target Base bits (see REG[00CCh] ~ REG[00CFh]) and specify the mask to validate the port address to a specific range for Port 1 of the BPPC. These bits must be byte, 2 byte, or 4 byte aligned based on the selected BPPC Port 1 Conversion Mode (see REG[00C0h] bits 3-0). For example, if 8 bpp conversion is selected, the bits must be byte aligned. For 16 bpp conversion, the bits must be 2 byte aligned. The lower 28 bits of the port address is ANDed with the compliment of the Mask Register and the result is then added to the Target Base Register. Refer to the BPPC Port 1 Target Base register description (REG[00CCh] ~ REG[00CFh]) for the required equations. Hardware Functional Specification Rev. 1.7 EPSON 171 Chapter 10 Registers S1D13515/S2D13515 REG[00CCh] BPPC Port 1 Target Base Register 0 Default = 00h Read/Write BPPC Port 1 Target Base bits 7-0 7 6 5 4 3 2 1 REG[00CDh] BPPC Port 1 Target Base Register 1 Default = 00h 0 Read/Write BPPC Port 1 Target Base bits 15-8 7 6 5 4 3 2 1 REG[00CEh] BPPC Port 1 Target Base Register 2 Default = 00h 0 Read/Write BPPC Port 1 Target Base bits 23-16 7 6 5 4 3 2 1 REG[00CFh] BPPC Port 1 Target Base Register 3 Default = 00h 0 Read/Write BPPC Port 1 Target Base bits 31-24 7 REG[00CFh] bits 7-0 REG[00CEh] bits 7-0 REG[00CDh] bits 7-0 REG[00CCh] bits 7-0 6 5 4 3 2 1 0 BPPC Port 1 Target Base bits [31:0] These bits are used in combination with the BPPC Port 1 Mask bits (see REG[00C8h] ~ REG[00CBh]) and specify the target base address which determines the memory target address for Port 1 of the BPPC. These bits must be byte, 2 byte, or 4 byte aligned based on the selected BPPC Port 1 Conversion Mode (see REG[00C0h] bits 3-0). For example, if 8 bpp conversion is selected, the bits must be byte aligned. For 16 bpp conversion, the bits must be 2 byte aligned. The target address is generated according to the following equations. MaskedAddr[27:0] = PortAddr[27:0] & ~Mask[27:0] if (8 bpp format) ConvertedAddr[27:0] = {00, MaskedAddr[27:2]} else if (16 bpp format) ConvertedAddr[27:0] = {0, MaskedAddr[27:1]} else ConvertedAddr[27:0] = MaskedAddr[27:0] TargetAddr[31:0] = TargetBase[31:0] + {0000, ConvertedAddr[27:0]} 172 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00D0h] BPPC Port 2 Mode Configuration Register 0 Default = 00h Read/Write n/a 7 BPPC Port 2 Conversion Mode bits 3-0 6 bits 3-0 5 4 3 2 1 0 BPPC Port 2 Conversion Mode bits [3:0] These bits determine the address and data conversion mode as follows. Table 10-22: BPPC Port 2 Conversion Modes REG[00D0h] bits 3-0 Data Conversion Mode 0000b No change 0001b 8 bpp conversion, [A8,R8,G8,B8] Æ R3G3B2, [FFh,R8,G8,B8] Å R3G3B2 0010b 16 bpp conversion, [A8,R8,G8,B8] Æ R5G6B5, [FFh,R8,G8,B8] Å R5G6B5 0011b 8 bpp conversion for reads only, [FFh, Lum8, Lum8, Lum8] Å Lum8 0100b Reserved 0101b 8 bpp conversion for reads only, [Alpha8, 00h, 00h, 00h] Å Alpha8 0110b 16 bpp conversion for reads only, [{A4,A4}, {R4,R4}, {G4,G4}, {B4,B4}] Å R4G4B4A4 0111b 8 bpp conversion for reads only, [{Alpha4,Alpha4}, {Lum4,Lum4}, {Lum4,Lum4}, {Lum4,Lum4}] Å [Lum4, Alpha4] 1000b ~ 1001b Reserved 1010b 16 bpp conversion for reads only, [Alpha8, Lum8, Lum8, Lum8] Å [Lum8, Alpha8] 1011b ~ 1111b Reserved REG[00D1h] BPPC Port 2 Mode Configuration Register 1 Default = 00h Read/Write BPPC Port 2 ARGB Byte Arrangement bits 1-0 n/a 7 6 bits 1-0 5 4 3 2 1 0 BPPC Port 2 ARGB Byte Arrangement bits [1:0] These bits configure the expected ARGB data arrangement in 32-bit WORD. Table 10-23: Expected BPPC Port 2 ARGB Data Arrangement REG[00D1h] bits 1-0 32-bit WORD Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0] 00b Alpha Red Green Blue 01b Red Green Blue Alpha 10b Alpha Blue Green Red 11b Blue Green Red Alpha Hardware Functional Specification Rev. 1.7 EPSON 173 Chapter 10 Registers S1D13515/S2D13515 REG[00D4h] BPPC Port 2 Base Register 0 Default = 00h Read Only BPPC Port 2 Base bits 7-0 7 6 5 4 3 2 1 REG[00D5h] BPPC Port 2 Base Register 1 Default = 00h 0 Read Only BPPC Port 2 Base bits 15-8 7 6 5 4 3 2 1 REG[00D6h] BPPC Port 2 Base Register 2 Default = 00h 0 Read Only BPPC Port 2 Base bits 23-16 7 6 5 4 3 2 1 REG[00D7h] BPPC Port 2 Base Register 3 Default = 60h 0 Read Only BPPC Port 2 Base bits 31-24 7 REG[00D7h] bits 7-0 REG[00D6h] bits 7-0 REG[00D5h] bits 7-0 REG[00D4h] bits 7-0 174 6 5 4 3 2 1 0 BPPC Port 2 Base bits [31:0] (Read Only) These bits indicate the base address for Port 2 of the BPPC. These bits are read only and have a value of 6000_0000h. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00D8h] BPPC Port 2 Mask Register 0 Default = 00h Read/Write BPPC Port 2 Mask bits 7-0 7 6 5 4 3 2 1 REG[00D9h] BPPC Port 2 Mask Register 1 Default = 00h 0 Read/Write BPPC Port 2 Mask bits 15-8 7 6 5 4 3 2 1 REG[00DAh] BPPC Port 2 Mask Register 2 Default = 00h 0 Read/Write BPPC Port 2 Mask bits 23-16 7 6 5 4 3 2 1 REG[00DBh] BPPC Port 2 Mask Register 3 Default = 00h Read/Write n/a 7 6 0 BPPC Port 2 Mask bits 27-24 5 4 3 2 1 0 REG[00DBh] bits 3-0 REG[00DAh] bits 7-0 REG[00D9h] bits 7-0 REG[00D8h] bits 7-0 BPPC Port 2 Mask bits [27:0] These bits are used in combination with the BPPC Port 2 Target Base bits (see REG[00DCh] ~ REG[00DFh]) and specify the mask to validate the port address to a specific range for Port 2 of the BPPC. These bits must be byte, 2 byte, or 4 byte aligned based on the selected BPPC Port 2 Conversion Mode (see REG[00D0h] bits 3-0). For example, if 8 bpp conversion is selected, the bits must be byte aligned. For 16 bpp conversion, the bits must be 2 byte aligned. The lower 28 bits of the port address is ANDed with the compliment of the Mask Register and the result is then added to the Target Base Register. Refer to the BPPC Port 2 Target Base register description (REG[00DCh] ~ REG[00DFh]) for the required equations. Hardware Functional Specification Rev. 1.7 EPSON 175 Chapter 10 Registers S1D13515/S2D13515 REG[00DCh] BPPC Port 2 Target Base Register 0 Default = 00h Read/Write BPPC Port 2 Target Base bits 7-0 7 6 5 4 3 2 1 REG[00DDh] BPPC Port 2 Target Base Register 1 Default = 00h 0 Read/Write BPPC Port 2 Target Base bits 15-8 7 6 5 4 3 2 1 REG[00DEh] BPPC Port 2 Target Base Register 2 Default = 00h 0 Read/Write BPPC Port 2 Target Base bits 23-16 7 6 5 4 3 2 1 REG[00DFh] BPPC Port 2 Target Base Register 3 Default = 00h 0 Read/Write BPPC Port 2 Target Base bits 31-24 7 6 5 4 3 2 1 0 REG[00DFh] bits 7-0 REG[00DEh] bits 7-0 REG[00DDh] bits 7-0 REG[00DCh] bits 7-0 BPPC Port 2 Target Base bits [31:0] These bits are used in combination with the BPPC Port 2 Mask bits (see REG[00D8h] ~ REG[00DBh]) and specify the target base address which determines the memory target address for Port 2 of the BPPC. These bits must be byte, 2 byte, or 4 byte aligned based on the selected BPPC Port 2 Conversion Mode (see REG[00D0h] bits 3-0). For example, if 8 bpp conversion is selected, the bits must be byte aligned. For 16 bpp conversion, the bits must be 2 byte aligned. The target address is generated according to the following equations. MaskedAddr[27:0] = PortAddr[27:0] & ~Mask[27:0] if (8 bpp format) ConvertedAddr[27:0] = {00, MaskedAddr[27:2]} else if (16 bpp format) ConvertedAddr[27:0] = {0, MaskedAddr[27:1]} else ConvertedAddr[27:0] = MaskedAddr[27:0] TargetAddr[31:0] = TargetBase[31:0] + {0000, ConvertedAddr[27:0]} 176 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00E0h] BPPC Port 3 Mode Configuration Register 0 Default = 00h Read/Write n/a 7 BPP Port 3 Conversion Mode bits 3-0 6 bits 3-0 5 4 3 2 1 0 BPP Port 3 Conversion Mode bits [3:0] These bits determine the address and data conversion mode as follows. Table 10-24: BPPC Port 3 Conversion Modes REG[00E0h] bits 3-0 Data Conversion Mode 0000b No change 0001b 8 bpp conversion, [A8,R8,G8,B8] Æ R3G3B2, [FFh,R8,G8,B8] Å R3G3B2 0010b 16 bpp conversion, [A8,R8,G8,B8] Æ R5G6B5, [FFh,R8,G8,B8] Å R5G6B5 0011b 8 bpp conversion for reads only, [FFh, Lum8, Lum8, Lum8] Å Lum8 0100b Reserved 0101b 8 bpp conversion for reads only, [Alpha8, 00h, 00h, 00h] Å Alpha8 0110b 16 bpp conversion for reads only, [{A4,A4}, {R4,R4}, {G4,G4}, {B4,B4}] Å R4G4B4A4 0111b 8 bpp conversion for reads only, [{Alpha4,Alpha4}, {Lum4,Lum4}, {Lum4,Lum4}, {Lum4,Lum4}] Å [Lum4, Alpha4] 1000b ~ 1001b Reserved 1010b 16 bpp conversion for reads only, [Alpha8, Lum8, Lum8, Lum8] Å [Lum8, Alpha8] 1011b ~ 1111b Reserved REG[00E1h] BPPC Port 3 Mode Configuration Register 1 Default = 00h Read/Write BPPC Port 3 ARGB Byte Arrangement bits 1-0 n/a 7 6 bits 1-0 5 4 3 2 1 0 BPPC Port 3 ARGB Byte Arrangement bits [1:0] These bits configure the expected ARGB data arrangement in 32-bit WORD. Table 10-25: Expected BPPC Port 3 ARGB Data Arrangement REG[00E1h] bits 1-0 32-bit WORD Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0] 00b Alpha Red Green Blue 01b Red Green Blue Alpha 10b Alpha Blue Green Red 11b Blue Green Red Alpha Hardware Functional Specification Rev. 1.7 EPSON 177 Chapter 10 Registers S1D13515/S2D13515 REG[00E4h] BPPC Port 3 Base Register 0 Default = 00h Read Only BPPC Port 3 Base bits 7-0 7 6 5 4 3 2 1 REG[00E5h] BPPC Port 3 Base Register 1 Default = 00h 0 Read Only BPPC Port 3 Base bits 15-8 7 6 5 4 3 2 1 REG[00E6h] BPPC Port 3 Base Register 2 Default = 00h 0 Read Only BPPC Port 3 Base bits 23-16 7 6 5 4 3 2 1 REG[00E7h] BPPC Port 3 Base Register 3 Default = 70h 0 Read Only BPPC Port 3 Base bits 31-24 7 REG[00E7h] bits 7-0 REG[00E6h] bits 7-0 REG[00E5h] bits 7-0 REG[00E4h] bits 7-0 178 6 5 4 3 2 1 0 BPPC Port 3 Base bits [31:0] (Read Only) These bits indicate the base address for Port 3 of the BPPC. These bits are read only and have a value of 7000_0000h. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[00E8h] BPPC Port 3 Mask Register 0 Default = 00h Read/Write BPPC Port 3 Mask bits 7-0 7 6 5 4 3 2 1 REG[00E9h] BPPC Port 3 Mask Register 1 Default = 00h 0 Read/Write BPPC Port 3 Mask bits 15-8 7 6 5 4 3 2 1 REG[00EAh] BPPC Port 3 Mask Register 2 Default = 00h 0 Read/Write BPPC Port 3 Mask bits 23-16 7 6 5 4 3 2 1 REG[00EBh] BPPC Port 3 Mask Register 3 Default = 00h Read/Write n/a 7 REG[00EBh] bits 3-0 REG[00EAh] bits 7-0 REG[00E9h] bits 7-0 REG[00E8h] bits 7-0 6 0 BPPC Port 3 Mask bits 27-24 5 4 3 2 1 0 BPPC Port 3 Mask bits [27:0] These bits are used in combination with the BPPC Port 3 Target Base bits (see REG[00ECh] ~ REG[00EFh]) and specify the mask to validate the port address to a specific range for Port 3 of the BPPC. These bits must be byte, 2 byte, or 4 byte aligned based on the selected BPPC Port 3 Conversion Mode (see REG[00E0h] bits 3-0). For example, if 8 bpp conversion is selected, the bits must be byte aligned. For 16 bpp conversion, the bits must be 2 byte aligned. The lower 28 bits of the port address is ANDed with the compliment of the Mask Register and the result is then added to the Target Base Register. Refer to the BPPC Port 3 Target Base register description (REG[00ECh] ~ REG[00EFh]) for the required equations. Hardware Functional Specification Rev. 1.7 EPSON 179 Chapter 10 Registers S1D13515/S2D13515 REG[00ECh] BPPC Port 3 Target Base Register 0 Default = 00h Read/Write BPPC Port 3 Target Base bits 7-0 7 6 5 4 3 2 1 REG[00EDh] BPPC Port 3 Target Base Register 1 Default = 00h 0 Read/Write BPPC Port 3 Target Base bits 15-8 7 6 5 4 3 2 1 REG[00EEh] BPPC Port 3 Target Base Register 2 Default = 00h 0 Read/Write BPPC Port 3 Target Base bits 23-16 7 6 5 4 3 2 1 REG[00EFh] BPPC Port 3 Target Base Register 3 Default = 00h 0 Read/Write BPPC Port 3 Target Base bits 31-24 7 REG[00EFh] bits 7-0 REG[00EEh] bits 7-0 REG[00EDh] bits 7-0 REG[00ECh] bits 7-0 6 5 4 3 2 1 0 BPPC Port 3 Target Base bits [31:0] These bits are used in combination with the BPPC Port 3 Mask bits (see REG[00E8h] ~ REG[00EBh]) and specify the target base address which determines the memory target address for Port 3 of the BPPC. These bits must be byte, 2 byte, or 4 byte aligned based on the selected BPPC Port 3 Conversion Mode (see REG[00E0h] bits 3-0). For example, if 8 bpp conversion is selected, the bits must be byte aligned. For 16 bpp conversion, the bits must be 2 byte aligned. The target address is generated according to the following equations. MaskedAddr[27:0] = PortAddr[27:0] & ~Mask[27:0] if (8 bpp format) ConvertedAddr[27:0] = {00, MaskedAddr[27:2]} else if (16 bpp format) ConvertedAddr[27:0] = {0, MaskedAddr[27:1]} else ConvertedAddr[27:0] = MaskedAddr[27:0] TargetAddr[31:0] = TargetBase[31:0] + {0000, ConvertedAddr[27:0]} 180 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.4 I2S Control Registers The S1D13515/S2D13515 includes an I2S interface which is typically used for audio output. For information concerning this interface, see Chapter 14, “I2S Audio Output Interface” on page 476. For information on configuring the I2S DMA buffers, refer to Section 10.4.5, “I2S DMA Registers” on page 187. REG[0100h] I2S Interface Control Register 0 Default = 21h I2S Blank Left Channel I2S Blank Right Channel I2S Left/Right Channel Data Order 7 6 5 Read/Write I2S Data Transition Clock Edge I2S WSIO Data Timing I2S Data Bit Ordering n/a IS2 Output Data Clock Source 4 3 2 1 0 bit 7 I2S Blank Left Channel This bit is used to blank left channel data for the I2S interface. When this bit = 0b, the left channel data is normal. When this bit = 1b, the left channel data is blanked. bit 6 I2S Blank Right Channel This bit is used to blank right channel data for the I2S interface. When this bit = 0b, the right channel data is normal. When this bit = 1b, the right channel data is blanked. bit 5 I2S Left/Right Channel Data Order This bit determines the left/right channel data order relative to the state of the WSIO pin. When this bit = 0b, the left/right channel data order is left channel when WSIO = 1, right channel when WSIO = 0. When this bit = 1b, the left/right channel data order is right channel when WSIO = 1, left channel when WSIO = 0. Note If the channel data order must be changed while the I2S interface is running, the I2S FIFO must be cleared using the following sequence. 1. Disable the I2S DAC Controller, REG[0104h] bit 0 = 0b 2. Reset the I2S FIFO, REG[010Ch] bit 8 = 1b 3. Change the I2S Left/Right Channel Data Order, REG[0100h] bit 5 4. Enable the I2S DAC Controller, REG[0104h] bit 0 = 1b bit 4 I2S Data Transition Clock Edge This bit determines when the serial output data on the SDO pin changes. When this bit = 0b, serial output data changes on the falling edge of the serial output source clock. When this bit = 1b, serial output data changes on the rising edge of the serial output source clock. bit 3 I2S WSIO Data Timing This bit determines when serial data output on the SDO pin occurs relative to the word sync signal edge (WSIO). When this bit = 0b, serial output data starts one clock after the WSIO edge. When this bit = 1b, serial output data starts on the same clock edge as WSIO. Hardware Functional Specification Rev. 1.7 EPSON 181 Chapter 10 Registers S1D13515/S2D13515 bit 2 I2S Data Bit Ordering This bit determines the bit order for serial data output on the SDO pin. When this bit = 0b, the most significant bit (msb) is sent first. When this bit = 1b, the least significant bit (lsb) is sent first. bit 0 I2S Data Clock Source This bit selects the source of the data clock used for serial data output on the SDO pin. This bit must be set in combination with the WSIO and SCKIO Output Enable bit (REG[0101h] bit 0) as shown in the following table. Table 10-26 : I2S Data Clock (WSIO/SCKIO) Settings REG[0101h] bit 0 REG[0100h] bit 0 0b 0b (default) Reserved I2S data clock source is the internal clock. WSIO/SCKIO are outputs driven by the internal clocks. 1b (default) 1b Description 0b I2S data clock source is an external clock and WSIO/SCKIO are inputs (high-impedance). 1b Reserved REG[0101h] I2S Interface Control Register 1 Default = 40h n/a Reserved 7 6 Read/Write WSIO and SCKIO Output Enable n/a 5 4 3 2 1 0 bit 6 Reserved This bit must be set to 1b. bit 0 WSIO and SCKIO Output Enable This bit controls whether the serial word clock (WSIO) and the serial bit clock (SCKIO) are outputs for the I2S interface. This bit must be set in combination with the I2S Data Clock Source bit (REG[0100h] bit 0) as shown in Table 10-26 “I2S Data Clock (WSIO/SCKIO) Settings” above. 182 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0104h] I2S FIFO Register 0 Default = 00h I2S FIFO Mode n/a 7 6 bit 7 Read/Write I2S FIFO Threshold Level bits 3-0 5 4 3 2 Reserved I2S DAC Controller Enable 1 0 I2S FIFO Mode This bit determines whether the data stored in the 16 byte I2S FIFO is stereo (16-bit left channel, 16-bit right channel) or mono (16-bit single data). When this bit = 0b, the data stored in the I2S FIFO is stereo. When this bit = 1b, the data stored in the I2S FIFO is mono. Note When stereo mode is selected, the I2S FIFO can hold up to 4 audio data samples. When mono mode is selected, the I2S FIFO can hold up to 8 audio data samples. bits 5-2 I2S FIFO Threshold Level bits [3:0] The I2S FIFO size is 16 bytes. These bits specify the I2S FIFO Threshold Level which determines the minimum number of bytes that should be in the I2S FIFO. If the number of bytes becomes less than or equal to the threshold level, an I2S FIFO Threshold Interrupt occurs (see REG[010Ch] bit 2) and a DMA transfer is initiated to increase the number of bytes in the I2S FIFO to the specified level. The recommended setting for these bits is 8h (1000b). bit 1 Reserved This bit must be set to 1b. Hardware Functional Specification Rev. 1.7 EPSON 183 Chapter 10 Registers S1D13515/S2D13515 bit 0 I2S DAC Controller Enable This bit controls the I2S DAC Controller. When this bit = 0b, the I2S DAC Controller is disabled and the I2S output stream is stopped. When this bit = 1b, the I2S DAC Controller is enabled and the I2S output stream is started. Note 1. When the I2S DAC Controller is enabled and stereo mode is selected (REG[0104h] bit 7 = 0b), the first serial output data is always the Left Channel data.If the I2S Left/Right Channel Data Order bit (REG[0100h] bit 5) is 0b, then the Left Channel data occurs when WSIO = 1 and the Right Channel data occurs when ‘WSIO = 0. If REG[0100h] bit 5 is 1b, then the Left Channel data occurs with WSIO = 0 and the Right Channel data occurs with WSIO = 1. 2. The I2S Audio Interface must be disabled in REG[0104h] bit 0 and REG[010Fh] bit 7 before enabling power save mode in REG[003Ch] bit 0. REG[0105h] I2S FIFO Register 1 Default = 00h Read/Write n/a 7 6 5 4 3 I2S FIFO Threshold Interrupt Enable I2S FIFO Overrun Interrupt Enable I2S FIFO Underrun Interrupt Enable 2 1 0 bit 2 I2S FIFO Threshold Interrupt Enable This bit determines whether the I2S FIFO Threshold Interrupt is indicated at the I2S DAC Interrupt Status bit, REG[0A00h] bit 6, where it can be redirected to the Host. When this bit = 0b, the I2S FIFO Threshold Interrupt is disabled. When this bit = 1b, the I2S FIFO Threshold Interrupt is enabled. bit 1 I2S FIFO Overrun Interrupt Enable This bit determines whether the I2S FIFO Overrun Interrupt is indicated at the I2S DAC Interrupt Status bit, REG[0A00h] bit 6, where it can be redirected to the Host. When this bit = 0b, the I2S FIFO Overrun Interrupt is disabled. When this bit = 1b, the I2S FIFO Overrun Interrupt is enabled. bit 0 I2S FIFO Underrun Interrupt Enable This bit determines whether the I2S FIFO Underrun Interrupt is indicated at the I2S DAC Interrupt Status bit, REG[0A00h] bit 6, where it can be redirected to the Host. When this bit = 0b, the I2S FIFO Underrun Interrupt is disabled. When this bit = 1b, the I2S FIFO Underrun Interrupt is enabled. 184 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[010Ah] I2S FIFO Status Register 0 Default = 00h Read Only n/a 7 I2S FIFO Level bits 4-0 6 bits 4-0 5 4 3 2 1 I2S FIFO Level bits [4:0] (Read Only) These bits indicate the number of bytes of data in the I2S FIFO. The FIFO size is 16 bytes. REG[010Ch] I2S FIFO Status Register 1 Default = 04h Read/Write n/a 7 0 6 5 4 I2S FIFO Software Reset (WO) I2S FIFO Threshold Interrupt Status (RO) I2S FIFO Overrun Interrupt Status I2S FIFO Underrun Interrupt Status 3 2 1 0 bit 3 I2S FIFO Software Reset (Write Only) This bit resets the I2S FIFO. Writing a 0b to this bit has no effect. Writing a 1b to this bit resets the I2S FIFO. bit 2 I2S FIFO Threshold Interrupt Status (Read Only) This read only bit indicates the status of the I2S FIFO Threshold Interrupt which occurs when the number of bytes in the I2S FIFO becomes less than the I2S FIFO Threshold Level, REG[0104h] bits 5-2. When this bit = 0b, an I2S FIFO Threshold Interrupt has not occurred. When this bit = 1b, an I2S FIFO Threshold Interrupt has occurred. This status bit is cleared when data is written to the FIFO to make the number of bytes in the FIFO greater than the threshold value (REG[0104h] bits 5-2). bit 1 I2S FIFO Overrun Interrupt Status This bit indicates the status of the I2S FIFO Overrun Interrupt which occurs when the IS2 DMA Controller tries to write to the I2S FIFO when it is already full. If the I2S FIFO Overrun Interrupt Enable bit is set (REG[0105h] bit 1 = 1b), this interrupt is also indicated at the I2S DAC Interrupt Status bit, REG[0A00h] bit 6, where it can be redirected to the Host. When this bit = 0b, an I2S FIFO Overrun Interrupt has not occurred. When this bit = 1b, an I2S FIFO Overrun Interrupt has occurred. To clear this status bit, write a 1b to this bit. Hardware Functional Specification Rev. 1.7 EPSON 185 Chapter 10 Registers S1D13515/S2D13515 bit 0 I2S FIFO Underrun Interrupt Status This bit indicates the status of the I2S FIFO Underrun Interrupt which occurs when the I2S DAC Controller has attempted to read the I2S FIFO while it is empty. If the I2S FIFO Underrun Interrupt Enable bit is set (REG[0105h] bit 0 = 1b), this interrupt is also indicated at the I2S DAC Interrupt Status bit, REG[0A00h] bit 6, where it can be redirected to the Host. When this bit = 0b, an I2S FIFO Underrun Interrupt has not occurred. When this bit = 1b, an I2S FIFO Underrun Interrupt has occurred. To clear this status bit, write a 1b to this bit. REG[010Eh] I2S Audio Clock Control Register 0 Default = 00h Read/Write Audio Clock Phase Increment bits 7-0 7 6 5 4 3 2 1 REG[010Fh] I2S Audio Clock Control Register 1 Default = 00h Audio Clock Enable 7 0 Read/Write Audio Clock Phase Increment bits 14-8 6 REG[010Fh] bits 6-0 REG[010Eh] bits 7-0 5 4 3 2 1 0 Audio Clock Phase Increment bits [14:0] The audio clock (MCLKO) is 256 times the audio sample rate and is derived from the SDRAM clock (see Section Chapter 9, “Clocks” on page 128). The frequency is calculated using the following formula. MCLKO frequency = (REG[010Fh] bits 6-0, REG[010Eh] bits 7-0) ÷ 65536 x SDRAM clock Note The audio clock frequency must be less than one half of 2 x System Clock in order for the phase accumulator logic to work. REG[010Fh] bit 7 Audio Clock Enable This bit controls the Audio Clock (MCLKO). When this bit = 0b, the audio clock is disabled. When this bit = 1b, the audio clock is enabled. Note The I2S Audio Interface must be disabled in REG[0104h] bit 0 and REG[010Fh] bit 7 before enabling power save mode in REG[003Ch] bit 0. 186 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.5 I2S DMA Registers When I2S DMA is enabled for the I2S interface (REG[0104h] bit 1 = 1b), data for the I2S FIFO can be written to the I2S DMA buffers (Buffer 0 and Buffer 1). The memory address for each buffer is configurable using the following registers. The I2S DMA controller toggles between reading from these two these buffers when sending data to the I2S FIFO. REG[0148h] I2S DMA Buffer 0 Address Register 0 Default = 00h Read/Write I2S DMA Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[0149h] I2S DMA Buffer 0 Address Register 1 Default = 00h 0 Read/Write I2S DMA Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[014Ah] I2S DMA Buffer 0 Address Register 2 Default = 00h 0 Read/Write I2S DMA Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[014Bh] I2S DMA Buffer 0 Address Register 3 Default = 00h 0 Read/Write I2S DMA Buffer 0 Address bits 31-24 7 6 REG[014Bh] bits 7-0 REG[014Ah] bits 7-0 REG[0149h] bits 7-0 REG[0148h] bits 7-0 5 4 3 2 1 0 I2S DMA Buffer 0 Address bits [31:0] These bits specify the memory start address for DMA Buffer 0. The address must be 32-bit aligned (i.e. 0, 4, 8, C,..., etc.). Note When the I2S Audio DMA Buffers are configured for DRAM, the performance of the I2S audio function will vary based on the other internal modules concurrently accesses DRAM. The I2S audio function can only be guaranteed if the I2S Audio DMA buffers are located in SRAM. Hardware Functional Specification Rev. 1.7 EPSON 187 Chapter 10 Registers S1D13515/S2D13515 REG[014Ch] I2S DMA Buffer 1 Address Register 0 Default = 00h Read/Write I2S DMA Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[014Dh] I2S DMA Buffer 1 Address Register 1 Default = 00h 0 Read/Write I2S DMA Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[014Eh] I2S DMA Buffer 1 Address Register 2 Default = 00h 0 Read/Write I2S DMA Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[014Fh] I2S DMA Buffer 1 Address Register 3 Default = 00h 0 Read/Write I2S DMA Buffer 1 Address bits 31-24 7 6 REG[014Fh] bits 7-0 REG[014Eh] bits 7-0 REG[014Dh] bits 7-0 REG[014Ch] bits 7-0 5 4 3 2 1 0 I2S DMA Buffer 1 Address bits [31:0] These bits specify the memory start address for DMA Buffer 1. The address must be 32-bit aligned (i.e. 0, 4, 8, C,..., etc.). REG[0152h] I2S DMA Buffers Size Register 0 Default = 00h Read/Write I2S DMA Buffers Size bits 7-0 7 6 5 4 3 2 1 REG[0153h] I2S DMA Buffers Size Register 1 Default = 00h 0 Read/Write I2S DMA Buffers Size bits 15-8 7 6 REG[0153h] bits 7-0 REG[0152h] bits 7-0 5 4 3 2 1 0 I2S DMA Buffers Size bits [15:0] These bits specify the size, in bytes, of the I2S DMA buffers (Buffer 0 and Buffer 1). The maximum size for the I2S DMA buffers is 65536 bytes and the minimum size is 4 bytes. I2S DMA Buffer Size = (REG[0153h], REG[0152h]) + 4 Bits 1-0 of REG[0152h] should always be programmed to 00b. 188 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0154h] I2S DMA Status Register Default = 00h Read/Write n/a 7 bit 3 6 5 I2S DMA Interrupt Status n/a I2S DMA Buffer Selection Status n/a 3 2 1 0 4 I2S DMA Interrupt Status This bit indicates when the I2S DMA Controller has finished reading from an I2S DMA buffer and switches to reading from the other buffer. This status of this interrupt can also be read at REG[0A00h] bit 3. To enable this interrupt to the Host, set the I2S DMA Interrupt Enable bit (REG[0A06h] bit 3 = 1b). When this bit = 0b, the I2S DMA Controller has not finished reading from an I2S DMA buffer. When this bit = 1b, the I2S DMA Controller has finished reading from an I2S DMA buffer. To clear this status bit, write a 1b to this bit. bit 1 I2S DMA Buffer Selection Status If I2S DMA is enabled (REG[0104h] bit 0 = 1b), this bit is read only and indicates which I2S DMA buffer is currently being read from. When this bit = 0b, I2S DMA Buffer 0 is being read from. When this bit = 1b, I2S DMA Buffer 1 is being read from. If I2S DMA is disabled (REG[0104h] bit 0 = 0b), this bit is read/write and can be used as a general-purpose “flag” bit. Hardware Functional Specification Rev. 1.7 EPSON 189 Chapter 10 Registers S1D13515/S2D13515 10.4.6 GPIO Registers REG[0180h] GPIO Configuration Register 0 Default = FFh Read/Write GPIO7 Config GPIO6 Config GPIO5 Config GPIO4 Config GPIO3 Config GPIO2 Config GPIO1 Config GPIO0 Config 7 6 5 4 3 2 1 0 REG[0181h] GPIO Configuration Register 1 Default = FFh Read/Write GPIO15 Config GPIO14 Config GPIO13 Config GPIO12 Config GPIO11 Config GPIO10 Config GPIO9 Config GPIO8 Config 7 6 5 4 3 2 1 0 REG[0181h] bits 7-0 REG[0180h] bits 7-0 GPIO[15:0] Configuration These bits configure each individual GPIO pin between an input or an output. When this bit = 0b, the corresponding GPIO pin is configured as an output pin. When this bit = 1b, the corresponding GPIO pin is configured as an input pin. (default) REG[0182h] GPIO Status Register 0 Default = XXh Read/Write GPIO7 Status GPIO6 Status GPIO5 Status GPIO4 Status GPIO3 Status GPIO2 Status GPIO1 Status GPIO0 Status 7 6 5 4 3 2 1 0 REG[0183h] GPIO Status Register 1 Default = XXh Read/Write GPIO15 Status GPIO14 Status GPIO13 Status GPIO12 Status GPIO11 Status GPIO10 Status GPIO9 Status GPIO8 Status 7 6 5 4 3 2 1 0 REG[0183h] bits 7-0 REG[0182h] bits 7-0 190 GPIO[15:0] Status When GPIOx is configured as an input (see REG[0180h] ~ REG[0181h]), a read from this bit returns the status of the corresponding GPIOx pin. When GPIOx is configured as an output (see (REG[0180h] ~ REG[0181h]), writing a 1b to the bit drives the corresponding GPIOx pin high and writing a 0b to the bit drives the corresponding GPIOx pin low. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0184h] GPIO Pull-down Control Register 0 Default = 00h Read/Write GPIO7 Pull-down Control GPIO6 Pull-down Control GPIO5 Pull-down Control GPIO4 Pull-down Control GPIO3 Pull-down Control GPIO2 Pull-down Control GPIO1 Pull-down Control GPIO0 Pull-down Control 7 6 5 4 3 2 1 0 REG[0185h] GPIO Pull-down Control Register 1 Default = 00h Read/Write GPIO15 Pull-down Control GPIO14 Pull-down Control GPIO13 Pull-down Control GPIO12 Pull-down Control GPIO11 Pull-down Control GPIO10 Pull-down Control GPIO9 Pull-down Control GPIO8 Pull-down Control 7 6 5 4 3 2 1 0 REG[0185h] bits 7-0 REG[0184h] bits 7-0 GPIO[15:0] Pull-down Control All GPIO pins have internal pull-down resistors. These bits control the state of the pulldown resistor for each GPIOx pin. When this bit = 0b, the pull-down resistor for the corresponding GPIOx pin is active. (default) When this bit = 1b, the pull-down resistor for the corresponding GPIOx pin is inactive. REG[0186h] GPIO[15:8] / Keypad Configuration Register Default = 00h n/a 7 bit 5 Read/Write GPIO[15:8] / Keypad Pin Mapping Select 6 5 n/a 4 3 2 1 0 GPIO[15:8] / Keypad Pin Mapping Select The GPIO[15:8] / Keypad interface pins can be multiplexed/mapped on either unused Host interface pins, or unused FP1 (LCD1 interface) pins. This bit selects which interface the pins are mapped to. When this bit = 0b, the Keypad interface signals are mapped on the Host Interface pins and the GPIO[15:8] signals are mapped on the FP1 pins (see Section 5.5, “Host Interface Pin Mapping” on page 34). When this bit = 1b, the Keypad interface signals are mapped on the FP1 pins and the GPIO[15:8] signals are mapped on the Host Interface pins (see Section 5.6, “LCD / Camera2 Pin Mapping” on page 39). Note GPIO7 is not available when the Keypad Interface is configured to use the FP1IO pins, REG[0186h] bit 5 = 1b. Hardware Functional Specification Rev. 1.7 EPSON 191 Chapter 10 Registers S1D13515/S2D13515 REG[0188h] Miscellaneous Pull-up/Pull-down Register 0 Default = 00h Read/Write SPIDIO Pull-down Control SDA Pull-up Control SCL Pull-up Control CM1CLKIN Pull-down Control CM1FIELD Pull-down Control CM1HREF Pull-down Control CM1VREF Pull-down Control CM1DAT[7:0] Pull-down Control 7 6 5 4 3 2 1 0 bit 7 SPIDIO Pull-down Control This bit controls the state of the pull-down resistor on the Serial Flash interface data pin, SPIDIO. When this bit = 0b, the pull-down resistor on the SPIDIO pin is active. (default) When this bit = 1b, the pull-down resistor on the SPIDIO pin is inactive. bit 6 SDA Pull-up Control This bit controls the state of the pull-up resistor on the I2C interface data pin, SDA. The I2C interface is typically used for programming the cameras. When this bit = 0b, the pull-up resistor on the SDA pin is active. (default) When this bit = 1b, the pull-up resistor on the SDA pin is inactive. bit 5 SCL Pull-up Control This bit controls the state of the pull-up resistor on the I2C interface clock pin, SCL. The I2C interface is typically used for programming the cameras. When this bit = 0b, the pull-up resistor on the SCL pin is active. (default) When this bit = 1b, the pull-up resistor on the SCL pin is inactive. bit 4 CM1CLKIN Pull-down Control This bit controls the state of the pull-down resistor on the Camera1 interface clock input pin, CM1CLKIN. When the Camera1 interface is configured for 24-bit RGB 8:8:8 streaming input (REG[0D06h] bits 2-1 = 10b), the Host Interface pins (SPI 2-stream mode) are used and this bit also controls the pull-up resistor on the C1PCLKIN input pin (BS#). When this bit = 0b, the pull-down/pull-up resistor is active. (default) When this bit = 1b, the pull-down/pull-up resistor is inactive. bit 3 CM1FIELD Pull-down Control This bit controls the state of the pull-down resistor on the Camera1 interface field input pin, CM1FIELD. When the Camera1 interface is configured for 24-bit RGB 8:8:8 streaming input (REG[0D06h] bits 2-1 = 10b), the Host Interface pins (SPI 2-stream mode) are used and this bit also controls the pull-down resistor on the C1DEIN input pin (AB0). When this bit = 0b, the pull-down resistor is active. (default) When this bit = 1b, the pull-down resistor is inactive. bit 2 CM1HREF Pull-down Control This bit controls the state of the pull-down resistor on the Camera1 interface horizontal sync input pin, CM1HREF. When the Camera1 interface is configured for 24-bit RGB 8:8:8 streaming input (REG[0D06h] bits 2-1 = 10b), the Host Interface pins (SPI 2-stream mode) are used and this bit also controls the pull-down resistor on the C1HSIN input pin (AB2). When this bit = 0b, the pull-down resistor is active. (default) When this bit = 1b, the pull-down resistor is inactive. 192 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 1 CM1VREF Pull-down Control This bit controls the state of the pull-down resistor on the Camera1 interface vertical sync input pin, CM1VREF. When the Camera1 interface is configured for 24-bit RGB 8:8:8 streaming input (REG[0D06h] bits 2-1 = 10b), the Host Interface pins (SPI 2-stream mode) are used and this bit also controls the pull-down resistor on the C1VSIN input pin (AB1). When this bit = 0b, the pull-down resistor is active. (default) When this bit = 1b, the pull-down resistor is inactive. bit 0 CM1DAT[7:0] Pull-down Control This bit controls the state of the pull-down resistors on the Camera1 interface bi-directional data pins (CM1DAT[7:0]). When the Camera1 interface is configured for 24-bit RGB 8:8:8 streaming input (REG[0D06h] bits 2-1 = 10b), the Host Interface pins (SPI 2-stream mode) are used and this bit also controls the pull-down/pull-up resistors on the C1RINx, C1GINx, and C1BINx input pins (RD#, BE1#, DB[15:0]). When this bit = 0b, the pull-down resistors are active. (default) When this bit = 1b, the pull-down resistors are inactive. REG[0189h] Miscellaneous Pull-up/Pull-down Register 1 Default = 00h n/a 7 Read/Write MEMDQ[31:0] Pull-down Control CM2CLKIN Pull-down Control CM2FIELD Pull-down Control CM2HREF Pull-down Control CM2VREF Pull-down Control CM2DAT[7:0] Pull-down Control 5 4 3 2 1 0 6 bit 5 MEMDQ[31:0] Pull-down Control This bit controls the state of the pull-down resistors on the SDRAM interface bidirectional data pins, MEMDQ[31:0]. When this bit = 0b, the pull-down resistors on the MEMDQ[31:0] pins are active. (default) When this bit = 1b, the pull-down resistors on the MEMDQ[31:0] pins are inactive. bit 4 CM2CLKIN Pull-down Control This bit controls the state of the pull-down resistor on the Camera2 interface clock input pin, CM2CLKIN (FP1IO8). When the Camera2 interface is configured for 24-bit RGB 8:8:8 streaming input (REG[0D46h] bits 2-1 = 10b), this bit also controls the pull-down resistor on the C2PCLKIN input pin (FP1IO23). When this bit = 0b, the pull-down resistor is active. (default) When this bit = 1b, the pull-down resistor is inactive. bit 3 CM2FIELD Pull-down Control This bit controls the state of the pull-down resistor on the Camera2 interface field input pin, CM2FIELD (FP1IO10). When the Camera2 interface is configured for 24-bit RGB 8:8:8 streaming input (REG[0D46h] bits 2-1 = 10b), this bit also controls the pull-down resistor on the C2DEIN input pin (FP1IO22). When this bit = 0b, the pull-down resistor is active. (default) When this bit = 1b, the pull-down resistor is inactive. Hardware Functional Specification Rev. 1.7 EPSON 193 Chapter 10 Registers S1D13515/S2D13515 bit 2 CM2HREF Pull-down Control This bit controls the state of the pull-down resistor on the Camera2 interface horizontal sync input pin, CM2HREF (FP1IO13). When the Camera2 interface is configured for 24bit RGB 8:8:8 streaming input (REG[0D46h] bits 2-1 = 10b), this bit also controls the pull-down resistor on the C2HSIN input pin (FP1IO20). When this bit = 0b, the pull-down resistor is active. (default) When this bit = 1b, the pull-down resistor is inactive. bit 1 CM2VREF Pull-down Control This bit controls the state of the pull-down resistor on the Camera2 interface vertical sync input pin, CM2VREF (FP1IO12). When the Camera2 interface is configured for 24-bit RGB 8:8:8 streaming input (REG[0D46h] bits 2-1 = 10b), this bit also controls the pulldown resistor on the C2VSIN input pin (FP1IO21). When this bit = 0b, the pull-down resistor is active. (default) When this bit = 1b, the pull-down resistor is inactive. bit 0 CM2DAT[7:0] Pull-down Control This bit controls the state of the pull-down resistors on the Camera2 interface bidirectional data pins, CM2DAT[7:0] (FP1IO[7:0]). When the Camera2 interface is configured for 24bit RGB 8:8:8 streaming input (REG[0D46h] bits 2-1 = 10b), this bit also controls the pull-down resistors on the C2RINx, C2GINx, and C2BINx input pins (FP1IO[17:0]). When this bit = 0b, the pull-down resistors are active. (default) When this bit = 1b, the pull-down resistors are inactive. 194 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.7 Keypad Registers The Keypad Interface scans for key presses using up to a 5x5 matrix. Each row, column input coordinate is associated with an interrupt which has independent enable, input polarity select, and status/clear controls. If a keypad smaller than 5x5 is used, the interrupt number associated with the coordinate does not change. KPC0 KPC1 KPC2 KPC3 KPC4 KPR0 0 5 10 15 20 KPR1 1 6 11 16 21 KPR2 2 7 12 17 22 KPR3 3 8 13 18 23 KPR4 4 9 14 19 24 Figure 10-2: Keypad Interface Example Hardware Functional Specification Rev. 1.7 EPSON 195 Chapter 10 Registers S1D13515/S2D13515 REG[01C0h] Keypad Control Register Default = 00h Read/Write n/a 7 6 5 4 3 2 Keypad Filter Enable Keypad Enable 1 0 bit 1 Keypad Filter Enable This bit controls glitch filtering for the keypad interface input pins (KPR[4:0] and KPC[4:0]). The sampling period for the filter is controlled using REG[01CCh] ~ REG[01CEh]. When this bit = 0b, the keypad filter is disabled. When this bit = 1b, the keypad filter is enabled. bit 0 Keypad Enable This bit controls glitch filtering for the keypad interface input pins (KPR[4:0] and KPC[4:0]). The sampling clock period for the filter is controlled using REG[01CCh] ~ REG[01CEh]. For detailed timing information, see Section 7.10, “Keypad Interface Timing” on page 123. When this bit = 0b, the keypad filter is disabled. When this bit = 1b, the keypad filter is enabled. Note After enabling the keypad, all interrupts in REG[01C4h] ~ REG[01C7h] should be cleared before enabling the Keypad Host Interrupt (REG[A08] bit 4 = 1b) 196 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[01C4h] Keypad Interrupt Enable Register 0 Default = 00h Read/Write Keypad Interrupt 7 Enable Keypad Interrupt 6 Enable Keypad Interrupt 5 Enable Keypad Interrupt 4 Enable Keypad Interrupt 3 Enable Keypad Interrupt 2 Enable Keypad Interrupt 1 Enable Keypad Interrupt 0 Enable 7 6 5 4 3 2 1 0 REG[01C5h] Keypad Interrupt Enable Register 1 Default = 00h Read/Write Keypad Interrupt 15 Enable Keypad Interrupt 14 Enable Keypad Interrupt 13 Enable Keypad Interrupt 12 Enable Keypad Interrupt 11 Enable Keypad Interrupt 10 Enable Keypad Interrupt 9 Enable Keypad Interrupt 8 Enable 7 6 5 4 3 2 1 0 REG[01C6h] Keypad Interrupt Enable Register 2 Default = 00h Read/Write Keypad Interrupt 23 Enable Keypad Interrupt 22 Enable Keypad Interrupt 21 Enable Keypad Interrupt 20 Enable Keypad Interrupt 19 Enable Keypad Interrupt 18 Enable Keypad Interrupt 17 Enable Keypad Interrupt 16 Enable 7 6 5 4 3 2 1 0 REG[01C7h] Keypad Interrupt Enable Register 3 Default = 00h Read/Write Keypad Interrupt 24 Enable n/a 7 6 REG[01C7h] bit 0 REG[01C6h] bits 7-0 REG[01C5h] bits 7-0 REG[01C4h] bits 7-0 5 4 3 2 1 0 Keypad Interrupt [24:0] Enable These bits control Keypad Interrupts 24-0 and determine if a Keypad Interrupt occurs in REG[0A02h] bit 4. Each keypad interrupt is associated with a specific row, column coordinate as shown in Figure 10-2: “Keypad Interface Example” on page 195. The status of each interrupt is indicated in REG[01D0h] ~ REG[01D3h] and the polarity of each interrupt can be changed using REG[01C8h] ~ REG[01CBh]. When this bit = 0b, Keypad Interrupt X is disabled. When this bit = 1b, Keypad Interrupt X is enabled. Hardware Functional Specification Rev. 1.7 EPSON 197 Chapter 10 Registers S1D13515/S2D13515 REG[01C8h] Keypad Input Polarity Register 0 Default = 00h Read/Write Keypad Input 7 Polarity Select Keypad Input 6 Polarity Select Keypad Input 5 Polarity Select Keypad Input 4 Polarity Select Keypad Input 3 Polarity Select Keypad Input 2 Polarity Select Keypad Input 1 Polarity Select Keypad Input 0 Polarity Select 7 6 5 4 3 2 1 0 REG[01C9h] Keypad Input Polarity Register 1 Default = 00h Read/Write Keypad Input 15 Polarity Select Keypad Input 14 Polarity Select Keypad Input 13 Polarity Select Keypad Input 12 Polarity Select Keypad Input 11 Polarity Select Keypad Input 10 Polarity Select Keypad Input 9 Polarity Select Keypad Input 8 Polarity Select 7 6 5 4 3 2 1 0 REG[01CAh] Keypad Input Polarity Register 2 Default = 00h Read/Write Keypad Input 23 Polarity Select Keypad Input 22 Polarity Select Keypad Input 21 Polarity Select Keypad Input 20 Polarity Select Keypad Input 19 Polarity Select Keypad Input 18 Polarity Select Keypad Input 17 Polarity Select Keypad Input 16 Polarity Select 7 6 5 4 3 2 1 0 REG[01CBh] Keypad Input Polarity Register 3 Default = 00h Read/Write Keypad Input 24 Polarity Select n/a 7 6 REG[01CBh] bit 0 REG[01CAh] bits 7-0 REG[01C9h] bits 7-0 REG[01C8h] bits 7-0 5 4 3 2 1 0 Keypad Input [24:0] Polarity Select These bits specify the polarity for Keypad inputs 24-0. Each keypad input is associated with a specific row, column coordinate as shown in Figure 10-2: “Keypad Interface Example” on page 195. When this bit = 0b, the polarity of Keypad Input X is inverted and will cause the corresponding Keypad Interrupt to occur, if enabled, when the key is released. When this bit = 1b, the polarity of Keypad Input X is normal and will cause the corresponding Keypad Interrupt to occur, if enabled, when the key is pressed. Note 1. These bits should only be changed when the keypad is disabled (REG[01C0h] bit 0 = 0b). 2. When a Keypad Input Polarity bit is changed from 1b to 0b, 2 keypad sampling clocks must take place before clearing the corresponding Interrupt Status bit in REG[01D0h] ~ REG[01D3h]. 198 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[01CCh] Keypad Filter Sampling Period Register 0 Default = 00h Read/Write Keypad Filter Sampling Period bits 7-0 7 6 5 4 3 2 1 REG[01CDh] Keypad Filter Sampling Period Register 1 Default = 00h 0 Read/Write Keypad Filter Sampling Period bits 15-8 7 6 5 4 3 2 1 REG[01CEh] Keypad Filter Sampling Period Register 2 Default = 00h Read/Write n/a 7 6 REG[01CEh] bits 3-0 REG[01CDh] bits 7-0 REG[01CCh] bits 7-0 0 Keypad Filter Sampling Period bits 19-16 5 4 3 2 1 0 Keypad Filter Sampling Period [19:0] When the Keypad Filter is enabled (REG[01C0h] bit 1 = 1b), these bits specify the sampling clock period for the keypad input glitch filter. The value in these bits specifies the number of keypad clocks between each sample of the keypad input pins. For detailed timing information, see Keypad Interface Timing section. The keypad clock is derived from the input clock INCLK1 which is sourced from either CLKI or OSCI. The keypad clock can be further divided using the Keypad Clock Divide Select bits, REG[01D4h] ~ REG[01D5h]. When the Keypad Filter is enabled, these bits should be set according to the following formula. Minimum Key Press Time Filter sampling period = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Keypad Clock Period × number of clocks per column × number of columns Where: Filter sampling period is defined by REG[01CCh] ~ REG[01CEh] Minimum Key Press Time is the shortest key press that will be detected Keypad Clock Period is defined by REG[01D4h] ~ REG[01D5h] number of clocks per column is 4 number of columns is 5 For example, use the following calculation to detect a minimum keypress of 10ms for a keypad clock period of 30us (32.68KHz). Filter Sampling Period = 10000us / (30us x 4 x 5) = 10000 / 600 = 16.667 = 16 Hardware Functional Specification Rev. 1.7 EPSON 199 Chapter 10 Registers S1D13515/S2D13515 REG[01D0h] Keypad Interrupt Raw Status/Clear Register 0 Default = 00h Read/Write Keypad Interrupt 7 Raw Status/ Clear Keypad Interrupt 6 Raw Status/ Clear Keypad Interrupt 5 Raw Status/ Clear Keypad Interrupt 4 Raw Status/ Clear Keypad Interrupt 3 Raw Status/ Clear Keypad Interrupt 2 Raw Status/ Clear Keypad Interrupt 1 Raw Status/ Clear Keypad Interrupt 0 Raw Status/ Clear 7 6 5 4 3 2 1 0 REG[01D1h] Keypad Interrupt Raw Status/Clear Register 1 Default = 00h Read/Write Keypad Interrupt 15 Raw Status/ Clear Keypad Interrupt 14 Raw Status/ Clear Keypad Interrupt 13 Raw Status/ Clear Keypad Interrupt 12 Raw Status/ Clear Keypad Interrupt 11 Raw Status/ Clear Keypad Interrupt 10 Raw Status/ Clear Keypad Interrupt 9 Raw Status/ Clear Keypad Interrupt 8 Raw Status/ Clear 7 6 5 4 3 2 1 0 REG[01D2h] Keypad Interrupt Raw Status/Clear Register 2 Default = 00h Read/Write Keypad Interrupt 23 Raw Status/ Clear Keypad Interrupt 22 Raw Status/ Clear Keypad Interrupt 21 Raw Status/ Clear Keypad Interrupt 20 Raw Status/ Clear Keypad Interrupt 19 Raw Status/ Clear Keypad Interrupt 18 Raw Status/ Clear Keypad Interrupt 17 Raw Status/ Clear Keypad Interrupt 16 Raw Status/ Clear 7 6 5 4 3 2 1 0 REG[01D3h] Keypad Interrupt Raw Status/Clear Register 3 Default = 00h Read/Write Keypad Interrupt 24 Raw Status/ Clear n/a 7 6 REG[01D3h] bits 7-0 REG[01D2h] bits 7-0 REG[01D1h] bits 7-0 REG[01D0h] bit 0 5 4 3 2 1 0 Keypad Interrupt [24:0] Raw Status/Clear For Reads: These bits indicate the raw status of the corresponding Keypad Interrupt, regardless of whether or not the corresponding Keypad Interrupt is enabled (see REG[01C4h] ~ REG[01C7h]). These bits indicate the status of the keypad interrupt associated with a specific row, column coordinate as shown in Figure 10-2: “Keypad Interface Example” on page 183. These bits are not masked by the Keypad Interrupt [24:0] Enable bits in REG[01C4h] ~ REG[01C7h]. When this bit = 0b, Keypad Interrupt X has not occurred. When this bit = 1b, Keypad Interrupt X has occurred which indicates that the corresponding key has been pressed/released according to the setting of the Keypad Input [24:0] Polarity Select bits (REG[01C8h] ~ REG[01CBh]). For Writes: Writing a 0b to this bit has no effect. Writing a 1b then 0b to this bit clears the interrupt status. Note After enabling the keypad, all interrupts in REG[01C4h] ~ REG[01C7h] should be cleared before enabling the Keypad Host Interrupt (REG[A08] bit 4 = 1b) 200 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[01D4h] Keypad Clock Configuration Register 0 Default = 00h Read/Write Keypad Clock Divide Select bits 7-0 7 6 5 4 3 2 1 REG[01D5h] Keypad Clock Configuration Register 1 Default = 00h Read/Write n/a 7 6 REG[01D5h] bits 3-0 REG[01D4h] bits 7-0 Keypad Clock Divide Select bits 11-8 5 4 3 2 1 Read/Write n/a bits 4-0 0 Keypad Clock Divide Select [11:0] These bits specify the clock divide ratio for the keypad clock. The keypad clock is derived from the input clock INCLK1 which is sourced from either CLKI or OSCI. For details, see Chapter 9, “Clocks” on page 128. The keypad clock divide ratio is calculated using the following formula. Keypad Clock Divide Ratio = 1: (REG[01D5h] bits 3-0, REG[01D4h] bits 7-0) + 1 REG[01D6h] Keypad GPI Function Enable Register Default = 00h 7 0 Keypad GPI Function Enable bits 4-0 6 5 4 3 2 1 0 Keypad GPI Function Enable bits [4:0] The keypad interface row pins (KPR[4:0]) can be configured as general purpose input pins which can generate edge-trigger interrupts. These bits control the GPI function for each corresponding KPR[4:0] pin. When configured as GPI pins, the status of each associated interrupt is indicated by REG[01D0h] bits 4-0 and the polarity of each interrupt can be controlled using REG[01C8h] bits 4-0. If the filter function is enabled (REG[01C0h] bit 1 = 1b), an interrupt is generated only when two consecutive samples (as controlled by the Keypad Filter Sampling Period bits in REG[01CCh] ~ REG[01CEh]) are the same. When this bit = 0b, the corresponding KPR[4:0] pin functions as a scan input pin for the keypad interface. When this bit = 1b, the corresponding KPR[4:0] pin functions as a general purpose input which can generate edge-trigger interrupts. Note If bit 0 = 1b, Keypad Interrupts 5, 10, 15, 20 are disabled. If bit 1 = 1b, Keypad Interrupts 6, 11, 16, 21 are disabled. If bit 2 = 1b, Keypad Interrupts 7, 12, 17, 22 are disabled. If bit 3 = 1b, Keypad Interrupts 8, 13, 18, 23 are disabled. If bit 4 = 1b, Keypad Interrupts 9, 14, 19, 24 are disabled. Hardware Functional Specification Rev. 1.7 EPSON 201 Chapter 10 Registers S1D13515/S2D13515 10.4.8 PWM Registers REG[0200h] PWM Control Register Default = 00h PWM Rate bits 2-0 7 bits 7-5 6 Read/Write PWM Output Polarity 5 4 PWM Logic Clock Divide Select bits 3-0 3 2 1 0 PWM Rate bits [2:0] These bits determine the M value used for slope calculations. These bits determine the rate (M value) at which the duty cycle of the Pulse Cycles is increased/decreased during duty cycle ramp-up/ramp-down. During ramp-up/ramp-down of the duty cycle of Pulse Cycles, the duty cycle is increased/decreased by a value (1/16 x N), where N is determined by the corresponding PWM1/PWM2 Slope bits (see REG[0203h] bits 7-4 or REG[0206h] bits 74), every M Pulse Clock cycles. These bits have no effect when the Slope bits are set to 0. These bits have no effect when the Slope bits are set to 0. REG[0200h] bits 7-5 = M - 1 bit 4 202 PWM Output Polarity This bit specifies the polarity of the PWM1/PWM2 outputs pin relative to the digital value output by the PWM circuit. When this bit = 0b, the PWM outputs are normal which means that the PWM1/PWM2 pin voltage is driven low when a logic 1 is driven from the PWM circuit and driven high when a logic 0 is driven from the PWM circuit. When this bit = 1b, the PWM outputs are inverted which means that the PWM1/PWM2 pin voltage is driven high when a logic 1 is driven from the PWM circuit and driven low when a logic 0 is driven from the PWM circuit. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bits 3-0 PWM Logic Clock Divide Select bits [3:0] These bits specify the divide ratio used to generate the PWM Logic Clock which is used to drive the PWM circuits. The PWM Logic Clock is derived from the internal PWM Source Clock (PWMSRCCLK) which is sourced from SYSCLK and is configured using the PWMSRCCLK Divide Select bits (REG[0034h] ~ REG[0035h]). For further details on PWMSRCCLK, see Section Chapter 9, “Clocks” on page 128. Table 10-27: PWM Logic Clock Divide Selection REG[0200h] bits 3-0 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b ~ 1111b PWM Logic Clock Divide Ratio 1:1 2:1 4:1 6:1 8:1 10:1 12:1 14:1 16:1 Reserved (PWM Logic Clock is stopped) Note BOTH PWM1 and PWM2 must be disabled when bits [3:0] are changed, then re-enabled. REG[0201h] PWM1 Enable/On Register Default = 00h Read/Write PWM1 Enable 7 PWM1 On Time bits 6-0 6 5 4 3 2 1 0 bit 7 PWM1 Enable This bit controls PWM1 output. When this bit = 0b, PWM1 output is disabled (becomes logic 0 before the PWM Output Polarity specified by REG[0200h] bit 4 is applied). When this bit = 1b, PWM1 output is enabled. bits 6-0 PWM1 On Time bits [6:0] These bits specify the point at which the PWM1 LED turns “on” relative to the start of the 128 clock pulse cycle. A value of 0 means the LED starts the turn on sequence immediately at the start of the 128 clock cycle. For further information on using PWM, see Section Chapter 19, “Pulse Width Modulation (PWM)” on page 507. Hardware Functional Specification Rev. 1.7 EPSON 203 Chapter 10 Registers S1D13515/S2D13515 REG[0202h] PWM1 Off Register Default = 00h Read/Write n/a 7 PWM1 Off Time bits 6-0 6 bits 6-0 5 4 3 2 1 0 PWM1 Off Time bits [6:0] These bits specify the point at which the PWM1 LED turns “off” relative to the start of the 128 clock pulse cycle. This value must be greater than the PWM1 On Duration specified in REG[0201h] bits 6-0. For further information on using PWM, see Section Chapter 19, “Pulse Width Modulation (PWM)” on page 507. REG[0202h] bits 6-0 = PWM1 Off Duration - 1 Note If a value of 7Fh is specified, the LED is on for the entire duration of the PWM1 duty cycle, REG[0203h] bits 3-0. REG[0203h] PWM1 Control Register Default = 00h Read/Write PWM1 Slope bits 3-0 7 6 PWM1 Maximum Duty Cycle bits 3-0 5 4 3 2 1 0 bits 7-4 PWM1 Slope bits [3:0] Within each Repeat Cycle consisting of 128 Pulse Clocks, the PWM1 output can start from completely off (0/16 duty cycle), ramp up to the maximum duty cycle specified REG[0203h] bits 3-0, and then ramp down back to completely off. The rate in which the duty cycle is incremented/decremented during ramp-up/ramp-down is determined by REG[0200h] bits 7-5 and for each increment/decrement step the duty cycle is increased/decreased by (1/16 x N) where N is the decimal value represented by these bits. If these bits are set to 0h, the duty cycle immediately changes from completely off, to the maximum duty cycle as specified by the PWM1 Maximum Duty Cycle bits. bits 3-0 PWM1 Maximum Duty Cycle bits [3:0] These bits specify the “full on” duty cycle for PWM1 which determines the maximum brightness that the LED reaches at the peak of the pulse. A value of Fh indicates full brightness (i.e. continuously on). A value of 0h means the LED is on for 1/16th of the time. Note When the PWM1 Slope (REG[0203h] bits 7-4) is non-zero, the PWM1 Duty Cycle must not be set to 1111b (Fh). 204 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0204h] PWM2 Enable/On Register Default = 00h Read/Write PWM2 Enable 7 PWM2 On Time bits 6-0 6 5 4 3 2 1 0 bit 7 PWM2 Enable This bit controls PWM2 output. When this bit = 0b, PWM2 output is disabled (becomes logic 0 before the PWM Output Polarity specified by REG[0200h] bit 4 is applied). When this bit = 1b, PWM2 output is enabled. bits 6-0 PWM2 On Time bits [6:0] These bits specify the point at which the PWM2 LED turns “on” relative to the start of the 128 clock pulse cycle. A value of 0 means the LED starts the turn on sequence immediately at the start of the 128 clock cycle. For further information on using PWM, see Section Chapter 19, “Pulse Width Modulation (PWM)” on page 507. REG[0205h] PWM2 Off Register Default = 00h Read/Write n/a 7 bits 6-0 PWM2 Off Time bits 6-0 6 5 4 3 2 1 0 PWM2 Off Time bits [6:0] These bits specify the point at which the PWM2 LED turns “off” relative to the start of the 128 clock pulse cycle. This value must be greater than the PWM2 On Duration specified in REG[0204h] bits 6-0. For further information on using PWM, see Section Chapter 19, “Pulse Width Modulation (PWM)” on page 507. REG[0205h] bits 6-0 = PWM2 Off Duration - 1 Note If a value of 7Fh is specified, the LED is on for the entire duration of the PWM2 duty cycle, REG[0206h] bits 3-0. Hardware Functional Specification Rev. 1.7 EPSON 205 Chapter 10 Registers S1D13515/S2D13515 REG[0206h] PWM2 Control Register Default = 00h Read/Write PWM2 Slope bits 3-0 7 6 PWM2 Maximum Duty Cycle bits 3-0 5 4 3 2 1 0 bits 7-4 PWM2 Slope bits [3:0] Within each Repeat Cycle consisting of 128 Pulse Clocks, the PWM2 output can start from completely off (0/16 duty cycle), ramp up to the maximum duty cycle specified REG[0206h] bits 3-0, and then ramp down back to completely off. The rate in which the duty cycle is incremented/decremented during ramp-up/ramp-down is determined by REG[0200h] bits 7-5 and for each increment/decrement step the duty cycle is increased/decreased by (1/16 x N) where N is the decimal value represented by these bits. If these bits are set to 0h, the duty cycle immediately changes from completely off, to the maximum duty cycle as specified by the PWM2 Maximum Duty Cycle bits. bits 3-0 PWM2 Maximum Duty Cycle bits [3:0] These bits specify the “full on” duty cycle for PWM2 which determines the maximum brightness that the LED reaches at the peak of the pulse. A value of Fh indicates full brightness (i.e. continuously on). A value of 0h means the LED is on for 1/16th of the time. Note When the PWM2 Slope (REG[0206h] bits 7-4) is non-zero, the PWM2 Duty Cycle must not be set to 1111b (Fh). 206 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.9 SDRAM Read/Write Buffer Registers SDRAM Buffer 0 and SDRAM Buffer 1 are designed to work together so that while one buffer is busy (the SDRAM Buffer 0/1 Start bit = 1b), the other buffer can also be started. The second buffer will wait for the first buffer to complete the transfer, and then will start the next transfer. The SDRAM Buffers are 128 bytes in size. See Section Chapter 18, “SDRAM Read/Write Buffer” on page 502 for further information. Note When using SPI, I2C, or any interface without WAIT, SDRAM must be accessed using the SDRAM Read/Write Buffers. REG[0240h] SDRAM Buffer 0 Configuration Register Default = 00h Read/Write n/a 7 6 5 4 3 2 SDRAM Buffer 0 Done Interrupt Enable SDRAM Buffer 0 Mode 1 0 bit 1 SDRAM Buffer 0 Done Interrupt Enable This bit controls whether the SDRAM Buffer 0 Done Interrupt can generate an interrupt request (see also REG[0A06h] bit 5). The status of this interrupt is indicated by the SDRAM Buffer 0 Done Status/Clear bit, REG[0242h] bit 3. When this bit = 0b, the interrupt is disabled. When this bit = 1b, the interrupt is enabled. bit 0 SDRAM Buffer 0 Mode This bit selects whether SDRAM Buffer 0 is used for reading from or writing to the SDRAM. When this bit = 0b, SDRAM Buffer 0 is used for writing data from the Host to SDRAM. When this bit = 1b, SDRAM Buffer 0 is used for reading data from SDRAM to the Host. Note When the SDRAM Buffer 0 mode is changed between read and write mode, the Read/Write Buffer FIFO is reset. Hardware Functional Specification Rev. 1.7 EPSON 207 Chapter 10 Registers S1D13515/S2D13515 REG[0242h] SDRAM Buffer 0 Control Register Default = 00h Read/Write n/a 7 bit 3 6 5 4 SDRAM Buffer 0 Done Interrupt Status/Clear SDRAM Buffer 0 Rectangular Increment (WO) SDRAM Buffer 0 Load Address (WO) SDRAM Buffer 0 Start 3 2 1 0 SDRAM Buffer 0 Done Interrupt Status/Clear This bit indicates the status of the SDRAM Buffer 0 Done Interrupt which occurs when a transfer between SDRAM Buffer 0 and the SDRAM has finished. This interrupt can generate an interrupt request when the SDRAM Buffer 0 Done Interrupt Enable bit (REG[0240h] bit 1) and the SDRAM Read/Write Buffers Interrupt Enable bit (REG[0A06h] bit 5) are set to 1b. When this bit = 0b, a SDRAM Buffer 0 Done Interrupt has not occurred. When this bit = 1b, a SDRAM Buffer 0 Done Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 2 SDRAM Buffer 0 Rectangular Increment (Write Only) This bit determines the type of address increment done to the SDRAM Buffer 0 Target Address (REG[0248h] ~ REG[024Bh]) at the completion of a SDRAM Buffer 0 transfer. This bit should be set at the same time as the SDRAM Buffer 0 Start bit (REG[0242h] bit 0) is set. Writing a 0b to this bit selects linear address incrementing. Writing a 1b to this bit selects rectangular address incrementing. The rectangular increment value is specified by the SDRAM Buffer 0 Rectangular Increment Value bits (see REG[0260h] ~ REG[0261h]). bit 1 SDRAM Buffer 0 Load Address (Write Only) This bit determines whether the SDRAM Buffer 0 Target Address (REG[0248h] ~ REG[024Bh]) is loaded before starting a SDRAM Buffer 0 transfer. This bit should be set at the same time as the SDRAM Buffer 0 Start bit (REG[0242h] bit 0) is set. Writing a 0b to this bit causes the SDRAM Buffer 0 Target Address to be ignored and the SDRAM Buffer 0 transfer uses the current value of the internal target address register (resulting from the end of the previous transfer). Writing a 1b to this bit causes the SDRAM Buffer 0 Target Address (REG[0248h] ~ REG[024Bh]) to be loaded before starting the SDRAM Buffer 0 transfer. bit 0 SDRAM Buffer 0 Start This bit starts a transfer between SDRAM Buffer 0 and the SDRAM. The type of transfer (SDRAM Buffer 0 to SDRAM or SDRAM to SDRAM Buffer 0) is determined by the SDRAM Buffer 0 Mode bit, REG[0240h] bit 0. If necessary, the SDRAM Buffer 0 Rectangular Increment and SDRAM Buffer 0 Load Address bits should be set at the same time as this bit. Writing a 0b to this bit has no effect. Writing a 1b to this bit starts a transfer between SDRAM Buffer 0 and the SDRAM. This bit remains at 1b during the transfer, and returns to 0b when the transfer completes. 208 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0244h] SDRAM Buffer 0 Read Bytes Register Default = 00h Read/Write SDRAM Buffer 0 Read Bytes bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 SDRAM Buffer 0 Read Bytes bits [7:0] These bits specify the number of bytes to read when the SDRAM Buffer 0 Mode is set for read mode, REG[0240h] bit 0 = 1b. The minimum value is 0 and the maximum value is 128. REG[0248h] SDRAM Buffer 0 Target Address Register 0 Default = 00h Read/Write SDRAM Buffer 0 Target Address bits 7-0 7 6 5 4 3 2 1 REG[0249h] SDRAM Buffer 0 Target Address Register 1 Default = 00h 0 Read/Write SDRAM Buffer 0 Target Address bits 15-8 7 6 5 4 3 2 1 REG[024Ah] SDRAM Buffer 0 Target Address Register 2 Default = 00h 0 Read/Write SDRAM Buffer 0 Target Address bits 23-16 7 6 5 4 3 2 1 REG[024Bh] SDRAM Buffer 0 Target Address Register 3 Default = 00h 0 Read/Write SDRAM Buffer 0 Target Address bits 31-24 7 REG[024Bh] bits 7-0 REG[024Ah] bits 7-0 REG[0249h] bits 7-0 REG[0248h] bits 7-0 6 5 4 3 2 1 0 SDRAM Buffer 0 Target Address bits [31:0] These bits specify the target address in SDRAM for transfers between SDRAM Buffer 0 and the SDRAM. These bits are automatically incremented at the end of a read/write operation (when REG[0242h] bit 0 returns to 0b) according to the setting of the SDRAM Buffer 0 Rectangular Increment bit, REG[0242h] bit 2. Hardware Functional Specification Rev. 1.7 EPSON 209 Chapter 10 Registers S1D13515/S2D13515 REG[024Ch] SDRAM Buffer 0 Data Port Register 0 Default = 00h Read/Write SDRAM Buffer 0 Data Port bits 7-0 7 6 5 4 3 2 1 REG[024Dh] SDRAM Buffer 0 Data Port Register 1 Default = 00h 0 Read/Write SDRAM Buffer 0 Data Port bits 15-8 7 6 REG[024Dh] bits 7-0 REG[024Ch] bits 7-0 5 4 3 2 1 0 SDRAM Buffer 0 Data Port bits [15:0] These bits are the data port where the Host reads from or writes to SDRAM Buffer 0. These registers are also “aliased” in the range REG[0300h] ~ REG[037Fh]. For example, writing to REG[0318h] is the same as writing to REG[024Ch]. The purpose of this “aliased” address range is for Direct host interfaces with “burst” mode which have incrementing addresses. When the host interface is 16-bit and both byte and 16-bit word accesses of the SDRAM Buffer port is desired, an even number of byte accesses are required before a 16-bit word access is possible. Note When using SPI for SDRAM read accesses, the number of bytes specified by the SDRAM Buffer 0 Read Bytes bits (REG[0244h] bits 7-0) must be read from this port without interruption. REG[0250h] SDRAM Buffer 1 Configuration Register Default = 00h Read/Write n/a 7 6 5 4 3 2 SDRAM Buffer 1 Done Interrupt Enable SDRAM Buffer 1 Mode 1 0 bit 1 SDRAM Buffer 1 Done Interrupt Enable This bit controls whether the SDRAM Buffer 1 Done Interrupt can generate an interrupt request (see also REG[0A06h] bit 5). The status of this interrupt is indicated by the SDRAM Buffer 1 Done Status/Clear bit, REG[0252h] bit 3. When this bit = 0b, the interrupt is disabled. When this bit = 1b, the interrupt is enabled. bit 0 SDRAM Buffer 1 Mode This bit selects whether SDRAM Buffer 1 is used for reading from or writing to the SDRAM. When this bit = 0b, SDRAM Buffer 1 is used for writing data from the Host to SDRAM. When this bit = 1b, SDRAM Buffer 1 is used for reading data from SDRAM to the Host. Note When the SDRAM Buffer 1 mode is changed between read and write mode, the Read/Write Buffer FIFO is reset. 210 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0252h] SDRAM Buffer 1 Control Register Default = 00h Read/Write n/a 7 bit 3 6 5 4 SDRAM Buffer 1 Done Interrupt Status/Clear SDRAM Buffer 1 Rectangular Increment (WO) SDRAM Buffer 1 Load Address (WO) SDRAM Buffer 1 Start 3 2 1 0 SDRAM Buffer 1 Done Interrupt Status/Clear This bit indicates the status of the SDRAM Buffer 1 Done Interrupt which occurs when a transfer between SDRAM Buffer 1 and the SDRAM has finished. This interrupt can generate an interrupt request when the SDRAM Buffer 1 Done Interrupt Enable bit (REG[0250h] bit 1) and the SDRAM Read/Write Buffers Interrupt Enable bit (REG[0A06h] bit 5) are set to 1b. When this bit = 0b, a SDRAM Buffer 1 Done Interrupt has not occurred. When this bit = 1b, a SDRAM Buffer 1 Done Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 2 SDRAM Buffer 1 Rectangular Increment (Write Only) This bit determines the type of address increment done to the SDRAM Buffer 1 Target Address (REG[0258h] ~ REG[025Bh]) at the completion of a SDRAM Buffer 1 transfer. This bit should be set at the same time as the SDRAM Buffer 1 Start bit (REG[0252h] bit 0) is set. Writing a 0b to this bit selects linear address incrementing. Writing a 1b to this bit selects rectangular address incrementing. The rectangular increment value is specified by the SDRAM Buffer 1 Rectangular Increment Value bits (see REG[0262h] ~ REG[0263h]). bit 1 SDRAM Buffer 1 Load Address (Write Only) This bit determines whether the SDRAM Buffer 1 Target Address (REG[0258h] ~ REG[025Bh]) is loaded before starting a SDRAM Buffer 1 transfer. This bit should be set at the same time as the SDRAM Buffer 1 Start bit (REG[0252h] bit 0) is set. Writing a 0b to this bit causes the SDRAM Buffer 1 Target Address to be ignored and the SDRAM Buffer 1 transfer uses the current value of the internal target address register (resulting from the end of the previous transfer). Writing a 1b to this bit causes the SDRAM Buffer 1 Target Address (REG[0258h] ~ REG[025Bh]) to be loaded before starting the SDRAM Buffer 1 transfer. bit 0 SDRAM Buffer 1 Start This bit starts a transfer between SDRAM Buffer 1 and the SDRAM. The type of transfer (SDRAM Buffer 1 to SDRAM or SDRAM to SDRAM Buffer 1) is determined by the SDRAM Buffer 1 Mode bit, REG[0250h] bit 0. If necessary, the SDRAM Buffer 1 Rectangular Increment and SDRAM Buffer 1 Load Address bits should be set at the same time as this bit. Writing a 0b to this bit has no effect. Writing a 1b to this bit starts a transfer between SDRAM Buffer 1 and the SDRAM. This bit remains at 1b during the transfer, and returns to 0b when the transfer completes. Hardware Functional Specification Rev. 1.7 EPSON 211 Chapter 10 Registers S1D13515/S2D13515 REG[0254h] SDRAM Buffer 1 Read Bytes Register Default = 00h Read/Write SDRAM Buffer 1 Read Bytes bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 SDRAM Buffer 1 Read Bytes bits [7:0] These bits specify the number of bytes to read when the SDRAM Buffer 1 Mode is set for read mode, REG[0250h] bit 0 = 1b. The minimum value is 0 and the maximum value is 128. REG[0258h] SDRAM Buffer 1 Target Address Register 0 Default = 00h Read/Write SDRAM Buffer 1 Target Address bits 7-0 7 6 5 4 3 2 1 REG[0259h] SDRAM Buffer 1 Target Address Register 1 Default = 00h 0 Read/Write SDRAM Buffer 1 Target Address bits 15-8 7 6 5 4 3 2 1 REG[025Ah] SDRAM Buffer 1 Target Address Register 2 Default = 00h 0 Read/Write SDRAM Buffer 1 Target Address bits 23-16 7 6 5 4 3 2 1 REG[025Bh] SDRAM Buffer 1 Target Address Register 3 Default = 00h 0 Read/Write SDRAM Buffer 1 Target Address bits 31-24 7 REG[025Bh] bits 7-0 REG[025Ah] bits 7-0 REG[0259h] bits 7-0 REG[0258h] bits 7-0 212 6 5 4 3 2 1 0 SDRAM Buffer 1 Target Address bits [31:0] These bits specify the target address in SDRAM for transfers between SDRAM Buffer 1 and the SDRAM. These bits are automatically incremented at the end of a read/write operation (when REG[0252h] bit 0 returns to 0b) according to the setting of the SDRAM Buffer 1 Rectangular Increment bit, REG[0252h] bit 2. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[025Ch] SDRAM Buffer 1 Data Port Register 0 Default = 00h Read/Write SDRAM Buffer 1 Data Port bits 7-0 7 6 5 4 3 2 1 REG[025Dh] SDRAM Buffer 1 Data Port Register 1 Default = 00h 0 Read/Write SDRAM Buffer 1 Data Port bits 15-8 7 6 REG[025Dh] bits 7-0 REG[025Ch] bits 7-0 5 4 3 2 1 0 SDRAM Buffer 1 Data Port bits [15:0] These bits are the data port where the Host reads from or writes to SDRAM Buffer 1. These registers are also “aliased” in the range REG[0380h] ~ REG[03FFh]. For example, writing to REG[0398h] is the same as writing to REG[025Ch]. The purpose of this “aliased” address range is for Direct host interfaces with “burst” mode which have incrementing addresses. When the host interface is 16-bit and both byte and 16-bit word accesses of the SDRAM Buffer port is desired, an even number of byte accesses are required before a 16-bit word access is possible. Note When using SPI for SDRAM read accesses, the number of bytes specified by the SDRAM Buffer 1 Read Bytes bits (REG[0254h] bits 7-0) must be read from this port without interruption. REG[0260h] SDRAM Buffer 0 Rectangular Increment Register 0 Default = 00h Read/Write SDRAM Buffer 0 Rectangular Increment Value bits 7-0 7 6 5 4 3 2 1 REG[0261h] SDRAM Buffer 0 Rectangular Increment Register 1 Default = 00h n/a 7 REG[0261h] bits 4-0 REG[0260h] bits 7-0 0 Read/Write SDRAM Buffer 0 Rectangular Increment Value bits 12-8 6 5 4 3 2 1 0 SDRAM Buffer 0 Rectangular Increment Value bits [12:0] When the SDRAM Buffer 0 Rectangular Increment bit is set to 1b (REG[0242h] bit 2 = 1b), these bits specify the value that is added to the SDRAM Buffer 0 Target Address (REG[0248h] ~ REG[024Bh]) when the SDRAM Buffer 0 transfer completes. This method is used to perform rectangular image reads/writes between the Host and SDRAM. Hardware Functional Specification Rev. 1.7 EPSON 213 Chapter 10 Registers S1D13515/S2D13515 REG[0262h] SDRAM Buffer 1 Rectangular Increment Register 0 Default = 00h Read/Write SDRAM Buffer 1 Rectangular Increment Value bits 7-0 7 6 5 4 3 2 1 REG[0263h] SDRAM Buffer 1 Rectangular Increment Register 1 Default = 00h n/a 7 Read/Write SDRAM Buffer 1 Rectangular Increment Value bits 12-8 6 REG[0263h] bits 4-0 REG[0262h] bits 7-0 0 5 4 3 2 1 0 SDRAM Buffer 1 Rectangular Increment Value bits [12:0] When the SDRAM Buffer 1 Rectangular Increment bit is set to 1b (REG[0252h] bit 2 = 1b), these bits specify the value that is added to the SDRAM Buffer 1 Target Address (REG[0258h] ~ REG[025Bh]) when the SDRAM Buffer 1 transfer completes. This method is used to perform rectangular image reads/writes between the Host and SDRAM. REG[0264h] SDRAM Read/Write Buffer Internal Address Register 0 Default = 00h Read Only SDRAM Read/Write Buffer Internal Address bits 7-0 7 6 5 4 3 2 1 REG[0265h] SDRAM Read/Write Buffer Internal Address Register 1 Default = 00h 0 Read Only SDRAM Read/Write Buffer Internal Address bits 15-8 7 6 5 4 3 2 1 REG[0266h] SDRAM Read/Write Buffer Internal Address Register 2 Default = 00h 0 Read Only SDRAM Read/Write Buffer Internal Address bits 23-16 7 6 5 4 3 2 1 REG[0267h] SDRAM Read/Write Buffer Internal Address Register 3 Default = 00h 0 Read Only SDRAM Read/Write Buffer Internal Address 31-24 7 REG[0267h] bits 7-0 REG[0266h] bits 7-0 REG[0265h] bits 7-0 REG[0264h] bits 7-0 6 5 4 3 2 1 0 SDRAM Read/Write Buffer Internal Address bits [31:0] (Read Only) These bits specify the internal memory pointer of the SDRAM Read/Write Buffer. Note These bits are updated at the end of each SDRAM Buffer transfer. 214 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0300h] ~ REG[037Eh] (Even Addresses) Aliased SDRAM Buffer 0 Data Port Register 0 Default = 00h Read/Write Aliased SDRAM Buffer 0 Data Port bits 7-0 7 6 5 4 3 2 1 REG[0301h] ~ REG[037Fh] (Odd Addresses) Aliased SDRAM Buffer 0 Data Port Register 1 Default = 00h 0 Read/Write Aliased SDRAM Buffer 0 Data Port bits 15-8 7 REG[0300h] bits 7-0 through REG[037Fh] bits 7-0 6 5 4 3 2 1 0 Aliased SDRAM Buffer 0 Data Port bits [15:0] These are the “aliased” registers of the SDRAM Buffer 0 Data Port REG[024Ch] ~ REG[024Dh]. Writing to REG[0300h], REG[0302h], REG0304h], REG[0306h], and so on, is the same as writing to REG[024Ch]. Writing to REG[0301h], REG[0303h], REG0304h], REG[0305h], and so on, is the same as writing to REG[024Dh].The purpose of this “aliased” address range is for Direct host interfaces with “burst” mode which have incrementing addresses. When the host interface is 16-bit and both byte and 16-bit word accesses of the SDRAM Buffer port is desired, an even number of byte accesses are required before a 16-bit word access is possible. Note These registers should not be used when the SPI host interface is selected (see Section Table 5-12 :, “Host Interface Configuration Summary” on page 33). For SDRAM Buffer 0 accesses, use the SDRAM Buffer 0 Data Port at REG[024Ch] ~ REG[024Dh]. Hardware Functional Specification Rev. 1.7 EPSON 215 Chapter 10 Registers S1D13515/S2D13515 REG[0380h] ~ REG[03FEh] (Even Addresses) Aliased SDRAM Buffer 1 Data Port Register 0 Default = 00h Read/Write Aliased SDRAM Buffer 1 Data Port bits 7-0 7 6 5 4 3 2 1 REG[0381h] ~ REG[03FFh] (Odd Addresses) Aliased SDRAM Buffer 1 Data Port Register 1 Default = 00h 0 Read/Write Aliased SDRAM Buffer 1 Data Port bits 15-8 7 REG[0380h] bits 7-0 through REG[03FFh] bits 7-0 6 5 4 3 2 1 0 Aliased SDRAM Buffer 1 Data Port bits [15:0] These are the “aliased” registers of the SDRAM Buffer 1 Data Port REG[025Ch] ~ REG[025Dh]. Writing to REG[0380h], REG[0382h], REG0384h], REG[0386h], and so on, is the same as writing to REG[025Ch]. Writing to REG[0381h], REG[0383h], REG0384h], REG[0385h], and so on, is the same as writing to REG[025Dh].The purpose of this “aliased” address range is for Direct host interfaces with “burst” mode which have incrementing addresses. When the host interface is 16-bit and both byte and 16-bit word accesses of the SDRAM Buffer port is desired, an even number of byte accesses are required before a 16-bit word access is possible. Note These registers should not be used when the SPI host interface is selected (see Table 512: Host Interface Configuration Summary). For SDRAM Buffer 1 accesses, use the SDRAM Buffer 1 Data Port at REG[025Ch] ~ REG[025Dh]. 216 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.10 Warp Logic Configuration Registers For a detailed discussion on the Display Subsystem, including the Warp Module, see Section Chapter 13, “Display Subsystem” on page 443. REG[0400h] Warp Logic Configuration Register Default = 00h Read/Write Warp Logic Software Reset (WO) Warp Logic Frame Double-Buffering Control Source Luminance Bilinear Enable Warp Logic Bilinear Enable Warp Logic Input/Output Pixel Data Format Reserved Luminance Effect Enable Warp Logic Effect Enable 7 6 5 4 3 2 1 0 bit 7 Warp Logic Software Reset (Write Only) This bit performs a software reset of the Warp logic. Writing a 0b to this bit has no effect. Writing a 1b to this bit initiates a software reset of the Warp logic. bit 6 Warp Logic Frame Double-Buffering Control Source This bit determines how frame double-buffering is controlled for the Warp Logic. When this bit = 0b, frame double-buffering is manually controlled through software (see REG[0408h] and REG[040Ah]). When this bit = 1b, frame double-buffering is controlled is through hardware and is selectable using REG[09DCh] bits 6-4. bit 5 Luminance Bilinear Enable This bit determines whether bilinear blending is used when the Luminance effect is enabled, REG[0400h] bit 1 = 1b. When this bit = 0b, the Luminance effect is non-bilinear. When this bit = 1b, the Luminance effect uses bilinear blending of adjacent pixels. bit 4 Warp Logic Bilinear Enable This bit determines whether bilinear blending is used when the Warp Logic effect is enabled, REG[0400h] bit 0= 1b. When this bit = 0b, the Warp Logic effect is non-bilinear. When this bit = 1b, the Warp Logic effect uses bilinear blending of adjacent pixels. bit 3 Warp Logic Input/Output Pixel Data Format This bit selects the RGB data pixel format of image data input to and output from the Warp Logic. When this bit = 0b, the data pixel format is 16 bpp (RGB 5:6:5). When this bit = 1b, the data pixel format is 8 bpp (RGB 3:3:2). bit 2 Reserved This bit must be set to 0b. bit 1 Luminance Effect Enable When the Warp Logic Effect is enabled (REG[0400h] bit 0 = 1b), this bit controls the Luminance effect. When this bit = 0b, the Luminance effect is disabled. When this bit = 1b, the Luminance effect is enabled. Hardware Functional Specification Rev. 1.7 EPSON 217 Chapter 10 Registers S1D13515/S2D13515 bit 0 Warp Logic Effect Enable This bit controls the Warp Logic effect. For details on the Warp Logic, see Section 13.2.3, “Warp Engine” on page 460. When this bit = 0b, the Warp Logic effect is disabled. When this bit = 1b, the Warp Logic effect is enabled. REG[0402h] Warp Logic Event Flag Register Default = 00h n/a 7 bit 5 6 Read Only Read Luminance Table End Event Flag Read Offset Table End Event Flag Reserved Warp Logic Frame End Event Flag 5 4 3 2 n/a 1 0 Read Luminance Table End Event Flag (Read Only) This bit indicates whether the end of the Warp Logic Luminance Table (see REG[0454h] ~ REG[0457h]) has been read. This flag is masked by the Read Luminance Table End Event Enable bit, REG[0404h] bit 5. When this bit = 0b, the end of the Luminance table has not been read yet. When this bit = 1b, the end of the Luminance table has been read. To clear this flag, write a 1b to REG[0406h] bit 5. bit 4 Read Offset Table End Event Flag (Read Only) This bit indicates whether the end of the Warp Logic Offset Table (see REG[0444h] ~ REG[0447h]) has been read. This flag is masked by the Read Offset Table End Event Enable bit, REG[0404h] bit 4. When this bit = 0b, the end of the Luminance table has not been read yet. When this bit = 1b, the end of the Luminance table has been read. To clear this flag, write a 1b to REG[0406h] bit 4. bit 3 Reserved The default value of this bit is 0b. bit 2 Warp Logic Frame End Event Flag (Read Only) This bit indicates whether the Warp Logic has processed the frame (not when the frame is completely written). This flag is masked by the Warp Logic Frame End Event Enable bit, REG[0404h] bit 2. When this bit = 0b, the end of the Warp Logic frame has not occurred. When this bit = 1b, the end of the Warp Logic frame has occurred. To clear this flag, write a 1b to REG[0406h] bit 2. 218 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0404h] Warp Logic Event Enable Register Default = 00h n/a 7 Read/Write Read Luminance Table End Event Enable Read Offset Table End Event Enable Reserved Warp Logic Frame End Event Enable 5 4 3 2 6 n/a 1 0 bit 5 Read Luminance Table End Event Enable This bit controls the Read Luminance Table End Event. The status of the event is indicated by the Read Luminance Table End Event Flag, REG[0402h] bit 5. When this bit = 0b, the Read Luminance Table End Event is disabled. When this bit = 1b, the Read Luminance Table End Event is enabled. bit 4 Read Offset Table End Event Enable This bit controls the Read Offset Table End Event. The status of the event is indicated by the Read Offset Table End Event Flag, REG[0402h] bit 4. When this bit = 0b, the Read Offset Table End Event is disabled. When this bit = 1b, the Read Offset Table End Event is enabled. bit 3 Reserved The default value of this bit is 0b. bit 2 Warp Logic Frame End Event Enable This bit controls the Warp Logic Frame End Event. The status of the event is indicated by the Warp Logic Frame End Event Flag, REG[0402h] bit 2. When this bit = 0b, the Warp Logic Frame End Event is disabled. When this bit = 1b, the Warp Logic Frame End Event is enabled. Hardware Functional Specification Rev. 1.7 EPSON 219 Chapter 10 Registers S1D13515/S2D13515 REG[0406h] Warp Logic Event Clear Register Default = 00h n/a 7 6 Write Only Read Luminance Table End Event Clear Read Offset Table End Event Clear Reserved Warp Logic Frame End Event Clear 5 4 3 2 n/a 1 0 bit 5 Read Luminance Table End Event Clear (Write Only) This bit clears the Read Luminance Table End Event Flag, REG[0402h] bit 5. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the Read Luminance Table End Event Flag. bit 4 Read Offset Table End Event Clear (Write Only) This bit clears the Read Offset Table End Event Flag, REG[0402h] bit 4. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the Read Offset Table End Event Flag. bit 3 Reserved The default value of this bit is 0b. bit 2 Warp Logic Frame End Event Clear (Write Only) This bit clears the Warp Logic Frame End Event Flag, REG[0402h] bit 2. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the Warp Logic Frame End Event Flag. REG[0408h] Warp Logic Frame Status Register Default = 00h Read Only n/a 7 6 5 4 Warp Logic Busy Warp Logic Current Frame Buffer Warp Logic Frame Buffer 1 Ready Status Warp Logic Frame Buffer 0 Ready Status 3 2 1 0 bit 3 Warp Logic Busy (Read Only) This bit indicates whether the Warp Logic is busy processing a frame. When this bit = 0b, the Warp Logic is idle (not busy). When this bit = 1b, the Warp Logic is busy processing a frame. bit 2 Warp Logic Current Frame Buffer (Read Only) This bit indicates which frame buffer (0 or 1) that the Warp Logic is currently reading from (or processing). When this bit = 0b, the current buffer is Warp Logic Frame Buffer 0. When this bit = 1b, the current buffer is Warp Logic Frame Buffer 1. bit 1 Warp Logic Frame Buffer 1 Ready Status (Read Only) This bit indicates the ready status of Warp Logic Frame Buffer 1. The frame buffer is ready when it contains valid frame image data. When this bit = 0b, Warp Logic Frame Buffer 1 is not ready. When this bit = 1b, Warp Logic Frame Buffer 1 is ready. 220 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 0 Warp Logic Frame Buffer 0 Ready Status (Read Only) This bit indicates the ready status of Warp Logic Frame Buffer 0. The frame buffer is ready when it contains valid frame image data. When this bit = 0b, Warp Logic Frame Buffer 0 is not ready. When this bit = 1b, Warp Logic Frame Buffer 0 is ready. REG[040Ah] Warp Logic Frame Ready Set Register Default = 00h Write Only n/a 7 6 5 4 3 2 Set Warp Logic Frame Buffer 1 Ready Set Warp Logic Frame Buffer 0 Ready 1 0 bit 1 Set Warp Logic Frame Buffer 1 Ready (Write Only) This bit only has an effect when Warp Logic double-buffering is configured for software control, REG[0400h] bit 6 = 0b. Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the Warp Logic Frame Buffer 1 input image data is ready for reading by the Warp Logic. Once this bit is set to 1b, it remains at 1b until it is reset by the Warp Logic hardware. bit 0 Set Warp Logic Frame Buffer 0 Ready (Write Only) This bit only has an effect when Warp Logic double-buffering is configured for software control, REG[0400h] bit 6 = 0b. Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the Warp Logic Frame Buffer 0 input image data is ready for reading by the Warp Logic. Once this bit is set to 1b, it remains at 1b until it is reset by the Warp Logic hardware. Hardware Functional Specification Rev. 1.7 EPSON 221 Chapter 10 Registers S1D13515/S2D13515 REG[0410h] Warp Logic Input Width Register 0 Default = 00h Read/Write Warp Logic Input Width bits 7-0 7 6 5 4 3 2 1 REG[0411h] Warp Logic Input Width Register 1 Default = 00h 0 Read/Write Warp Logic Input Width bits 15-8 7 6 REG[0411h] bits 7-0 REG[0410h] bits 7-0 5 4 3 2 1 0 Warp Logic Input Width bits [15:0] These bits specify the width of the image data input to the Warp Logic, in pixels. REG[0412h] Warp Logic Input Height Register 0 Default = 00h Read/Write Warp Logic Image Height bits 7-0 7 6 5 4 3 2 1 REG[0413h] Warp Logic Input Height Register 1 Default = 00h 0 Read/Write Warp Logic Input Height bits 15-8 7 REG[0413h] bits 7-0 REG[0412h] bits 7-0 222 6 5 4 3 2 1 0 Warp Logic Input Height bits [15:0] These bits specify the height of the image data input to the Warp Logic, in pixels. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0414h] Warp Logic Output Width Register 0 Default = 00h Read/Write Warp Logic Output Width bits 7-0 (bit 0 is read only = 0b) 7 6 5 4 3 2 1 REG[0415h] Warp Logic Output Width Register 1 Default = 00h Read/Write n/a 7 6 REG[0415h] bits 2-0 REG[0414h] bits 7-0 5 0 Warp Logic Output Width bits 10-8 4 3 2 1 0 Warp Logic Output Width bits [10:0] These bits specify the width of the image data output by the Warp Logic, in pixels. REG[0414h] bit 0 is read only and always returns 0b (writes to this bit have no effect). Note These bits must be set such that the Warp Logic output width is a multiple of the offset horizontal block size (see REG[0440h] bits 2-0) and luminance horizontal block size (see REG[0450h] bits 2-0). REG[0416h] Warp Logic Output Height Register 0 Default = 00h Read/Write Warp Logic Output Height bits 7-0 (bit 0 is read only = 0b) 7 6 5 4 3 2 1 REG[0417h] Warp Logic Output Height Register 1 Default = 00h Read/Write n/a 7 REG[0417h] bits 2-0 REG[0416h] bits 7-0 6 5 0 Warp Logic Output Height bits 10-8 4 3 2 1 0 Warp Logic Output Height bits [10:0] These bits specify the height of the image data output by the Warp Logic, in pixels. REG[0416h] bit 0 is read only and always returns 0b (writes to this bit have no effect). Note These bits must be set such that the Warp Logic output height is a multiple of the offset vertical block size (see REG[0440h] bits 6-4) and luminance horizontal block size (see REG[0450h] bits 6-4). Hardware Functional Specification Rev. 1.7 EPSON 223 Chapter 10 Registers S1D13515/S2D13515 REG[0420h] Warp Logic Frame Buffer 0 Start Address Register 0 Default = 00h Read/Write Warp Logic Frame Buffer 0 Start Address bits 7-0 (bits 2-0 are read only = 000b) 7 6 5 4 3 2 1 REG[0421h] Warp Logic Frame Buffer 0 Start Address Register 1 Default = 00h 0 Read/Write Warp Logic Frame Buffer 0 Start Address bits 15-8 7 6 5 4 3 2 1 REG[0422h] Warp Logic Frame Buffer 0 Start Address Register 2 Default = 00h 0 Read/Write Warp Logic Frame Buffer 0 Start Address bits 23-16 7 6 5 4 3 2 1 REG[0423h] Warp Logic Frame Buffer 0 Start Address Register 3 Default = 00h 0 Read/Write Warp Logic Frame Buffer 0 Start Address bits 31-24 7 REG[0423h] bits 7-0 REG[0422h] bits 7-0 REG[0421h] bits 7-0 REG[0420h] bits 7-0 224 6 5 4 3 2 1 0 Warp Logic Frame Buffer 0 Start Address bits [31:0] These bits specify the memory start address for Warp Logic Frame Buffer 0 which is used for input image data to the Warp Logic. These bits must be set such that the start address is 8 byte (64-bit) aligned. REG[0420h] bits 2-0 are read only and always return 000b (writes to these bits have no effect). EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0424h] Warp Logic Frame Buffer 1 Start Address Register 0 Default = 00h Read/Write Warp Logic Frame Buffer 1 Start Address bits 7-0 (bits 2-0 are read only = 000b) 7 6 5 4 3 2 1 REG[0425h] Warp Logic Frame Buffer 1 Start Address Register 1 Default = 00h 0 Read/Write Warp Logic Frame Buffer 1 Start Address bits 15-8 7 6 5 4 3 2 1 REG[0426h] Warp Logic Frame Buffer 1 Start Address Register 2 Default = 00h 0 Read/Write Warp Logic Frame Buffer 1 Start Address bits 23-16 7 6 5 4 3 2 1 REG[0427h] Warp Logic Frame Buffer 1 Start Address Register 3 Default = 00h 0 Read/Write Warp Logic Frame Buffer 1 Start Address bits 31-24 7 6 REG[0427h] bits 7-0 REG[0426h] bits 7-0 REG[0425h] bits 7-0 REG[0424h] bits 7-0 5 4 3 2 1 0 Warp Logic Frame Buffer 1 Start Address bits [31:0] These bits specify the memory start address for Warp Logic Frame Buffer 1 which is used for input image data to the Warp Logic. These bits must be set such that the start address is 8 byte (64-bit) aligned. REG[0424h] bits 2-0 are read only and always return 000b (writes to these bits have no effect). REG[0430h] Warp Logic Background Color Blue Register Default = 00h Read/Write Warp Logic Background Color Blue bits 7-0 (bits 2-0 RO) 7 bits 7-0 6 5 4 3 2 1 0 Warp Logic Background Color Blue bits [7:0] These bits specify the blue component of the Warp Logic background color. Bits 2-0 of this register are read only and always return 000b. The background color registers (REG[0430h] ~ REG[0432h) specify the background color as RGB 8:8:8, but only the most significant bits of each color byte are actually used. If the Warp Logic Input/Output Data Pixel Format is RGB 5:6:5 (REG[0400h] bit 3 = 0b). REG[0432h] bits 7-3 = RED REG[0431h] bits 7-2 = GREEN REG[0430h] bits 7-3 = BLUE If the Warp Logic Input/Output Data Pixel Format is RGB 3:3:2 (REG[0400h] bit 3 = 1b). REG[0432h] bits 7-5 = RED REG[0431h] bits 7-5 = GREEN REG[0430h] bits 7-6 = BLUE Hardware Functional Specification Rev. 1.7 EPSON 225 Chapter 10 Registers S1D13515/S2D13515 REG[0431h] Warp Logic Background Color Green Register Default = 00h Read/Write Warp Logic Background Color Green bits 7-0 (bits 1-0 RO) 7 6 bits 7-0 5 4 3 2 1 0 Warp Logic Background Color Green bits [7:0] These bits specify the green component of the Warp Logic background color. Bits 1-0 of this register are read only and always return 00b. The background color registers (REG[0430h] ~ REG[0432h) specify the background color as RGB 8:8:8, but only the most significant bits of each color byte are actually used. If the Warp Logic Input/Output Data Pixel Format is RGB 5:6:5 (REG[0400h] bit 3 = 0b). REG[0432h] bits 7-3 = RED REG[0431h] bits 7-2 = GREEN REG[0430h] bits 7-3 = BLUE If the Warp Logic Input/Output Data Pixel Format is RGB 3:3:2 (REG[0400h] bit 3 = 1b). REG[0432h] bits 7-5 = RED REG[0431h] bits 7-5 = GREEN REG[0430h] bits 7-6 = BLUE REG[0432h] Warp Logic Background Color Red Register Default = 00h Read/Write Warp Logic Background Color Red bits 7-0 (bits 2-0 RO) 7 bits 7-0 6 5 4 3 2 1 0 Warp Logic Background Color Red bits [7:0] These bits specify the red component of the Warp Logic background color. Bits 2-0 of this register are read only and always return 000b. The background color registers (REG[0430h] ~ REG[0432h]) specify the background color as RGB 8:8:8, but only the most significant bits of each color byte are actually used. If the Warp Logic Input/Output Data Pixel Format is RGB 5:6:5 (REG[0400h] bit 3 = 0b). REG[0432h] bits 7-3 = RED REG[0431h] bits 7-2 = GREEN REG[0430h] bits 7-3 = BLUE If the Warp Logic Input/Output Data Pixel Format is RGB 3:3:2 (REG[0400h] bit 3 = 1b). REG[0432h] bits 7-5 = RED REG[0431h] bits 7-5 = GREEN REG[0430h] bits 7-6 = BLUE 226 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0434h] Warp Logic Input X Offset Register 0 Default = 00h Read/Write Warp Logic Input X Offset bits 7-0 7 6 5 4 3 2 1 REG[0435h] Warp Logic Input X Offset Register 1 Default = 00h 0 Read/Write Warp Logic Input X Offset bits 15-8 7 6 REG[0435h] bits 7-0 REG[0434h] bits 7-0 5 4 3 2 1 0 Warp Logic Input X Offset bits [15:0] These bits specify the Warp Logic Input X Offset, in pixels. When the Warp Logic output size is smaller than the input size, the input X,Y offset values (see also REG[0436h] ~ REG[0437h]) specify the top left corner of the output window which can “pan” the larger input image. The input X offset value is specified relative to the top left corner of the input image. The X offset supports both positive and negative values using 2’s complement. REG[0436h] Warp Logic Input Y Offset Register 0 Default = 00h Read/Write Warp Logic Input Y Offset bits 7-0 7 6 5 4 3 2 1 REG[0437h] Warp Logic Input Y Offset Register 1 Default = 00h 0 Read/Write Warp Logic Input Y Offset bits 15-8 7 REG[0437h] bits 7-0 REG[0436h] bits 7-0 6 5 4 3 2 1 0 Warp Logic Input Y Offset bits [15:0] These bits specify the Warp Logic Input Y Offset, in pixels. When the Warp Logic output size is smaller than the input size, the input X,Y offset values (see also REG[0434h] ~ REG[0435h]) specify the top left corner of the output window which can “pan” the larger input image. The input Y offset value is specified relative to the top left corner of the input image. The Y offset supports both positive and negative values using 2’s complement. Hardware Functional Specification Rev. 1.7 EPSON 227 Chapter 10 Registers S1D13515/S2D13515 REG[0440h] Warp Logic Offset Table Configuration Register Default = 33h n/a 7 bits 6-4 Offset Vertical Block Power bits 2-0 6 5 Read/Write n/a 4 Offset Horizontal Block Power bits 2-0 3 2 1 0 Offset Vertical Block Power bits [2:0] The Warp Logic divides the output image into NxM pixel blocks. These bits specify the vertical size (M) of the pixel block. Table 10-28: Offset Vertical Block Power Selection bits 2-0 REG[0440h] bits 6-4 Vertical Block Power 000b Reserved 001b Reserved 010b 4 (22) 011b (default) 8 (23) 100b 16 (24) 101b 32 (25) 110b 64 (26) 111b Reserved Offset Horizontal Block Power bits [2:0] The Warp Logic divides the output image into NxM pixel blocks. These bits specify the horizontal size (N) of the pixel block. Table 10-29: Offset Horizontal Block Power Selection 228 REG[0440h] bits 2-0 Horizontal Block Power 000b Reserved 001b Reserved 010b 4 (22) 011b (default) 8 (23) 100b 16 (24) 101b 32 (25) 110b 64 (26) 111b Reserved EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0444h] Warp Logic Offset Table SDRAM Start Address Register 0 Default = 00h Read/Write Warp Logic Offset Table SDRAM Start Address bits 7-0 (bits 2-0 are read only = 000b) 7 6 5 4 3 2 1 0 REG[0445h] Warp Logic Offset Table SDRAM Start Address Register 1 Default = 00h Read/Write Warp Logic Offset Table SDRAM Start Address bits 15-8 7 6 5 4 3 2 1 0 REG[0446h] Warp Logic Offset Table SDRAM Start Address Register 2 Default = 00h Read/Write Warp Logic Offset Table SDRAM Start Address bits 23-16 7 6 5 4 3 2 1 0 REG[0447h] Warp Logic Offset Table SDRAM Start Address Register 3 Default = 00h Read/Write Warp Logic Offset Table SDRAM Start Address bits 31-24 7 6 REG[0447h] bits 7-0 REG[0446h] bits 7-0 REG[0445h] bits 7-0 REG[0444h] bits 7-0 5 4 3 2 1 0 Warp Logic Offset Table SDRAM Start Address bits [31:0] These bits specify the location in SDRAM of the Warp Logic Offset Table. These bits must be set such that the start address is 8 byte (64-bit) aligned. REG[0444h] bits 2-0 are read only and always return 000b (writes to these bits have no effect). Additionally, the Warp Logic Offset Table layout also requires 8 byte alignment for each row. The byte arrangement for each row must be set as described below. Table 10-30: Warp Logic Offset Table Layout Warp Table = each value is 16-bit (2’s complement) X(0,0) Y(0,0) X(1,0) Y(1,0) X(2,0) Y(2,0) ••• X(outputwidth÷N,0) Y(outputwidth÷N,0) See Note X(0,1) Y(0,1) X(1,1) Y(1,1) X(2,1) Y(2,1) ••• X(outputwidth÷N,1) Y(outputwidth÷N,1) See Note • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • X(0,outputheight÷M) Y(0,outputheight÷M ••• ••• ••• ••• ••• X(outputwidth÷N, outputheight÷M) Y(outputwidth÷N, outputheight÷M See Note N is the horizontal size of the pixel block as specified by REG[0440h] bits 2-0 M is the vertical size of the pixel block as specified by REG[0440h] bits 6-4 Note Each row must be padded if it does not end on an 8 byte boundary. Hardware Functional Specification Rev. 1.7 EPSON 229 Chapter 10 Registers S1D13515/S2D13515 REG[0450h] Warp Logic Luminance Table Configuration Register 0 Default = 33h n/a 7 bits 6-4 Luminance Vertical Block Power bits 2-0 6 5 n/a 4 Read/Write Luminance Horizontal Block Power bits 2-0 3 2 1 0 Luminance Vertical Block Power bits [2:0] The Luminance function divides the output image into NxM pixel blocks. These bits specify the vertical size (M) of the pixel block. Table 10-31: Luminance Vertical Block Power bits 2-0 REG[0450h] bits 6-4 Vertical Block Power 000b Reserved 001b Reserved 010b 4 (22) 011b (default) 8 (23) 100b 16 (24) 101b 32 (25) 110b 64 (26) 111b Reserved Luminance Horizontal Block Power bits [2:0] The Luminance function divides the output image into NxM pixel blocks. These bits specify the horizontal size (N) of the pixel block. Table 10-32: Luminance Horizontal Block Power 230 REG[0450h] bits 2-0 Horizontal Block Power 000b Reserved 001b Reserved 010b 4 (22) 011b (default) 8 (23) 100b 16 (24) 101b 32 (25) 110b 64 (26) 111b Reserved EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0452h] Warp Logic Luminance Table Configuration Register 1 Default = 01h Read/Write n/a 7 6 5 4 3 2 Warp Logic Background Color Luminance Disable Warp Logic Black Color Luminance Disable 1 0 bit 1 Warp Logic Background Color Luminance Disable When the Luminance effect is enabled (REG[0400h] bit 1 = 1b), this bit determines whether the luminance effect is applied to the background color (REG[0430h] ~ REG[0432h]). When this bit = 0b, the luminance effect is applied to the background color. When this bit = 1b, the luminance effect is not applied to background color. bit 0 Warp Logic Black Color Luminance Disable When the Luminance effect is enabled (REG[0400h] bit 1 = 1b), this bit determines whether the luminance effect is applied to black pixels. When this bit = 0b, the luminance effect is applied to black pixels. When this bit = 1b, the luminance effect is not applied to black pixels. Hardware Functional Specification Rev. 1.7 EPSON 231 Chapter 10 Registers S1D13515/S2D13515 REG[0454h] Warp Logic Luminance Table SDRAM Start Address Register 0 Default = 00h Read/Write Warp Logic Luminance Table SDRAM Start Address bits 7-0 (bits 2-0 are read only = 000b) 7 6 5 4 3 2 1 REG[0455h] Warp Logic Luminance Table SDRAM Start Address Register 1 Default = 00h 0 Read/Write Warp Logic Luminance Table SDRAM Start Address bits 15-8 7 6 5 4 3 2 1 REG[0456h] Warp Logic Luminance Table SDRAM Start Address Register 2 Default = 00h 0 Read/Write Warp Logic Luminance Table SDRAM Start Address bits 23-16 7 6 5 4 3 2 1 REG[0457h] Warp Logic Luminance Table SDRAM Start Address Register 3 Default = 00h 0 Read/Write Warp Logic Luminance Table SDRAM Start Address bits 31-24 7 6 REG[0457h] bits 7-0 REG[0456h] bits 7-0 REG[0455h] bits 7-0 REG[0454h] bits 7-0 5 4 3 2 1 0 Warp Logic Luminance Table SDRAM Start Address bits [31:0] These bits specify the location in SDRAM of the Warp Logic Luminance Table. These bits must be set such that the start address is 8 byte (64-bit) aligned. REG[0454h] bits 2-0 are read only and always return 000b (writes to these bits have no effect). Additionally, the Luminance Table layout also requires 8 byte alignment for each row. The byte arrangement for each row must be set as described below. Table 10-33: Luminance Table Layout Luminance Table = each value is 8-bit (2’s complement) Luminance(0,0) Luminance(1,0) Luminance(2,0) Luminance(3,0) ••• Luminance (outputwidth÷N,0) See Note Luminance(0,1) Luminance(1,1) Luminance(2,1) Luminance(3,1) ••• Luminance (outputwidth÷N,1) See Note • • • • • • • • • • • • • • • • • • • • • Luminance ••• ••• ••• ••• Luminance (outputwidth÷N, outputheight÷M) See Note (0,outputheight÷M) N is the horizontal size of the pixel block as specified by REG[0450h] bits 2-0 M is the vertical size of the pixel block as specified by REG[0450h] bits 6-4 Note Each row must be padded if it does not end on an 8 byte boundary. 232 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.11 Blending Engine Configuration Registers For a detailed discussion on the Display Subsystem, including the Blending Engine, see Section Chapter 13, “Display Subsystem” on page 443. REG[0900h] CH1OUT Control Register Default = 00h CH1OUT Writeback Pixel Format bits 1-0 n/a 7 bits 5-4 Read/Write 6 5 4 CH1OUT Vertical Flip Enable CH1OUT Writeback Memory Mode CH1OUT Mode CH1OUT Enable 3 2 1 0 CH1OUT Writeback Pixel Format bits [1:0] When CH1OUT writeback mode is selected (REG[0900h] bit 1 = 1b), these bits specify the RGB pixel format for the image data written to the SDRAM. Table 10-34: CH1OUT Writeback Pixel Format Select REG[0900h] bits 5-4 CH1OUT Writeback Pixel Format 00b RGB 3:3:2 01b RGB 5:6:5 10b RGB 8:8:8 11b Reserved bit 3 CH1OUT Vertical Flip Enable This bit determines whether the image data output on CH1OUT is flipped around the X axis (vertical). This bit must set to 0b for tiled frame mode, REG[0900h] bit 2 = 1b. When this bit = 0b, CH1OUT image data is not vertically flipped (disabled). When this bit = 1b, CH1OUT image data is vertically flipped (enabled). bit 2 CH1OUT Writeback Memory Mode When CH1OUT writeback mode is selected (REG[0900h] bit 1 = 1b), this bit determines how the image data is stored in memory. For details on the memory organization methods, see Section 13.3, “Memory Organization of Frames” on page 465. When this bit = 0b, CH1OUT writeback uses “line-by-line” mode to write to SDRAM. When this bit = 1b, CH1OUT writeback uses “tiled frame” mode to write to SDRAM. Note For tiled frame mode, the image width must be a multiple of 8 pixels and CH1OUT Vertical Flip must be disabled, REG[0900h] bit 3 = 0b. bit 1 CH1OUT Mode This bit selects the CH1OUT mode which determines whether the image data output on CH1OUT goes to the LCD interface, or is written back to the SDRAM. For further details on CH1OUT Writeback mode, see Section 13.2.4, “CH1OUT Writeback” on page 462. When this bit = 0b, CH1OUT image data goes to LCD interface. When this bit = 1b, CH1OUT image data is written back to SDRAM. Hardware Functional Specification Rev. 1.7 EPSON 233 Chapter 10 Registers S1D13515/S2D13515 bit 0 CH1OUT Enable This bit controls the blending engine output CH1OUT. For an overview of the Blending Engine, see Section 13.1, “Block Diagram” on page 443. When this bit = 0b, CH1OUT is disabled. When this bit = 1b, CH1OUT is enabled. Note If hardware frame control is selected for the MAIN window (REG[09D8h] bit 0 = 1b), it must be disabled before CH1OUT can be disabled. The following sequence is recommended. 1. Disable hardware frame control, REG[09D8h] bit 0 = 0b. 2. Wait 1 frame. 3. Disable CH1OUT, REG[0900h] bit 0 = 0b. REG[0904h] CH1OUT Writeback Frame Buffer 0 Address Register 0 Default = 00h Read/Write CH1OUT Writeback Frame Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[0905h] CH1OUT Writeback Frame Buffer 0 Address Register 1 Default = 00h 0 Read/Write CH1OUT Writeback Frame Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[0906h] CH1OUT Writeback Frame Buffer 0 Address Register 2 Default = 00h 0 Read/Write CH1OUT Writeback Frame Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[0907h] CH1OUT Writeback Frame Buffer 0 Address Register 3 Default = 10h 0 Read/Write CH1OUT Writeback Frame Buffer 0 Address bits 31-24 7 REG[0907h] bits 7-0 REG[0906h] bits 7-0 REG[0905h] bits 7-0 REG[0904h] bits 7-0 234 6 5 4 3 2 1 0 CH1OUT Writeback Frame Buffer 0 Address bits [31:0] These bits specify the start address in SDRAM of CH1OUT Writeback Frame Buffer 0. These bits must be set such that the start address is 8 byte (64-bit) aligned. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0908h] CH1OUT Writeback Frame Buffer 1 Address Register 0 Default = 00h Read/Write CH1OUT Writeback Frame Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[0909h] CH1OUT Writeback Frame Buffer 1 Address Register 1 Default = 00h 0 Read/Write CH1OUT Writeback Frame Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[090Ah] CH1OUT Writeback Frame Buffer 1 Address Register 2 Default = 00h 0 Read/Write CH1OUT Writeback Frame Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[090Bh] CH1OUT Writeback Frame Buffer 1 Address Register 3 Default = 10h 0 Read/Write CH1OUT Writeback Frame Buffer 1 Address bits 31-24 7 6 REG[090Bh] bits 7-0 REG[090Ah] bits 7-0 REG[0909h] bits 7-0 REG[0908h] bits 7-0 5 4 3 2 1 0 CH1OUT Writeback Frame Buffer 1 Address bits [31:0] These bits specify the start address in SDRAM of CH1OUT Writeback Frame Buffer 1. These bits must be set such that the start address is 8 byte (64-bit) aligned. REG[090Ch] Scratchpad Register 0 Default = 40h Read/Write Scratchpad Register bits 7-0 7 6 5 4 3 2 1 REG[090Dh] Scratchpad Register 1 Default = 00h 0 Read/Write Scratchpad Register bits 15-8 7 6 5 4 3 2 1 REG[090Eh] Scratchpad Register 2 Default = 00h 0 Read/Write Scratchpad Register bits 23-16 7 6 5 4 3 2 1 REG[090Fh] Scratchpad Register 3 Default = 00h 0 Read/Write Scratchpad Register bits 31-24 7 REG[090Fh] bits 7-0 REG[090Eh] bits 7-0 REG[090Dh] bits 7-0 REG[090Ch] bits 7-0 6 5 4 3 2 1 0 Scratchpad Register bits [31:0] These bits have no hardware effect and are available for scratchpad use. Hardware Functional Specification Rev. 1.7 EPSON 235 Chapter 10 Registers S1D13515/S2D13515 REG[0920h] CH2OUT Control Register Default = 00h Read/Write n/a 7 6 bit 0 5 CH2OUT Enable 4 3 2 1 0 CH2OUT Enable This bit controls the blending engine output CH2OUT. For an overview of the Blending Engine, see Section 13.1, “Block Diagram” on page 443. When this bit = 0b, CH2OUT is disabled. When this bit = 1b, CH2OUT is enabled. Note If hardware frame control is selected for the AUX window (REG[09D9h] bit 0 = 1b) or the OSD window (REG[09DAh] bit 0 = 1b) and either window is the source for CH2, hardware frame control for the windows must be disabled before CH2OUT can be disabled. The following sequence is recommended. 1. Disable hardware frame control, REG[09D9h] and/or REG[09DAh] bit 0 = 0b. 2. Wait 1 frame. 3. Disable CH2OUT, REG[0920h] bit 0 = 0b. REG[0930h] OSDOUT Control Register Default = 00h Read/Write n/a 7 bit 0 6 5 OSDOUT Enable 4 3 2 1 0 OSDOUT Enable This bit controls the blending engine output OSDOUT. For an overview of the Blending Engine, see Section 13.1, “Block Diagram” on page 443. When this bit = 0b, OSDOUT is disabled. When this bit = 1b, OSDOUT is enabled. Note If hardware frame control is selected for the OSD window (REG[09DAh] bit 0 = 1b), it must be disabled before OSDOUT can be disabled. The following sequence is recommended. 1. Disable hardware frame control, REG[09DAh] bit 0 = 0b. 2. Wait 1 frame. 3. Disable OSDOUT, REG[0930h] bit 0 = 0b. 236 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0940h] MAIN Window Control Register Default = 00h Read/Write MAIN Window Line Double Enable MAIN Horizontal Flip Enable MAIN Vertical Flip Enable n/a 7 6 5 4 MAIN Window Pixel Format bits 1-0 3 2 MAIN Window Fetch Mode MAIN Window Blank 1 0 bit 7 MAIN Window Line Double Enable This bit controls “line double” mode which is typically used for displaying interlaced images from the camera interface. When line doubling is enabled, each line of the input image stored in the SDRAM is read twice. When this bit = 0b, MAIN window line doubling is disabled. When this bit = 1b, MAIN window line doubling is enabled. bit 6 MAIN Horizontal Flip Enable This bit determines whether the image data input from the MAIN window is flipped around the Y axis (horizontal). This bit must be set to 0b when the MAIN window fetch uses “tiled-frame” mode, REG[0940h] bit 1 = 1b. When this bit = 0b, the MAIN image data is not horizontally flipped (disabled). When this bit = 1b, the MAIN image data is horizontally flipped (enabled). Note If the AUX and/or OSD window overlays the MAIN window (REG[09A0h] bits 1-0 = 00b or 01b) when MAIN Horizontal Flip is enabled, the relative position of the overlaid window(s) is flipped. However, the image in the AUX and/or OSD window is NOT flipped and is still controlled by the individual flip enable bits (see REG[0960h] bits 6-5 for AUX, REG[0980h] bits 6-5 for OSD). bit 5 MAIN Vertical Flip Enable This bit determines whether the image data input from the MAIN window is flipped around the X axis (vertical). This bit must be set to 0b when the MAIN window fetch uses “tiled-frame” mode, REG[0940h] bit 1 = 1b. When this bit = 0b, the MAIN image data is not vertically flipped (disabled). When this bit = 1b, the MAIN image data is vertically flipped (enabled). Note If the AUX and/or OSD window overlays the MAIN window (REG[09A0h] bits 1-0 = 00b or 01b) when MAIN Vertical Flip is enabled, the relative position of the overlaid window(s) is flipped. However, the image in the AUX and/or OSD window is NOT flipped and is still controlled by the individual flip enable bits (see REG[0960h] bits 6-5 for AUX, REG[0980h] bits 6-5 for OSD). Hardware Functional Specification Rev. 1.7 EPSON 237 Chapter 10 Registers S1D13515/S2D13515 bits 3-2 MAIN Window Pixel Format bits [1:0] These bits determine the RGB pixel format of the MAIN window image data that is input to the Blending Engine. Table 10-35: MAIN Window Pixel Format Selection REG[0940h] bits 3-2 bit 1 Pixel Format 00b 8 bpp (RGB 3:3:2) 01b 16 bpp (RGB 5:6:5) 10b 24 bpp (RGB 8:8:8) 11b Reserved MAIN Window Fetch Mode This bit specifies how the MAIN window image data is stored in memory. For details on the memory organization methods, see Section 13.3, “Memory Organization of Frames” on page 465. When this bit = 0b, MAIN window fetch uses “line-by-line” mode to read from SDRAM. When this bit = 1b, MAIN window fetch uses “tiled-frame” mode to read from SDRAM. Note For tiled frame mode, the image width and virtual width must be a multiple of 8 pixels and the MAIN window image data must not be flipped (REG[0940h] bit 6 = 0b and bit 5 = 0b). bit 0 MAIN Window Blank This bit controls the MAIN window blank function. The blank function replaces the image data input to the Blending Engine from the MAIN window with the color specified by the MAIN Blank Color registers, REG[0944h] ~ REG[0946h]. When this bit = 0b, the MAIN window image data is read normally (not blanked). When this bit = 1b, the MAIN window image data is “blanked” with the specified color. REG[0942h] MAIN Window Frame Control/Status Register Default = 00h n/a 7 6 MAIN Frame Buffer 1 Ready Clear (WO) MAIN Frame Buffer 0 Ready Clear (WO) 5 4 Read/Write n/a Main Window Current Frame Status (RO) MAIN Frame Buffer 1 Ready MAIN Frame Buffer 0 Ready 3 2 1 0 bit 5 MAIN Frame Buffer 1 Ready Clear (Write Only) This bit is used to manually clear the MAIN Frame Buffer 1 Ready bit, REG[0942h] bit 1. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the MAIN Frame Buffer 1 Ready bit. bit 4 MAIN Frame Buffer 0 Ready Clear (Write Only) This bit is used to manually clear the MAIN Frame Buffer 0 Ready bit, REG[0942h] bit 0. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the MAIN Frame Buffer 0 Ready bit. 238 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 bit 2 Chapter 10 Registers Main Window Current Frame Status (Read Only) This bit indicates which MAIN frame buffer is currently being read by the Blending Engine. When this bit = 0b, MAIN Frame Buffer 0 is being read by the Blending Engine. When this bit = 1b, MAIN Frame Buffer 1 is being read by the Blending Engine. Note When the MAIN window is disabled and then re-enabled using the CH1OUT Enable bit (REG[0900h] bit 0), the hardware always sets the Current Frame status to 0b and checks the MAIN Frame Buffer 0 Ready bit first. Therefore before re-enabling the MAIN window, the MAIN window image stream must be reset to start with Buffer 0, the MAIN Frame Buffer 0/1 Ready bits must be cleared (see REG[0942h] bits 5-4), and the MAIN Frame Buffer 0 Ready bit must be set to 1b (REG[0942h] bit 0 = 1b). bit 1 MAIN Frame Buffer 1 Ready This bit only has an effect when MAIN window double-buffering is configured for software control, REG[09D8h] bit 0 = 0b. For Writes: Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the MAIN Frame Buffer 1 image data is ready for reading by the Blending Engine. Once this bit is set to 1b, it remains at 1b until it is reset by the Blending Engine. For Reads: When this bit = 0b, MAIN Frame Buffer 1 does not contain valid image data. When this bit = 1b, MAIN Frame Buffer 1 contains valid image data. bit 0 MAIN Frame Buffer 0 Ready This bit only has an effect when MAIN window double-buffering is configured for software control, REG[09D8h] bit 0 = 0b. For Writes: Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the MAIN Frame Buffer 0 image data is ready for reading by the Blending Engine. Once this bit is set to 1b, it remains at 1b until it is reset by the Blending Engine. For Reads: When this bit = 0b, MAIN Frame Buffer 0 does not contain valid image data. When this bit = 1b, MAIN Frame Buffer 0 contains valid image data. Hardware Functional Specification Rev. 1.7 EPSON 239 Chapter 10 Registers S1D13515/S2D13515 REG[0944h] MAIN Blank Color Blue Register Default = 00h Read/Write MAIN Blank Color Blue bits 7-0 7 6 5 4 3 2 1 REG[0945h] MAIN Blank Color Green Register Default = 00h 0 Read/Write MAIN Blank Color Green bits 7-0 7 6 5 4 3 2 1 REG[0946h] MAIN Blank Color Red Register Default = 00h 0 Read/Write MAIN Blank Color Red bits 7-0 7 REG[0946h] bits 7-0 REG[0945h] bits 7-0 REG[0944h] bits 7-0 6 5 4 3 2 1 0 MAIN Blank Color Red bits [7:0] MAIN Blank Color Green bits [7:0] MAIN Blank Color Blue bits [7:0] When the MAIN Window Blank bit is set (REG[0940h] bit 0 = 1b), these bits specify the RGB components of the color that the Blending Engine replaces MAIN window image data with. If the MAIN Window Pixel Format is RGB 8:8:8 (REG[940h] bits 3-2 = 10b). REG[0946h] bits 7-0 = RED REG[0945h] bits 7-0 = GREEN REG[0944h] bits 7-0 = BLUE If the MAIN Window Pixel Format is RGB 5:6:5 (REG[0940h] bits 3-2 = 01b). REG[0946h] bits 7-3 = RED REG[0945h] bits 7-2 = GREEN REG[0944h] bits 7-3 = BLUE If the MAIN Window Pixel Format is RGB 3:3:2 (REG[0940h] bits 3-2 = 00b). REG[0946h] bits 7-5 = RED REG[0945h] bits 7-5 = GREEN REG[0944h] bits 7-6 = BLUE 240 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0948h] MAIN Window Frame Buffer 0 Address Register 0 Default = 00h Read/Write MAIN Window Frame Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[0949h] MAIN Window Frame Buffer 0 Address Register 1 Default = 00h 0 Read/Write MAIN Window Frame Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[094Ah] MAIN Window Frame Buffer 0 Address Register 2 Default = 00h 0 Read/Write MAIN Window Frame Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[094Bh] MAIN Window Frame Buffer 0 Address Register 3 Default = 10h 0 Read/Write MAIN Window Frame Buffer 0 Address bits 31-24 7 REG[094Bh] bits 7-0 REG[094Ah] bits 7-0 REG[0949h] bits 7-0 REG[0948h] bits 7-0 6 5 4 3 2 1 0 MAIN Window Frame Buffer 0 Address bits [31:0] These bits specify the memory start address for MAIN Window Frame Buffer 0 which is used for input image data to the Blending Engine. These bits must be set such that the start address is 8 byte (64-bit) aligned. Hardware Functional Specification Rev. 1.7 EPSON 241 Chapter 10 Registers S1D13515/S2D13515 REG[094Ch] MAIN Window Frame Buffer 1 Address Register 0 Default = 00h Read/Write MAIN Window Frame Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[094Dh] MAIN Window Frame Buffer 1 Address Register 1 Default = 00h 0 Read/Write MAIN Window Frame Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[094Eh] MAIN Window Frame Buffer 1 Address Register 2 Default = 00h 0 Read/Write MAIN Window Frame Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[094Fh] MAIN Window Frame Buffer 1 Address Register 3 Default = 10h 0 Read/Write MAIN Window Frame Buffer 1 Address bits 31-24 7 REG[094Fh] bits 7-0 REG[094Eh] bits 7-0 REG[094Dh] bits 7-0 REG[094Ch] bits 7-0 242 6 5 4 3 2 1 0 MAIN Window Frame Buffer 1 Address bits [31:0] These bits specify the memory start address for MAIN Window Frame Buffer 1which is used for input image data to the Blending Engine. These bits must be set such that the start address is 8 byte (64-bit) aligned. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0950h] MAIN Window Width Register 0 Default = 40h Read/Write MAIN Window Width bits 7-0 7 6 5 4 3 2 1 REG[0951h] MAIN Window Width Register 1 Default = 01h Read/Write n/a 7 6 REG[0951h] bits 2-0 REG[0950h] bits 7-0 0 MAIN Window Width bits 10-8 5 4 3 2 1 0 MAIN Window Width bits [10:0] These bits specify the width of the MAIN window, in pixels. Note For tiled frame mode, the image width must be a multiple of 8 pixels. REG[0952h] MAIN Window Height Register 0 Default = F0h Read/Write MAIN Window Height bits 7-0 7 6 5 4 3 2 1 REG[0953h] MAIN Window Height Register 1 Default = 00h Read/Write n/a 7 REG[0953h] bits 2-0 REG[0952h] bits 7-0 6 5 0 MAIN Window Height bits 10-8 4 3 2 1 0 MAIN Window Height bits [10:0] These bits specify the height of the MAIN window, in pixels. Hardware Functional Specification Rev. 1.7 EPSON 243 Chapter 10 Registers S1D13515/S2D13515 REG[0954h] MAIN Window Virtual Width Register 0 Default = 40h Read/Write MAIN Window Virtual Width bits 7-0 7 6 5 4 3 2 1 REG[0955h] MAIN Window Virtual Width Register 1 Default = 01h Read/Write n/a 7 MAIN Window Virtual Width bits 12-8 6 REG[0955h] bits 4-0 REG[0954h] bits 7-0 0 5 4 3 2 1 0 MAIN Window Virtual Width bits [12:0] These bits specify the width of the MAIN window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. Note 1. The Main window virtual width must be set such that the virtual width multiplied by the pixel format (in bpp, see REG[0940h] bits 3-2) is divisible by 64. 2. For tiled frame mode, the image virtual width must be a multiple of 8 pixels. REG[095Ah] MAIN Input X Offset Register 0 Default = 00h Read/Write MAIN Input X Offset bits 7-0 7 6 5 4 3 2 1 REG[095Bh] MAIN Input X Offset Register 1 Default = 00h Read/Write n/a 7 REG[095Bh] bits 4-0 REG[095Ah] bits 7-0 244 6 0 MAIN Input X Offset bits 12-8 5 4 3 2 1 0 MAIN Input X Offset bits [12:0] These bits specify the X offset of the top left corner of the MAIN window relative to the top left corner of the MAIN window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[095Ch] MAIN Input Y Offset Register 0 Default = 00h Read/Write MAIN Input Y Offset bits 7-0 7 6 5 4 3 2 1 REG[095Dh] MAIN Input Y Offset Register 1 Default = 00h Read/Write n/a 7 MAIN Input Y Offset bits 12-8 6 REG[095Dh] bits 4-0 REG[095Ch] bits 7-0 0 5 4 3 2 1 0 MAIN Input Y Offset bits [12:0] These bits specify the Y offset of the top left corner of the MAIN window relative to the top left corner of the MAIN window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. REG[0960h] AUX Window Control Register Default = 00h Read/Write AUX Window Line Double Enable AUX Horizontal Flip Enable AUX Vertical Flip Enable AUX Enable 7 6 5 4 AUX Window Pixel Format bits 1-0 3 2 AUX Window Fetch Mode AUX Window Blank 1 0 bit 7 AUX Window Line Double Enable This bit controls “line double” mode which is typically used for displaying interlaced images from the camera interface. When line doubling is enabled, each line of the input image stored in the SDRAM is read twice. When this bit = 0b, AUX window line doubling is disabled. When this bit = 1b, AUX window line doubling is enabled. bit 6 AUX Horizontal Flip Enable This bit determines whether the image data input from the AUX window is flipped around the Y axis (horizontal). This bit must be set to 0b when the AUX window fetch uses “tiledframe” mode, REG[0960h] bit 1 = 1b. When this bit = 0b, the AUX image data is not horizontally flipped (disabled). When this bit = 1b, the AUX image data is horizontally flipped (enabled). Note If the OSD overlays the AUX window (REG[09A0h] bits 1-0 = 10b) when AUX Horizontal Flip is enabled, the relative position of the OSD window is flipped. However, the image in the OSD window is NOT flipped and is still controlled by the OSD flip enable bits, REG[0980h] bits 6-5. Hardware Functional Specification Rev. 1.7 EPSON 245 Chapter 10 Registers bit 5 S1D13515/S2D13515 AUX Vertical Flip Enable This bit determines whether the image data input from the AUX window is flipped around the X axis (vertical). This bit must be set to 0b when the AUX window fetch uses “tiledframe” mode, REG[0960h] bit 1 = 1b. When this bit = 0b, the AUX image data is not vertically flipped (disabled). When this bit = 1b, the AUX image data is vertically flipped (enabled). Note If the OSD overlays the AUX window (REG[09A0h] bits 1-0 = 10b) when AUX Vertical Flip is enabled, the relative position of the OSD window is flipped. However, the image in the OSD window is NOT flipped and is still controlled by the OSD flip enable bits, REG[0980h] bits 6-5. bit 4 AUX Enable This bit only has an effect when Blend Mode 0 is selected, REG[09A0h] bits 1-0 = 00b. This bit controls whether the AUX window is displayed (enabled) or not (disabled). When this bit = 0b, the AUX window is disabled. When this bit = 1b, the AUX window is enabled. Note If hardware frame control is selected for the AUX window (REG[09D9h] bit 0 = 1b), it must be disabled before the AUX window can be disabled. The following sequence is recommended. 1. Disable hardware frame control, REG[09D9h] bit 0 = 0b. 2. Wait 1 frame. 3. Disable the AUX window, REG[0960h] bit 4 = 0b. bits 3-2 AUX Window Pixel Format bits [1:0] These bits determine the RGB pixel format of the AUX window image data that is input to the Blending Engine. Table 10-36: AUX Window Pixel Format Selection bit 1 REG[0960h] bits 3-2 Pixel Format 00b 8 bpp (RGB 3:3:2) 01b 16 bpp (RGB 5:6:5) 10b 24 bpp (RGB 8:8:8) 11b Reserved AUX Window Fetch Mode This bit specifies how the AUX window image data is stored in memory. For details on the memory organization methods, see Section 13.3, “Memory Organization of Frames” on page 465. When this bit = 0b, AUX window fetch uses “line-by-line” mode to read from SDRAM. When this bit = 1b, AUX window fetch uses “tiled-frame” mode to read from SDRAM. Note For tiled frame mode, the image width and virtual width must be a multiple of 8 pixels and the AUX window image data must not be flipped (REG[0960h] bit 6 = 0b and bit 5 = 0b). 246 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 0 AUX Window Blank This bit controls the AUX window blank function. The blank function replaces the image data input to the Blending Engine from the AUX window with the color specified by the AUX Blank Color registers, REG[0964h] ~ REG[0966h]. When this bit = 0b, the AUX window image data is read normally (not blanked). When this bit = 1b, the AUX window image data is “blanked” with the specified color. REG[0962h] AUX Window Frame Control/Status Register Default = 00h n/a 7 Read/Write AUX Frame Buffer 1 Ready Clear (WO) AUX Frame Buffer 0 Ready Clear (WO) n/a AUX Window Current Frame Status (RO) AUX Frame Buffer 1 Ready AUX Frame Buffer 0 Ready 5 4 3 2 1 0 6 bit 5 AUX Frame Buffer 1 Ready Clear (Write Only) This bit is used to manually clear the AUX Frame Buffer 1 Ready bit, REG[0962h] bit 1. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the AUX Frame Buffer 1 Ready bit. bit 4 AUX Frame Buffer 0 Ready Clear (Write Only) This bit is used to manually clear the AUX Frame Buffer 0 Ready bit, REG[0962h] bit 0. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the AUX Frame Buffer 0 Ready bit. bit 2 AUX Window Current Frame Status (Read Only) This bit indicates which AUX frame buffer is currently being read by the Blending Engine. When this bit = 0b, AUX Frame Buffer 0 is being read by the Blending Engine. When this bit = 1b, AUX Frame Buffer 1 is being read by the Blending Engine. Note When the AUX window is disabled and then re-enabled using the AUX Enable bit (REG[0960h] bit 4), the hardware always sets the Current Frame status to 0b and checks the AUX Frame Buffer 0 Ready bit first. Therefore before re-enabling the AUX window, the AUX window image stream must be reset to start with Buffer 0, the AUX Frame Buffer 0/1 Ready bits must be cleared (see REG[0962h] bits 5-4), and the AUX Frame Buffer 0 Ready bit must be set to 1b (REG[0962h] bit 0 = 1b). bit 1 AUX Frame Buffer 1 Ready This bit only has an effect when AUX window double-buffering is configured for software control, REG[09D9h] bit 0 = 0b. For Writes: Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the AUX Frame Buffer 1 image data is ready for reading by the Blending Engine. Once this bit is set to 1b, it remains at 1b until it is reset by the Blending Engine. For Reads: When this bit = 0b, AUX Frame Buffer 1 does not contain valid image data. When this bit = 1b, AUX Frame Buffer 1 contains valid image data. Hardware Functional Specification Rev. 1.7 EPSON 247 Chapter 10 Registers S1D13515/S2D13515 bit 0 AUX Frame Buffer 0 Ready This bit only has an effect when AUX window double-buffering is configured for software control, REG[09D9h] bit 0 = 0b. For Writes: Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the AUX Frame Buffer 0 image data is ready for reading by the Blending Engine. Once this bit is set to 1b, it remains at 1b until it is reset by the Blending Engine. For Reads: When this bit = 0b, AUX Frame Buffer 0 does not contain valid image data. When this bit = 1b, AUX Frame Buffer 0 contains valid image data. REG[0964h] AUX Blank Color Blue Register Default = 00h Read/Write AUX Blank Color Blue bits 7-0 7 6 5 4 3 2 1 REG[0965h] AUX Blank Color Green Register Default = 00h 0 Read/Write AUX Blank Color Green bits 7-0 7 6 5 4 3 2 1 REG[0966h] AUX Blank Color Red Register Default = 00h 0 Read/Write AUX Blank Color Red bits 7-0 7 REG[0966h] bits 7-0 REG[0965h] bits 7-0 REG[0964h] bits 7-0 6 5 4 3 2 1 0 AUX Blank Color Red bits [7:0] AUX Blank Color Green bits [7:0] AUX Blank Color Blue bits [7:0] When the AUX Window Blank bit is set (REG[0960h] bit 0 = 1b), these bits specify the RGB components of the color that the Blending Engine replaces AUX window image data with. If the AUX Window Pixel Format is RGB 8:8:8 (REG[960h] bits 3-2 = 10b). REG[0966h] bits 7-0 = RED REG[0965h] bits 7-0 = GREEN REG[0964h] bits 7-0 = BLUE If the AUX Window Pixel Format is RGB 5:6:5 (REG[0960h] bits 3-2 = 01b). REG[0966h] bits 7-3 = RED REG[0965h] bits 7-2 = GREEN REG[0964h] bits 7-3 = BLUE If the AUX Window Pixel Format is RGB 3:3:2 (REG[0960h] bits 3-2 = 00b). REG[0966h] bits 7-5 = RED REG[0965h] bits 7-5 = GREEN REG[0964h] bits 7-6 = BLUE 248 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0968h] AUX Window Frame Buffer 0 Address Register 0 Default = 00h Read/Write AUX Window Frame Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[0969h] AUX Window Frame Buffer 0 Address Register 1 Default = 00h 0 Read/Write AUX Window Frame Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[096Ah] AUX Window Frame Buffer 0 Address Register 2 Default = 00h 0 Read/Write AUX Window Frame Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[096Bh] AUX Window Frame Buffer 0 Address Register 3 Default = 10h 0 Read/Write AUX Window Frame Buffer 0 Address bits 31-24 7 REG[096Bh] bits 7-0 REG[096Ah] bits 7-0 REG[0969h] bits 7-0 REG[0968h] bits 7-0 6 5 4 3 2 1 0 AUX Window Frame Buffer 0 Address bits [31:0] These bits specify the memory start address for AUX Window Frame Buffer 0 which is used for input image data to the Blending Engine. These bits must be set such that the start address is 8 byte (64-bit) aligned. Hardware Functional Specification Rev. 1.7 EPSON 249 Chapter 10 Registers S1D13515/S2D13515 REG[096Ch] AUX Window Frame Buffer 1 Address Register 0 Default = 00h Read/Write AUX Window Frame Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[096Dh] AUX Window Frame Buffer 1 Address Register 1 Default = 00h 0 Read/Write AUX Window Frame Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[096Eh] AUX Window Frame Buffer 1 Address Register 2 Default = 00h 0 Read/Write AUX Window Frame Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[096Fh] AUX Window Frame Buffer 1 Address Register 3 Default = 10h 0 Read/Write AUX Window Frame Buffer 1 Address bits 31-24 7 REG[096Fh] bits 7-0 REG[096Eh] bits 7-0 REG[096Dh] bits 7-0 REG[096Ch] bits 7-0 250 6 5 4 3 2 1 0 AUX Window Frame Buffer 1 Address bits [31:0] These bits specify the memory start address for AUX Window Frame Buffer 1 which is used for input image data to the Blending Engine. These bits must be set such that the start address is 8 byte (64-bit) aligned. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0970h] AUX Window Width Register 0 Default = 40h Read/Write AUX Window Width bits 7-0 7 6 5 4 3 2 1 REG[0971h] AUX Window Width Register 1 Default = 01h Read/Write n/a 7 6 REG[0971h] bits 2-0 REG[0970h] bits 7-0 0 AUX Window Width bits 10-8 5 4 3 2 1 0 AUX Window Width bits [10:0] These bits specify the width of the AUX window, in pixels. Note For tiled frame mode, the image width must be a multiple of 8 pixels. REG[0972h] AUX Window Height Register 0 Default = F0h Read/Write AUX Window Height bits 7-0 7 6 5 4 3 2 1 REG[0973h] AUX Window Height Register 1 Default = 00h Read/Write n/a 7 REG[0973h] bits 2-0 REG[0972h] bits 7-0 6 5 0 AUX Window Height bits 10-8 4 3 2 1 0 AUX Window Height bits [10:0] These bits specify the height of the AUX window, in pixels. Hardware Functional Specification Rev. 1.7 EPSON 251 Chapter 10 Registers S1D13515/S2D13515 REG[0974h] AUX Window Virtual Width Register 0 Default = 40h Read/Write AUX Window Virtual Width bits 7-0 7 6 5 4 3 2 1 REG[0975h] AUX Window Virtual Width Register 1 Default = 01h Read/Write n/a 7 AUX Window Virtual Width bits 12-8 6 REG[0975h] bits 4-0 REG[0974h] bits 7-0 0 5 4 3 2 1 0 AUX Window Virtual Width bits [12:0] These bits specify the width of the AUX window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. Note 1. The AUX window virtual width must be set such that the virtual width multiplied by the pixel format (in bpp, see REG[0960h] bits 3-2) is divisible by 64. 2. For tiled frame mode, the image virtual width must be a multiple of 8 pixels. REG[0976h] AUX Window X Offset Register 0 Default = 00h Read/Write AUX Window X Offset bits 7-0 7 6 5 4 3 2 1 REG[0977h] AUX Window X Offset Register 1 Default = 00h Read/Write n/a 7 REG[0977h] bits 2-0 REG[0976h] bits 7-0 252 6 5 0 AUX Window X Offset bits 10-8 4 3 2 1 0 AUX Window X Offset bits [10:0] These bits only have an effect when Blend Mode 0 is selected, REG[09A0h] bits 1-0 = 00b. These bits specify the X offset of the top left corner of the AUX window relative to the top left corner of the LCD display, in pixels. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0978h] AUX Window Y Offset Register 0 Default = 00h Read/Write AUX Window Y Offset bits 7-0 7 6 5 4 3 2 1 REG[0979h] AUX Window Y Offset Register 1 Default = 00h Read/Write n/a 7 6 REG[0979h] bits 2-0 REG[0978h] bits 7-0 5 0 AUX Window Y Offset bits 10-8 4 3 2 1 0 AUX Window Y Offset bits [10:0] These bits only have an effect when Blend Mode 0 is selected, REG[09A0h] bits 1-0 = 00b. These bits specify the Y offset of the top left corner of the AUX window relative to the top left corner of the LCD display, in pixels. REG[097Ah] AUX Input X Offset Register 0 Default = 00h Read/Write AUX Input X Offset bits 7-0 7 6 5 4 3 2 1 REG[097Bh] AUX Input X Offset Register 1 Default = 00h Read/Write n/a 7 AUX Input X Offset bits 12-8 6 REG[097Bh] bits 4-0 REG[097Ah] bits 7-0 0 5 4 3 2 1 0 AUX Input X Offset bits [12:0] These bits specify the X offset of the top left corner of the AUX window relative to the top left corner of the AUX window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. REG[097Ch] AUX Input Y Offset Register 0 Default = 00h Read/Write AUX Input Y Offset bits 7-0 7 6 5 4 3 2 1 REG[097Dh] AUX Input Y Offset Register 1 Default = 00h Read/Write n/a 7 REG[097Dh] bits 4-0 REG[097Ch] bits 7-0 0 AUX Input Y Offset bits 12-8 6 5 4 3 2 1 0 AUX Input Y Offset bits [12:0] These bits specify the Y offset of the top left corner of the AUX window relative to the top left corner of the AUX window virtual image, in pixels, For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. Hardware Functional Specification Rev. 1.7 EPSON 253 Chapter 10 Registers S1D13515/S2D13515 REG[0980h] OSD Window Control Register Default = 00h Read/Write OSD Window Line Double Enable OSD Horizontal Flip Enable OSD Vertical Flip Enable OSD Enable 7 6 5 4 OSD Window Pixel Format bits 1-0 3 2 OSD Window Fetch Mode OSD Window Blank 1 0 bit 7 OSD Window Line Double Enable This bit controls “line double” mode which is typically used for displaying interlaced images from the camera interface. When line doubling is enabled, each line of the input image stored in the SDRAM is read twice. When this bit = 0b, OSD window line doubling is disabled. When this bit = 1b, OSD window line doubling is enabled. bit 6 OSD Horizontal Flip Enable This bit determines whether the image data input from the OSD window is flipped around the Y axis (horizontal). This bit must be set to 0b when the OSD window fetch uses “tiledframe” mode, REG[0980h] bit 1 = 1b. When this bit = 0b, the OSD image data is not horizontally flipped (disabled). When this bit = 1b, the OSD image data is horizontally flipped (enabled). bit 5 OSD Vertical Flip Enable This bit determines whether the image data input from the OSD window is flipped around the X axis (vertical). This bit must be set to 0b when the OSD window fetch uses “tiledframe” mode, REG[0980h] bit 1 = 1b. When this bit = 0b, the OSD image data is not vertically flipped (disabled). When this bit = 1b, the OSD image data is vertically flipped (enabled). bit 4 OSD Enable This bit only has an effect when Blend Mode 0, 1, or 2 is selected, REG[09A0h] bits 1-0 = 00b or 01b or 10b. This bit controls whether the OSD window is displayed (enabled) or not (disabled). When this bit = 0b, the OSD window is disabled. When this bit = 1b, the OSD window is enabled. Note If hardware frame control is selected for the OSD window (REG[09DAh] bit 0 = 1b), it must be disabled before the OSD window can be disabled. The following sequence is recommended. 1. Disable hardware frame control, REG[09DAh] bit 0 = 0b. 2. Wait 1 frame. 3. Disable the OSD window, REG[0980h] bit 4 = 0b. 254 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 bits 3-2 Chapter 10 Registers OSD Window Pixel Format bits [1:0] These bits determine the RGB or ARGB pixel format of the OSD window image data that is input to the Blending Engine. Table 10-37: OSD Window Pixel Format Selection REG[09A0h] bit 3 (Alpha Format) 0b 1b REG[0980h] bits 3-2 Pixel Format 00b 8 bpp (RGB 3:3:2) 01b 16 bpp (RGB 5:6:5) 10b 24 bpp (RGB 8:8:8) 11b Reserved 00b 16 bpp (ARGB 4:4:4:4) 01b 16 bpp (ARGB 1:5:5:5) 10b 24 bpp (ARGB 8:5:6:5) 11b Reserved Note When Blend Mode 3 is selected (REG[09A0h] bits 1-0 = 11b), ARGB pixel formats are not supported for the OSD window. bit 1 OSD Window Fetch Mode This bit specifies how the OSD window image data is stored in memory. For details on the memory organization methods, see Section 13.3, “Memory Organization of Frames” on page 465. When this bit = 0b, OSD window fetch uses “line-by-line” mode to read from SDRAM. When this bit = 1b, OSD window fetch uses “tiled-frame” mode to read from SDRAM. Note For tiled frame mode, the image width and virtual width must be a multiple of 8 pixels and the OSD window image data must not be flipped (REG[0980h] bit 6 = 0b and bit 5 = 0b). bit 0 OSD Window Blank This bit controls the OSD window blank function. The blank function replaces the image data input to the Blending Engine from the OSD window with the color specified by the OSD Blank Color registers, REG[0984h] ~ REG[0986h]. When this bit = 0b, the OSD window image data is read normally (not blanked). When this bit = 1b, the OSD window image data is “blanked” with the specified color. Note If the OSD window is blanked while OSD Alpha Format is enabled (REG[09A0h] bit 3 = 1b), the RGB blank color is specified by the OSD Blank Color registers (REG[0984h] ~ REG[0986h]) and the alpha ratio is specified by the OSD Alpha Blend Ratio register (REG[09A1h]). Hardware Functional Specification Rev. 1.7 EPSON 255 Chapter 10 Registers S1D13515/S2D13515 REG[0982h] OSD Window Frame Control/Status Register Default = 00h n/a 7 6 Read/Write OSD Frame Buffer 1 Ready Clear (WO) OSD Frame Buffer 0 Ready Clear (WO) n/a OSD Window Current Frame Status (RO) OSD Frame Buffer 1 Ready OSD Frame Buffer 0 Ready 5 4 3 2 1 0 bit 5 OSD Frame Buffer 1 Ready Clear (Write Only) This bit is used to manually clear the OSD Frame Buffer 1 Ready bit, REG[0982h] bit 1. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the OSD Frame Buffer 1 Ready bit. bit 4 OSD Frame Buffer 0 Ready Clear (Write Only) This bit is used to manually clear the OSD Frame Buffer 0 Ready bit, REG[0982h] bit 0. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the OSD Frame Buffer 0 Ready bit. bit 2 OSD Window Current Frame Status (Read Only) This bit indicates which OSD frame buffer is currently being read by the Blending Engine. When this bit = 0b, OSD Frame Buffer 0 is being read by the Blending Engine. When this bit = 1b, OSD Frame Buffer 1 is being read by the Blending Engine. Note When the OSD window is disabled and then re-enabled using the OSD Enable bit (REG[0980h] bit 4), the hardware always sets the Current Frame status to 0b and checks the OSD Frame Buffer 0 Ready bit first. Therefore before re-enabling the OSD window, the OSD window image stream must be reset to start with Buffer 0, the OSD Frame Buffer 0/1 Ready bits must be cleared (see REG[0982h] bits 5-4), and the OSD Frame Buffer 0 Ready bit must be set to 1b (REG[0982h] bit 0 = 1b). 256 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 1 OSD Frame Buffer 1 Ready This bit only has an effect when OSD window double-buffering is configured for software control, REG[09DAh] bit 0 = 0b. For Writes: Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the OSD Frame Buffer 1 image data is ready for reading by the Blending Engine. Once this bit is set to 1b, it remains at 1b until it is reset by the Blending Engine. For Reads: When this bit = 0b, OSD Frame Buffer 1 does not contain valid image data. When this bit = 1b, OSD Frame Buffer 1 contains valid image data. bit 0 OSD Frame Buffer 0 Ready This bit only has an effect when OSD window double-buffering is configured for software control, REG[09DAh] bit 0 = 0b. For Writes: Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the OSD Frame Buffer 0 image data is ready for reading by the Blending Engine. Once this bit is set to 1b, it remains at 1b until it is reset by the Blending Engine. For Reads: When this bit = 0b, OSD Frame Buffer 0 does not contain valid image data. When this bit = 1b, OSD Frame Buffer 0 contains valid image data. Hardware Functional Specification Rev. 1.7 EPSON 257 Chapter 10 Registers S1D13515/S2D13515 REG[0984h] OSD Blank Color Blue Register Default = 00h Read/Write OSD Blank Color Blue bits 7-0 7 6 5 4 3 2 1 REG[0985h] OSD Blank Color Green Register Default = 00h 0 Read/Write OSD Blank Color Green bits 7-0 7 6 5 4 3 2 1 REG[0986h] OSD Blank Color Red Register Default = 00h 0 Read/Write OSD Blank Color Red bits 7-0 7 REG[0986h] bits 7-0 REG[0985h] bits 7-0 REG[0984h] bits 7-0 6 5 4 3 2 1 0 OSD Blank Color Red bits [7:0] OSD Blank Color Green bits [7:0] OSD Blank Color Blue bits [7:0] When the OSD Window Blank bit is set (REG[0980h] bit 0 = 1b), these bits specify the RGB components of the color that the Blending Engine replaces OSD window image data with. If the OSD Window Pixel Format is RGB 8:8:8 (REG[0980h] bits 3-2 = 10b). REG[0986h] bits 7-0 = RED REG[0985h] bits 7-0 = GREEN REG[0984h] bits 7-0 = BLUE If the OSD Window Pixel Format is RGB 5:6:5 (REG[0980h] bits 3-2 = 01b). REG[0986h] bits 7-3 = RED REG[0985h] bits 7-2 = GREEN REG[0984h] bits 7-3 = BLUE If the OSD Window Pixel Format is RGB 3:3:2 (REG[0980h] bits 3-2 = 00b). REG[0986h] bits 7-5 = RED REG[0985h] bits 7-5 = GREEN REG[0984h] bits 7-6 = BLUE Note If the OSD window is blanked (REG[0980h] bit 0 = 1b) while OSD Alpha Format is enabled (REG[09A0h] bit 3 = 1b), the RGB blank color is specified by the OSD Blank Color registers (REG[0984h] ~ REG[0986h]) and the alpha ratio is specified by the OSD Alpha Blend Ratio register (REG[09A1h]). 258 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0988h] OSD Window Frame Buffer 0 Address Register 0 Default = 00h Read/Write OSD Window Frame Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[0989h] OSD Window Frame Buffer 0 Address Register 1 Default = 00h 0 Read/Write OSD Window Frame Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[098Ah] OSD Window Frame Buffer 0 Address Register 2 Default = 00h 0 Read/Write OSD Window Frame Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[098Bh] OSD Window Frame Buffer 0 Address Register 3 Default = 10h 0 Read/Write OSD Window Frame Buffer 0 Address bits 31-24 7 REG[098Bh] bits 7-0 REG[098Ah] bits 7-0 REG[0989h] bits 7-0 REG[0988h] bits 7-0 6 5 4 3 2 1 0 OSD Window Frame Buffer 0 Address bits [31:0] These bits specify the memory start address for OSD Window Frame Buffer 0 which is used for input image data to the Blending Engine. These bits must be set such that the start address is 8 byte (64-bit) aligned. Hardware Functional Specification Rev. 1.7 EPSON 259 Chapter 10 Registers S1D13515/S2D13515 REG[098Ch] OSD Window Frame Buffer 1 Address Register 0 Default = 00h Read/Write OSD Window Frame Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[098Dh] OSD Window Frame Buffer 1 Address Register 1 Default = 00h 0 Read/Write OSD Window Frame Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[098Eh] OSD Window Frame Buffer 1 Address Register 2 Default = 00h 0 Read/Write OSD Window Frame Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[098Fh] OSD Window Frame Buffer 1 Address Register 3 Default = 10h 0 Read/Write OSD Window Frame Buffer 1 Address bits 31-24 7 6 REG[098Fh] bits 7-0 REG[098Eh] bits 7-0 REG[098Dh] bits 7-0 REG[098Ch] bits 7-0 5 4 3 2 1 0 OSD Window Frame Buffer 1 Address bits [31:0] These bits specify the memory start address for OSD Window Frame Buffer 1 which is used for input image data to the Blending Engine. These bits must be set such that the start address is 8 byte (64-bit) aligned. REG[0990h] OSD Window Width Register 0 Default = 40h Read/Write OSD Window Width bits 7-0 7 6 5 4 3 2 1 REG[0991h] OSD Window Width Register 1 Default = 01h Read/Write n/a 7 REG[0991h] bits 2-0 REG[0990h] bits 7-0 6 5 0 OSD Window Width bits 10-8 4 3 2 1 0 OSD Window Width bits [10:0] These bits specify the width of the OSD window, in pixels. Note For tiled frame mode, the image width must be a multiple of 8 pixels. 260 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0992h] OSD Window Height Register 0 Default = F0h Read/Write OSD Window Height bits 7-0 7 6 5 4 3 2 1 REG[0993h] OSD Window Height Register 1 Default = 00h Read/Write n/a 7 6 REG[0993h] bits 2-0 REG[0992h] bits 7-0 5 0 OSD Window Height bits 10-8 4 3 2 1 0 OSD Window Height bits [10:0] These bits specify the height of the OSD window, in pixels. REG[0994h] OSD Window Virtual Width Register 0 Default = 40h Read/Write OSD Window Virtual Width bits 7-0 7 6 5 4 3 2 1 REG[0995h] OSD Window Virtual Width Register 1 Default = 01h Read/Write n/a 7 REG[0995h] bits 4-0 REG[0994h] bits 7-0 0 OSD Window Virtual Width bits 12-8 6 5 4 3 2 1 0 OSD Window Virtual Width bits [12:0] These bits specify the width of the OSD window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. Note 1. The OSD window virtual width must be set such that the virtual width multiplied by the pixel format (in bpp, see REG[0980h] bits 3-2) is divisible by 64. 2. For tiled frame mode, the image virtual width must be a multiple of 8 pixels. Hardware Functional Specification Rev. 1.7 EPSON 261 Chapter 10 Registers S1D13515/S2D13515 REG[0996h] OSD Window X Offset Register 0 Default = 00h Read/Write OSD Window X Offset bits 7-0 7 6 5 4 3 2 1 REG[0997h] OSD Window X Offset Register 1 Default = 00h Read/Write n/a 7 6 REG[0997h] bits 2-0 REG[0996h] bits 7-0 0 OSD Window X Offset bits 10-8 5 4 3 2 1 0 OSD Window X Offset bits [10:0] These bits only have an effect when Blend Mode 0, 1, or 2 is selected, REG[09A0h] bits 1-0 = 00b or 01b or 10b. These bits specify the X offset of the top left corner of the OSD window relative to the top left corner of the LCD display, in pixels. REG[0998h] OSD Window Y Offset Register 0 Default = 00h Read/Write OSD Window Y Offset bits 7-0 7 6 5 4 3 2 1 REG[0999h] OSD Window Y Offset Register 1 Default = 00h Read/Write n/a 7 6 REG[0999h] bits 2-0 REG[0998h] bits 7-0 5 0 OSD Window Y Offset bits 10-8 4 3 2 1 0 OSD Window Y Offset bits [10:0] These bits only have an effect when Blend Mode 0, 1, or 2 is selected, REG[09A0h] bits 1-0 = 00b or 01b or 10b. These bits specify the Y offset of the top left corner of the OSD window relative to the top left corner of the LCD display, in pixels. REG[099Ah] OSD Input X Offset Register 0 Default = 00h Read/Write OSD Input X Offset bits 7-0 7 6 5 4 3 2 1 REG[099Bh] OSD Input X Offset Register 1 Default = 00h Read/Write n/a 7 REG[099Bh] bits 4-0 REG[099Ah] bits 7-0 262 6 0 OSD Input X Offset bits 12-8 5 4 3 2 1 0 OSD Input X Offset bits [12:0] These bits specify the X offset of the top left corner of the OSD window relative to the top left corner of the OSD window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[099Ch] OSD Input Y Offset Register 0 Default = 00h Read/Write OSD Input Y Offset bits 7-0 7 6 5 4 3 2 1 REG[099Dh] OSD Input Y Offset Register 1 Default = 00h Read/Write n/a 7 OSD Input Y Offset bits 12-8 6 REG[099Dh] bits 4-0 REG[099Ch] bits 7-0 5 4 3 2 1 0 OSD Input Y Offset bits [12:0] These bits specify the Y offset of the top left corner of the OSD window relative to the top left corner of the OSD window virtual image, in pixels, For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. REG[09A0h] Blending Engine Control Register Default = 00h Reserved 7 0 n/a 6 Read/Write ARGB 1:5:5:5 Alpha Ratio Select OSD Alpha Format Enable AUX on Top 4 3 2 5 Blend Mode Select bits 1-0 1 0 bit 7 Reserved This bit must be set to 0b. bit 4 ARGB 1:5:5:5 Alpha Ratio Select When the OSD window is configured for ARGB 1:5:5:5 (REG[09A0h] bit 3 = 1b and REG[0980h] bits 3-2 = 01b), this bit selects the ratio used to alpha-blend the OSD window when the 1-bit alpha value is 1b. When the 1-bit alpha value is 0b, the ratio is 00% (00h). When this bit = 0b, the 8-bit alpha blend ratio for ARGB 1:5:5:5 is 50% (80h). When this bit = 1b, the 8-bit alpha blend ratio for ARGB 1:5:5:5 is 75% (C0h). bit 3 OSD Alpha Format Enable This bit determines the method used for alpha-blending the OSD window. When this bit = 0b, the OSD window pixel format is non-alpha (RGB 3:3:2, RGB 5:6:5, or RGB 8:8:8, see REG[0980h] bits 3-2). In this mode, the OSD window is alpha-blended using a common alpha ratio as specified by the OSD Alpha Blend Ratio register, REG[09A1h]. When this bit = 1b, the OSD window pixel format is alpha (ARGB 4:4:4:4, ARGB 1:5:5:5, or ARGB 8:5:6:5, see REG[0980h] bits 3-2). In this mode, the OSD window is alpha-blended using the alpha ratio for each pixel. Note 1. If the OSD window is blanked (REG[0980h] bit 0 = 1b) while OSD Alpha Format is enabled, the RGB blank color is specified by the OSD Blank Color registers (REG[0984h] ~ REG[0986h]) and the alpha ratio is specified by the OSD Alpha Blend Ratio register (REG[09A1h]). 2. If OSD Alpha Format is enabled and OSD Transparency is enabled (REG[09A7h] bit 7 = 1b), only the RGB components of the pixel value are compared. Hardware Functional Specification Rev. 1.7 EPSON 263 Chapter 10 Registers S1D13515/S2D13515 bit 2 AUX on Top This bit only has an effect when Blend Mode 0 is selected, REG[09A0h] bits 1-0 = 00b. This bit determines whether the AUX or OSD window is on top. When this bit = 0b, the OSD window is on top of the AUX window. When this bit = 1b, the AUX window is on top of the OSD window. Note When the AUX window is on top, the OSD window is alpha-blended with the MAIN window only. bits 1-0 Blend Mode Select bits [1:0] These bits select the Blending Engine mode of operation. For details on each mode, see Section 13.2.2, “Blending Engine” on page 451. Table 10-38: Blend Mode Selection REG[09A0h] bits 1-0 Blend Mode CH1OUT CH2OUT OSDOUT 00b 0 MAIN+AUX+OSD Off Off 01b 1 MAIN+OSD AUX Off 10b 2 MAIN AUX+OSD Off 11b 3 MAIN AUX OSD REG[09A1h] OSD Alpha Blend Ratio Register Default = FFh Read/Write OSD Alpha Blend Ratio bits 7-0 7 bits 7-0 6 5 4 3 2 1 0 OSD Alpha Blend Ratio bits [7:0] When OSD Alpha Format is disabled (REG[09A0h] bit 3 = 0b), the OSD window is alpha-blended using the common alpha ratio specified by these bits. When the Alpha value is FFh, the OSD window is fully displayed. When the Alpha value is 00h, the OSD window is turned off. If the Alpha value changes from zero to non-zero, it turns on the OSD window and care must be taken by software to ensure that the frame double-buffering between the OSD window and its source image stream restarts at Buffer 0 (see note for REG[0982h] bit 2). When the OSD window is blanked (REG[0980h] bit 0 is 1b), these bits specify the alpha blend ratio for all OSD window pixel formats. For RGB 3:3:2, RGB 5:6:5, and RGB 8:8:8, and ARGB 8:5:6:5 formats (see REG[09A0h] bit 3 and REG[0980h] bits 3-2), bits 7-0 of this register are used as the alpha blend ratio. For ARGB 1:5:5:5, bit 7 of this register is used as the 1-bit alpha blend ratio. For ARGB 4:4:4:4, bits 7-4 of this register are used as the 4-bit alpha blend ratio. 264 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09A2h] Camera I2C Data Register Default = 0Xh Read Only n/a 7 6 5 4 3 2 I2C SDA Pin Status I2C SCL Pin Status 1 0 bit 1 I2C SDA Pin Status (Read Only) This bit indicates the input status of the SDA pin used for the I2C interface. When this bit = 0b, the SDA pin is 0 (low). When this bit = 1b, the SDA pin is 1 (high). bit 0 I2C SCL Pin Status (Read Only) This bit indicates the input status of the SCL pin used for the I2C interface. When this bit = 0b, the SCL pin is 0 (low). When this bit = 1b, the SCL pin is 1 (high). REG[09A3h] Camera I2C Output Enable Register Default = 03h Read/Write n/a 7 6 5 4 3 2 I2C SDA Output Enable I2C SCL Output Enable 1 0 bit 1 I2C SDA Output Enable This bit controls SDA pin output for the I2C interface. When this bit = 0b, the I2C SDA pin is enabled and driven low. When this bit = 1b, the I2C SDA pin is disabled, tri-stated (high-impedance), and pulled high. bit 0 I2C SCL Output Enable This bit controls SCL pin output for the I2C interface. When this bit = 0b, the I2C SCL pin is enabled and driven low. When this bit = 1b, the I2C SCL pin is disabled, tri-stated (high-impedance), and pulled high. Hardware Functional Specification Rev. 1.7 EPSON 265 Chapter 10 Registers S1D13515/S2D13515 REG[09A4h] OSD Transparency Color Blue Register Default = 00h Read/Write OSD Transparency Color Blue bits 7-0 7 6 5 4 3 2 1 REG[09A5h] OSD Transparency Color Green Register Default = 00h 0 Read/Write OSD Transparency Color Green bits 7-0 7 6 5 4 3 2 1 REG[09A6h] OSD Transparency Color Red Register Default = 00h 0 Read/Write OSD Transparency Color Red bits 7-0 7 REG[09A6h] bits 7-0 REG[09A5h] bits 7-0 REG[09A4h] bits 7-0 6 5 4 3 2 1 0 OSD Transparency Color Red bits [7:0] OSD Transparency Color Green bits [7:0] OSD Transparency Color Blue bits [7:0] These bits only have an effect when OSD Transparency is enabled, REG[09A7h] bit 7 = 1b. These bits specify the RGB components of the transparency color for the OSD window which are compared with the OSD window pixels to determine whether the OSD window pixel or the “background” pixel is displayed. If the pixel format is RGB 8:8:8 (see REG[09A0h] bit 3 and REG[0980h] bits 3-2). REG[09A6h] bits 7-0 = RED REG[09A5h] bits 7-0 = GREEN REG[09A4h] bits 7-0 = BLUE If the pixel format is RGB 5:6:5 (see REG[09A0h] bit 3 and REG[0980h] bits 3-2). REG[09A6h] bits 7-3 = RED REG[09A5h] bits 7-2 = GREEN REG[09A4h] bits 7-3 = BLUE If the pixel format is RGB 3:3:2 (see REG[09A0h] bit 3 and REG[0980h] bits 3-2). REG[09A6h] bits 7-5 = RED REG[09A5h] bits 7-5 = GREEN REG[09A4h] bits 7-6 = BLUE If the pixel format is ARGB 8:5:6:5 (see REG[09A0h] bit 3 and REG[0980h] bits 3-2). REG[09A6h] bits 7-3 = RED REG[09A5h] bits 7-2 = GREEN REG[09A4h] bits 7-3 = BLUE If the pixel format is ARGB 1:5:5:5 (see REG[09A0h] bit 3 and REG[0980h] bits 3-2). REG[09A6h] bits 7-3 = RED REG[09A5h] bits 7-3 = GREEN REG[09A4h] bits 7-3 = BLUE If the pixel format is ARGB 4:4:4:4 (see REG[09A0h] bit 3 and REG[0980h] bits 3-2). REG[09A6h] bits 7-4 = RED REG[09A5h] bits 7-4 = GREEN REG[09A4h] bits 7-4 = BLUE 266 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers Note If OSD Alpha Format is enabled (REG[09A0h] bit 3 = 1b) and OSD Transparency is enabled (REG[09A7h] bit 7 = 1b, only the RGB components of the pixel value are compared. REG[09A7h] OSD Transparency Enable Register Default = 00h OSD Transparency Enable 7 bit 7 Read/Write n/a 6 5 4 3 2 1 0 OSD Transparency Enable This bit controls the transparency function for the OSD window. The transparency color is specified by the OSD Transparency Color registers, REG[09A4h] ~ REG[09A6h]. When this bit = 0b, OSD transparency is disabled. When this bit = 1b, OSD transparency is enabled. Note If OSD Alpha Format is enabled (REG[09A0h] bit 3 = 1b) and OSD Transparency is enabled, only the RGB components of the pixel value are compared. Hardware Functional Specification Rev. 1.7 EPSON 267 Chapter 10 Registers S1D13515/S2D13515 10.4.12 Image Fetcher Configuration Registers REG[09AAh] Image Fetcher Input X Offset Register 0 Default = 00h Read/Write Image Fetcher Input X Offset bits 7-0 7 6 5 4 3 2 1 REG[09ABh] Image Fetcher Input X Offset Register 1 Default = 00h Read/Write n/a 7 0 Image Fetcher Input X Offset bits 12-8 6 5 4 3 2 1 0 REG[09ABh] bits 4-0 REG[09AAh] bits 7-0 Image Fetcher Input X Offset bits [12:0] These bits specify the X offset of the top left corner of the Image Fetcher window relative to the top left corner of the Image Fetcher window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. REG[09ACh] Image Fetcher Input Y Offset Register 0 Default = 00h Read/Write Image Fetcher Input Y Offset bits 7-0 7 6 5 4 3 2 1 REG[09ADh] Image Fetcher Input Y Offset Register 1 Default = 00h Read/Write n/a 7 0 Image Fetcher Input Y Offset bits 12-8 6 5 4 3 2 1 0 REG[09ADh] bits 4-0 REG[09ACh] bits 7-0 Image Fetcher Input Y Offset bits [12:0] These bits specify the Y offset of the top left corner of the Image Fetcher window relative to the top left corner of the Image Fetcher window virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. REG[09B0h] Image Fetcher Control Register Default = 00h Read/Write Image Fetcher Line Double Enable Image Fetcher Horizontal Flip Image Fetcher Vertical Flip Image Fetcher Enable 7 6 5 4 bit 7 268 n/a 3 2 Image Fetcher Mode Image Fetcher Blank 1 0 Image Fetcher Line Double Enable This bit controls “line double” mode which is typically used for displaying interlaced images from the camera interface. When line doubling is enabled, each line of the input image stored in the SDRAM is read twice. When this bit = 0b, Image Fetcher line doubling is disabled. When this bit = 1b, Image Fetcher line doubling is enabled. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 6 Image Fetcher Horizontal Flip This bit determines whether the image data input from the Image Fetcher is flipped around the Y axis (horizontal). This bit must be set to 0b when the Image Fetcher uses “tiledframe” mode, REG[09B0h] bit 1 = 1b. When this bit = 0b, the Image Fetcher image data is not horizontally flipped (disabled). When this bit = 1b, the Image Fetcher image data is horizontally flipped (enabled). bit 5 Image Fetcher Vertical Flip This bit determines whether the image data input from the Image Fetcher is flipped around the X axis (vertical). This bit must be set to 0b when the Image Fetcher uses “tiled-frame” mode, REG[09B0h] bit 1 = 1b. When this bit = 0b, the Image Fetcher image data is not vertically flipped (disabled). When this bit = 1b, the Image Fetcher image data is vertically flipped (enabled). bit 4 Image Fetcher Enable This bit controls whether the Image Fetcher image data is displayed (enabled) or not (disabled). When this bit = 0b, the Image Fetcher is disabled. When this bit = 1b, the Image Fetcher is enabled. Note If hardware frame control is selected for the Image Fetcher (REG[09DBh] bit 0 = 1b), it must be disabled before the Image Fetcher can be disabled. The following sequence is recommended. 1. Disable hardware frame control, REG[09DBh] bit 0 = 0b. 2. Wait 1 frame. 3. Disable the Image Fetcher, REG[09B0h] bit 4 = 0b. bit 1 Image Fetcher Mode This bit specifies how the Image Fetcher image data is stored in memory. For details on the memory organization methods, see Section 13.3, “Memory Organization of Frames” on page 465. When this bit = 0b, the Image Fetcher uses “line-by-line” mode to read from SDRAM. When this bit = 1b, the Image Fetcher uses “tiled-frame” mode to read from SDRAM. Note For tiled frame mode, the image width must be a multiple of 8 pixels and the Image Fetcher image data must not be flipped (REG[09B0h] bit 6 = 0b and bit 5 = 0b). bit 0 Image Fetcher Blank This bit controls the Image Fetcher blank function. The blank function replaces the image data from the Image Fetcher with the color specified by the Image Fetcher Blank Color registers, REG[09B4h] ~ REG[09B6h]. When this bit = 0b, the Image Fetcher image data is read normally (not blanked). When this bit = 1b, the Image Fetcher image data is “blanked” with the specified color. Hardware Functional Specification Rev. 1.7 EPSON 269 Chapter 10 Registers S1D13515/S2D13515 REG[09B2h] Image Fetcher Frame Control/Status Register Default = 00h n/a 7 6 Read/Write Image Fetcher Frame Buffer 1 Ready Clear (WO) Image Fetcher Frame Buffer 0 Ready Clear (WO) n/a Image Fetcher Current Frame Status (RO) Image Fetcher Frame Buffer 1 Ready Image Fetcher Frame Buffer 0 Ready 5 4 3 2 1 0 bit 5 Image Fetcher Frame Buffer 1 Ready Clear (Write Only) This bit is used to manually clear the Image Fetcher Frame Buffer 1 Ready bit, REG[09B2h] bit 1. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the Image Fetcher Frame Buffer 1 Ready bit. bit 4 Image Fetcher Frame Buffer 0 Ready Clear (Write Only) This bit is used to manually clear the Image Fetcher Frame Buffer 0 Ready bit, REG[09B2h] bit 0. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the Image Fetcher Frame Buffer 0 Ready bit. bit 2 Image Fetcher Current Frame Status (Read Only) This bit indicates which Image Fetcher frame buffer is currently being read. When this bit = 0b, Image Fetcher Frame Buffer 0 is being read. When this bit = 1b, Image Fetcher Frame Buffer 1 is being read. Note When the Image Fetcher is disabled and then re-enabled using the Image Fetcher Enable bit (REG[09B0h] bit 4), the hardware always sets the Current Frame status to 0b and checks the Image Fetcher Frame Buffer 0 Ready bit first. Therefore before re-enabling the Image Fetcher, the Image Fetcher image stream must be reset to start with Buffer 0, the Image Fetcher Frame Buffer 0/1 Ready bits must be cleared (see REG[09B2h] bits 5-4), and the Image Fetcher Frame Buffer 0 Ready bit must be set to 1b (REG[09B2h] bit 0 = 1b). bit 1 270 Image Fetcher Frame Buffer 1 Ready This bit only has an effect when Image Fetcher double-buffering is configured for software control, REG[09DBh] bit 0 = 0b. For Writes: Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the Image Frame Buffer 1 image data is ready for reading. Once this bit is set to 1b, it remains at 1b until it is reset by the Image Fetcher when it switches reading from frame buffer 1 to frame buffer 0. For Reads: When this bit = 0b, Image Fetcher Frame Buffer 1 does not contain valid image data. When this bit = 1b, Image Fetcher Frame Buffer 1 contains valid image data. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 0 Image Fetcher Frame Buffer 0 Ready This bit only has an effect when Image Fetcher double-buffering is configured for software control, REG[09DBh] bit 0 = 0b. For Writes: Writing a 0b to this bit has no effect. Writing a 1b to this bit sets this bit to 1b and indicates that the Image Frame Buffer 0 image data is ready for reading. Once this bit is set to 1b, it remains at 1b until it is reset by the Image Fetcher when it switches reading from frame buffer 0 to frame buffer 1. For Reads: When this bit = 0b, Image Fetcher Frame Buffer 0 does not contain valid image data. When this bit = 1b, Image Fetcher Frame Buffer 0 contains valid image data. REG[09B4h] Image Fetcher Blank Color Blue Register Default = 00h Read/Write Image Fetcher Blank Color Blue bits 7-0 7 6 5 4 3 2 1 REG[09B5h] Image Fetcher Blank Color Green Register Default = 00h 0 Read/Write Image Fetcher Blank Color Green bits 7-0 7 6 5 4 3 2 1 REG[09B6h] Image Fetcher Blank Color Red Register Default = 00h 0 Read/Write Image Fetcher Blank Color Red bits 7-0 7 REG[09B6h] bits 7-0 REG[09B5h] bits 7-0 REG[09B4h] bits 7-0 6 5 4 3 2 1 0 Image Fetcher Blank Color Red bits [7:0] Image Fetcher Blank Color Green bits [7:0] Image Fetcher Blank Color Blue bits [7:0] When the Image Fetcher Blank bit is set (REG[09B0h] bit 0 = 1b), these bits specify the RGB components of the color that the Image Fetcher replaces image data with. Note that the Image Fetcher pixel format is determined by the CH1IN pixel format, REG[4062h] bits 2-0. If the Image Fetcher Pixel Format is RGB 8:8:8 (REG[4062h] bits 2-0 = 010b). REG[09B6h] bits 7-0 = RED REG[09B5h] bits 7-0 = GREEN REG[09B4h] bits 7-0 = BLUE If the Image Fetcher Pixel Format is RGB 5:6:5 (REG[4062h] bits 2-0 = 001b). REG[09B6h] bits 7-3 = RED REG[09B5h] bits 7-2 = GREEN REG[09B4h] bits 7-3 = BLUE If the Image Fetcher Pixel Format is RGB 3:3:2 (REG[4062h] bits 2-0 = 000b). REG[09B6h] bits 7-5 = RED REG[09B5h] bits 7-5 = GREEN REG[09B4h] bits 7-6 = BLUE Hardware Functional Specification Rev. 1.7 EPSON 271 Chapter 10 Registers S1D13515/S2D13515 REG[09B8h] Image Fetcher Frame Buffer 0 Address Register 0 Default = 00h Read/Write Image Fetcher Frame Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[09B9h] Image Fetcher Frame Buffer 0 Address Register 1 Default = 00h 0 Read/Write Image Fetcher Frame Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[09BAh] Image Fetcher Frame Buffer 0 Address Register 2 Default = 00h 0 Read/Write Image Fetcher Frame Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[09BBh] Image Fetcher Frame Buffer 0 Address Register 3 Default = 10h 0 Read/Write Image Fetcher Frame Buffer 0 Address bits 31-24 7 REG[09BBh] bits 7-0 REG[09BAh] bits 7-0 REG[09B9h] bits 7-0 REG[09B8h] bits 7-0 272 6 5 4 3 2 1 0 Image Fetcher Frame Buffer 0 Address bits [31:0] These bits specify the memory start address for Image Fetcher Frame Buffer 0. These bits must be set such that the start address is 8 byte (64-bit) aligned. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09BCh] Image Fetcher Frame Buffer 1 Address Register 0 Default = 00h Read/Write Image Fetcher Frame Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[09BDh] Image Fetcher Frame Buffer 1 Address Register 1 Default = 00h 0 Read/Write Image Fetcher Frame Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[09BEh] Image Fetcher Frame Buffer 1 Address Register 2 Default = 00h 0 Read/Write Image Fetcher Frame Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[09BFh] Image Fetcher Frame Buffer 1 Address Register 3 Default = 10h 0 Read/Write Image Fetcher Frame Buffer 1 Address bits 31-24 7 REG[09BFh] bits 7-0 REG[09BEh] bits 7-0 REG[09BDh] bits 7-0 REG[09BCh] bits 7-0 6 5 4 3 2 1 0 Image Fetcher Frame Buffer 1 Address bits [31:0] These bits specify the memory start address for Image Fetcher Frame Buffer 1. These bits must be set such that the start address is 8 byte (64-bit) aligned. Hardware Functional Specification Rev. 1.7 EPSON 273 Chapter 10 Registers S1D13515/S2D13515 REG[09C0h] Image Fetcher Width Register 0 Default = 40h Read/Write Image Fetcher Width bits 7-0 7 6 5 4 3 2 1 REG[09C1h] Image Fetcher Width Register 1 Default = 01h Read/Write n/a 7 6 REG[09C1h] bits 2-0 REG[09C0h] bits 7-0 0 Image Fetcher Width bits 10-8 5 4 3 2 1 0 Image Fetcher Width bits [10:0] These bits specify the width of the Image Fetcher image, in pixels. REG[09C2h] Image Fetcher Height Register 0 Default = F0h Read/Write Image Fetcher Height bits 7-0 7 6 5 4 3 2 1 REG[09C3h] Image Fetcher Height Register 1 Default = 00h Read/Write n/a 7 6 REG[09C3h] bits 2-0 REG[09C2h] bits 7-0 5 0 Image Fetcher Height bits 10-8 4 3 2 1 0 Image Fetcher Height bits [10:0] These bits specify the height of the Image Fetcher image, in pixels. REG[09C4h] Image Fetcher Virtual Width Register 0 Default = 40h Read/Write Image Fetcher Virtual Width bits 7-0 7 6 5 4 3 2 1 REG[09C5h] Image Fetcher Virtual Width Register 1 Default = 01h Read/Write n/a 7 REG[09C5h] bits 4-0 REG[09C4h] bits 7-0 0 Image Fetcher Virtual Width bits 12-8 6 5 4 3 2 1 0 Image Fetcher Virtual Width bits [12:0] These bits specify the width of the Image Fetcher virtual image, in pixels. For an example showing a virtual source window, see Figure 13-9: “Virtual Source Window Example,” on page 459. Note The Image Fetcher virtual width must be set such that the virtual width multiplied by the pixel format (in bpp, see REG[4062h] bits 2-0) is divisible by 64. 274 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.13 LCD Configuration Registers REG[09C8h] LCD Control A Register Default = F0h Camera2 Frame Write Idle (RO) Camera1 Frame Write Idle (RO) CH1OUT Writeback Frame Write Idle (RO) 7 6 5 Read/Write Warp Writeback Frame Write Idle (RO) OSDIN Source Select CH2IN Source Select 4 3 2 CH1IN Source Select bits 1-0 1 0 bit 7 Camera2 Frame Write Idle (Read Only) This bit indicates whether the Camera2 Writer is writing a frame to SDRAM. When this bit = 0b, the Camera2 Writer is busy writing a frame to SDRAM. When this bit = 1b, the Camera2 Writer is idle. (default) bit 6 Camera1 Frame Write Idle (Read Only) This bit indicates whether the Camera1 Writer is writing a frame to SDRAM. When this bit = 0b, the Camera1 Writer is busy writing a frame to SDRAM. When this bit = 1b, the Camera1 Writer is idle. (default) bit 5 CH1OUT Writeback Frame Write Idle (Read Only) This bit indicates whether CH1OUT Writeback is writing a frame to SDRAM. For further information on CH1OUT Writeback, see Section 13.2.4, “CH1OUT Writeback” on page 462. When this bit = 0b, CH1OUT Writeback is busy writing a frame to SDRAM. When this bit = 1b, CH1OUT Writeback is idle. (default) bit 4 Warp Writeback Frame Write Idle (Read Only) This bit indicates whether Warp Writeback is writing a frame to SDRAM. For further information on Warp Writeback, see Section 13.2.5, “Warp Writeback” on page 463. When this bit = 0b, Warp Writeback is busy writing a frame to SDRAM. When this bit = 1b, Warp Writeback is idle. (default) bit 3 OSDIN Source Select This bit selects the Blending Engine output source used for the LCD controller input OSDIN. When this bit = 0b, OSDOUT is the OSDIN source. When this bit = 1b, CH1OUT is the OSDIN source (see Note). Note Only one of the LCD controller input channels can have CH1OUT as the source. For a summary of the possible settings, see Table 10-39: “CH1/CH2/OSD Input Source Selection,” on page 276. Hardware Functional Specification Rev. 1.7 EPSON 275 Chapter 10 Registers bit 2 S1D13515/S2D13515 CH2IN Source Select This bit selects the Blending Engine output source used for the LCD controller input CH2IN. When this bit = 0b, CH2OUT is the CH2IN source. When this bit = 1b, CH1OUT is the CH2IN source (see Note). Note Only one of the LCD controller input channels can have CH1OUT as the source. For a summary of the possible settings, see Table 10-39: “CH1/CH2/OSD Input Source Selection,” on page 276. bits 1-0 CH1IN Source Select bits [1:0] These bits select the output source used for the LCD controller input CH1IN. Note Only one of the LCD controller input channels can have CH1OUT as the source. For a summary of the possible settings, see Table 10-39: “CH1/CH2/OSD Input Source Selection,” on page 276. Table 10-39: CH1/CH2/OSD Input Source Selection REG[09C8h] bits 1-0 REG[09C8h] bit 2 0b 00b 1b 0b 01b 1b 0b 10b 1b 11b 276 Xb REG[09C8h] bit 3 CH1IN Source CH2IN Source OSDIN Source 0b CH1OUT CH2OUT OSDOUT 1b Reserved 0b Reserved 1b Reserved 0b 1b CH2OUT Warp 0b CH1OUT 1b Reserved 0b 1b Image Fetcher CH2OUT 0b CH1OUT 1b Reserved Xb Reserved EPSON OSDOUT CH1OUT OSDOUT OSDOUT CH1OUT OSDOUT Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09CAh] LCD Control B Register Default = 00h Read/Write Warp Writeback Mode Reserved Warp Writeback Vertical Flip Warp Writeback Manual Trigger (WO) CH1OUT Writeback Manual Trigger (WO) 7 6 5 4 3 bit 7 n/a 2 1 0 Warp Writeback Mode This bit only has an effect when Warp output is written back to the SDRAM, REG[09CAh] bit 6 = 1b. The bit specifies how Warp Writeback image data is stored in memory. For details on the memory organization methods, see Section 13.3, “Memory Organization of Frames” on page 465. When this bit = 0b, Warp Writeback uses “line-by-line” mode to write to SDRAM. When this bit = 1b, Warp Writeback uses “tiled-frame” mode to write to SDRAM. Note For tiled frame mode, the image width must be a multiple of 8 pixels and the Warp Writeback image data must not be flipped (REG[09CA0h] bit 5 = 0b). bit 6 Reserved This bit MUST be set to 1b when the HUD/Warp engine is used. bit 5 Warp Writeback Vertical Flip This bit only has an effect when Warp output is written back to the SDRAM, REG[09CAh] bit 6 = 1b. This bit determines whether image data output from the Warp Logic is flipped around the X axis (vertical).This bit must be set to 0b when Warp Writeback uses “tiled-frame” mode, REG[09CAh] bit 7 = 1b. When this bit = 0b, the Warp image data is not vertically flipped (disabled). When this bit = 1b, the Warp image data is vertically flipped (enabled). bit 4 Warp Writeback Manual Trigger (Write Only) This bit is a manual trigger which forces the Warp Writeback logic to process another frame and store it in the SDRAM. Writing a 0b to this bit has no effect. Writing a 1b to this bit forces the Warp Writeback logic to process another frame. Hardware Functional Specification Rev. 1.7 EPSON 277 Chapter 10 Registers S1D13515/S2D13515 bit 3 CH1OUT Writeback Manual Trigger (Write Only) This bit is a manual trigger which forces the CH1OUT Writeback logic to process another frame and store it in the SDRAM. Writing a 0b to this bit has no effect. Writing a 1b to this bit forces the CH1OUT Writeback logic to process another frame. Note Manually triggering CH1OUT Writeback to process another frame does not cause the MAIN frame buffer to switch. REG[09D0h] Warp Writeback Frame Buffer 0 Address Register 0 Default = 00h Read/Write Warp Writeback Frame Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[09D1h] Warp Writeback Frame Buffer 0 Address Register 1 Default = 00h 0 Read/Write Warp Writeback Frame Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[09D2h] Warp Writeback Frame Buffer 0 Address Register 2 Default = 00h 0 Read/Write Warp Writeback Frame Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[09D3h] Warp Writeback Frame Buffer 0 Address Register 3 Default = 10h 0 Read/Write Warp Writeback Frame Buffer 0 Address bits 31-24 7 REG[09D3h] bits 7-0 REG[09D2h] bits 7-0 REG[09D1h] bits 7-0 REG[09D0h] bits 7-0 278 6 5 4 3 2 1 0 Warp Writeback Frame Buffer 0 Address bits [31:0] These bits specify the memory start address for Warp Writeback Frame Buffer 0 which is used for writing image data processed by the Warp Logic back to the SDRAM. These bits must be set such that the start address is 8 byte (64-bit) aligned. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09D4h] Warp Writeback Frame Buffer 1 Address Register 0 Default = 00h Read/Write Warp Writeback Frame Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[09D5h] Warp Writeback Frame Buffer 1 Address Register 1 Default = 00h 0 Read/Write Warp Writeback Frame Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[09D6h] Warp Writeback Frame Buffer 1 Address Register 2 Default = 00h 0 Read/Write Warp Writeback Frame Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[09D7h] Warp Writeback Frame Buffer 1 Address Register 3 Default = 10h 0 Read/Write Warp Writeback Frame Buffer 1 Address bits 31-24 7 REG[09D7h] bits 7-0 REG[09D6h] bits 7-0 REG[09D5h] bits 7-0 REG[09D4h] bits 7-0 6 5 4 3 2 1 0 Warp Writeback Frame Buffer 1 Address bits [31:0] These bits specify the memory start address for Warp Writeback Frame Buffer 1 which is used for writing image data processed by the Warp Logic back to the SDRAM. These bits must be set such that the start address is 8 byte (64-bit) aligned. Hardware Functional Specification Rev. 1.7 EPSON 279 Chapter 10 Registers S1D13515/S2D13515 REG[09D8h] LCD Frame Control A Register 0 Default = 00h n/a 7 bits 6-4 Read/Write MAIN Window Hardware Frame Control Source bits 2-0 6 5 4 MAIN Window HW/SW Frame Control n/a 3 2 1 0 MAIN Window Hardware Frame Control Source bits [2:0] When hardware frame control is selected for the MAIN window (REG[09D8h] bit 0 = 1b), these bits determine the control source (or producer) that will set the MAIN Window Frame Control status bits in REG[0942h]. Table 10-40: MAIN Window Hardware Frame Source Selection bit 0 REG[09D8h] bits 6-4 Frame Source 000b Camera1 001b Camera2 010b Reserved 011b Warp Writeback 100b ~ 111b Sprite Engine MAIN Window HW/SW Frame Control This bit determines whether MAIN window double-buffering frame control is done by hardware or software. When hardware frame control is selected, the control source (or producer), as selected by REG[09D8h] bits 6-4, directly sets the Frame Control status bits in REG[0942h]. When software frame control is selected, software must set the Frame Control status bits. For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. When this bit = 0b, software frame control is selected. When this bit = 1b, hardware frame control is selected. Note 1. When Camera1 or Camera2 uses double buffer method 1 (REG[09F6h]/[09FEh] bit 7 = 1b) and Camera1 or Camera2 is selected as the MAIN window frame source, the setting of this bit is ignored and hardware frame control is used. 2. If the frame source for the MAIN window is double buffered (see REG[09DCh]), the frame source double buffering must be disabled before the MAIN window frame control setting is changed. The frame source double buffering may be re-enabled once the setting is changed. 280 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09D9h] LCD Frame Control A Register 1 Default = 00h n/a 7 bits 6-4 Read/Write AUX Window Hardware Frame Control Source bits 2-0 6 5 4 AUX Window HW/SW Frame Control n/a 3 2 1 0 AUX Window Hardware Frame Control Source bits [2:0] When hardware frame control is selected for the AUX window (REG[09D9h] bit 0 = 1b), these bits determine the control source (or producer) that will set the AUX Window Frame Control status bits in REG[0962h]. Table 10-41: AUX Window Hardware Frame Source Selection bit 0 REG[09D9h] bits 6-4 Frame Source 000b Camera1 001b Camera2 010b CH1OUT writeback 011b Warp writeback 100b - 111b Sprite Engine AUX Window HW/SW Frame Control This bit determines whether AUX window double-buffering frame control is done by hardware or software. When hardware frame control is selected, the control source (or producer), as selected by REG[09D9h] bits 6-4, directly sets the Frame Control status bits in REG[0962h]. When software frame control is selected, software must set the Frame Control status bits. For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. When this bit = 0b, software frame control is selected. When this bit = 1b, hardware frame control is selected. Note 1. When Camera1 or Camera2 uses double buffer method 1 (REG[09F6h]/[09FEh] bit 7 = 1b) and Camera1 or Camera2 is selected as the AUX window frame source, the setting of this bit is ignored and hardware frame control is used. 2. If the frame source for the AUX window is double buffered (see REG[09DCh]), the frame source double buffering must be disabled before the AUX window frame control setting is changed. The frame source double buffering may be re-enabled once the setting is changed. 3. Hardware Frame Control is only supported for Blend Modes 1, 2, and 3 (see REG[09A0h] bits 1-0) and CH1OUT writeback (REG[09D9h] bits 6-4 = 010b). Hardware Functional Specification Rev. 1.7 EPSON 281 Chapter 10 Registers S1D13515/S2D13515 REG[09DAh] LCD Frame Control B Register 0 Default = 00h n/a 7 bits 6-4 Read/Write OSD Window Hardware Frame Control Source bits 2-0 6 5 4 OSD Window HW/SW Frame Control n/a 3 2 1 0 OSD Window Hardware Frame Control Source bits [2:0] When hardware frame control is selected for the OSD window (REG[09DAh] bit 0 = 1b), these bits determine the control source (or producer) that will set the OSD Window Frame Control status bits in REG[0982h]. Table 10-42: OSD Window Hardware Frame Source Selection bit 0 REG[09DAh] bits 6-4 Frame Source 000b Camera1 001b Camera2 010b CH1OUT writeback 011b Warp writeback 100b Sprite Engine OSD Window HW/SW Frame Control This bit determines whether OSD window double-buffering frame control is done by hardware or software. When hardware frame control is selected, the control source (or producer), as selected by REG[09DAh] bits 6-4, directly sets the Frame Control status bits in REG[0982h]. When software frame control is selected, software must set the Frame Control status bits. For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. When this bit = 0b, software frame control is selected. When this bit = 1b, hardware frame control is selected. Note 1. When Camera1 or Camera2 uses double buffer method 1 (REG[09F6h]/[09FEh] bit 7 = 1b) and Camera1 or Camera2 is selected as the OSD window frame source, the setting of this bit is ignored and hardware frame control is used. 2. If the frame source for the OSD window is double buffered (see REG[09DCh]), the frame source double buffering must be disabled before the OSD window frame control setting is changed. The frame source double buffering may be re-enabled once the setting is changed. 3. Hardware Frame Control is only supported for Blend Modes 2 and 3 (see REG[09A0h] bits 1-0) and CH1OUT writeback (REG[09DAh] bits 6-4 = 010b). 282 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09DBh] LCD Frame Control B Register 1 Default = 00h n/a 7 bits 6-4 Read/Write Image Fetcher Hardware Frame Control Source bits 2-0 6 5 4 Image Fetcher HW/SW Frame Control n/a 3 2 1 0 Image Fetcher Hardware Frame Control Source bits [2:0] When hardware frame control is selected for the Image Fetcher (REG[09DBh] bit 0 = 1b), these bits determine the control source (or producer) that will set the Image Fetcher Frame Control status bits in REG[09B2h]. Table 10-43: Image Fetcher Hardware Frame Source Selection bit 0 REG[09DBh] bits 6-4 Frame Source 000b Camera1 001b Reserved 010b CH1OUT writeback 011b Warp writeback 100b Sprite Engine Image Fetcher HW/SW Frame Control This bit determines whether Image Fetcher double-buffering frame control is done by hardware or software. When hardware frame control is selected, the control source (or producer), as selected by REG[09DBh] bits 6-4, directly sets the Frame Control status bits in REG[09B2h]. When software frame control is selected, software must set the Frame Control status bits. For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. When this bit = 0b, software frame control is selected. When this bit = 1b, hardware frame control is selected. Note 1. When Camera1 or Camera2 uses double buffer method 1 (REG[09F6h]/[09FEh] bit 7 = 1b) and Camera1 or Camera2 is selected as the Image Fetcher frame source, the setting of this bit is ignored and hardware frame control is used. 2. If the frame source for the Image Fetcher is double buffered (see REG[09DCh]), the frame source double buffering must be disabled before the Image Fetcher frame control setting is changed. The frame source double buffering may be re-enabled once the setting is changed. Hardware Functional Specification Rev. 1.7 EPSON 283 Chapter 10 Registers S1D13515/S2D13515 REG[09DCh] LCD Frame Control C Register 0 Default = 00h n/a 7 bits 6-4 Read/Write Warp Logic Hardware Frame Control Source bits 2-0 6 5 4 Camera2 Frame Double-Buffer Disable Camera1 Frame Double-Buffer Disable CH1OUT Writeback Frame Double-Buffer Disable Warp Writeback Frame DoubleBuffer Disable 3 2 1 0 Warp Logic Hardware Frame Control Source bits [2:0] When hardware frame control is selected for the Warp Logic (REG[0400h] bit 6 = 1b), these bits determine the control source (or producer) that will set the Warp Frame Control status bits in REG[0408h] ~ REG[040Ah]. Table 10-44: Warp Logic Hardware Frame Source Selection REG[09DCh] bits 6-4 Frame Source 000b Camera1 001b Camera2 010b CH1OUT writeback 011b Reserved 100b ~ 111b Sprite Engine bit 3 Camera2 Writeback Frame Double-Buffer Disable This bit is used to disable hardware controlled frame double-buffering for Camera2 Writeback. When this bit = 0b, hardware controlled frame double-buffering is enabled. (default) When this bit = 1b, hardware controlled frame double-buffering is disabled and Camera2 Writeback only writes to buffer 0. bit 2 Camera1 Writeback Frame Double-Buffer Disable This bit used to disable hardware controlled frame double-buffering for Camera1 Writeback. When this bit = 0b, hardware controlled frame double-buffering is enabled. (default) When this bit = 1b, hardware controlled frame double-buffering is disabled and Camera1 Writeback only writes to buffer 0. bit 1 CH1OUT Writeback Frame Double-Buffer Disable This bit used to disable hardware controlled frame double-buffering for CH1OUT Writeback. When this bit = 0b, hardware controlled frame double-buffering is enabled. (default) When this bit = 1b, hardware controlled frame double-buffering is disabled and CH1OUT Writeback only writes to buffer 0. bit 0 Warp Writeback Frame Double-Buffer Disable This bit used to disable the hardware controlled frame double-buffering for Warp Writeback. When this bit = 0b, hardware controlled frame double-buffering is enabled. (default) When this bit = 1b, hardware controlled frame double-buffering is disabled and Warp Writeback only writes to buffer 0. 284 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09DDh] LCD Frame Control C Register 1 Default = 00h Read/Write n/a 7 bits 3-0 6 Sprite Engine Hardware Frame Control Destination bits 3-0 5 4 3 2 1 0 Sprite Engine Hardware Frame Control Destination bits [3:0] These bits select the destination (or consumer) for image data from the Sprite Engine. This allows the Sprite Engine (or producer) to receive frame control status information from the selected destination when Hardware Frame Control is enabled (see REG[09D8h] ~ REG[09DBh] bit 0 or REG[0400h] bit 6). For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. Table 10-45: Sprite Engine Hardware Frame Control Destination Selection REG[09DDh] bits 3-0 Frame Control Destination 0000b MAIN Window Hardware Frame Control 0010b AUX Window Hardware Frame Control 0100b OSD Window Hardware Frame Control 0110b Image Fetcher Hardware Frame Control Other values Warp Hardware Frame Control Hardware Functional Specification Rev. 1.7 EPSON 285 Chapter 10 Registers S1D13515/S2D13515 REG[09DEh] LCD Frame Control D Register 0 Default = 00h Read/Write Camera2 Hardware Frame Control Destination bits 3-0 7 bits 7-4 6 5 Camera1 Hardware Frame Control Destination bits 3-0 4 3 2 1 0 Camera2 Hardware Frame Control Destination bits [3:0] These bits select the destination (or consumer) for image data from the Camera2 interface. This allows the Camera2 interface (or producer) to receive frame control status information from the selected destination when Hardware Frame Control is enabled (see REG[09D8h] ~ REG[09DBh] bit 0 or REG[0400h] bit 6). For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. Table 10-46: Camera2 Hardware Frame Control Destination Selection bits 3-0 REG[09DEh] bits 7-4 Frame Control Destination 0000b MAIN Window Hardware Frame Control 0010b AUX Window Hardware Frame Control 0100b OSD Window Hardware Frame Control 0110b Image Fetcher Hardware Frame Control Other values Warp Hardware Frame Control Camera1 Hardware Frame Control Destination bits [3:0] These bits select the destination (or consumer) for image data from the Camera1 interface. This allows the Camera1 interface (or producer) to receive frame control status information from the selected destination when Hardware Frame Control is enabled (see REG[09D8h] ~ REG[09DBh] bit 0 or REG[0400h] bit 6). For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. Table 10-47: Camera1 Hardware Frame Control Destination Selection 286 REG[09DEh] bits 3-0 Frame Control Destination 0000b MAIN Window Hardware Frame Control 0010b AUX Window Hardware Frame Control 0100b OSD Window Hardware Frame Control 0110b Image Fetcher Hardware Frame Control Other values Warp Hardware Frame Control EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09DFh] LCD Frame Control D Register 1 Default = 00h Read/Write Warp Writeback Hardware Frame Control Destination bits 3-0 7 bits 7-4 6 5 CH1OUT Writeback Hardware Frame Control Destination bits 3-0 4 3 2 1 0 Warp Writeback Hardware Frame Control Destination bits [3:0] These bits select the destination (or consumer) for image data from Warp Writeback. This allows the Warp Writeback (or producer) to receive frame control status information from the selected destination when Hardware Frame Control is enabled (see REG[09D8h] ~ REG[09DBh] bit 0 or REG[0400h] bit 6). For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. Table 10-48: Warp Writeback Hardware Frame Control Destination Selection bits 3-0 REG[09DFh] bits 7-4 Frame Control Destination 0000b MAIN Window Hardware Frame Control 0010b AUX Window Hardware Frame Control 0100b OSD Window Hardware Frame Control 0110b Image Fetcher Hardware Frame Control Other values Reserved CH1OUT Writeback Hardware Frame Control Destination bits [3:0] These bits select the destination (or consumer) for image data from CH1OUT Writeback. This allows the CH1OUT Writeback (or producer) to receive frame control status information from the selected destination when Hardware Frame Control is enabled (see REG[09D8h] ~ REG[09DBh] bit 0 or REG[0400h] bit 6). For further information on frame control and double buffering, see Section 13.4, “Frame Double-Buffering Scheme” on page 467. Table 10-49: CH1OUT Writeback Hardware Frame Control Destination Selection REG[09DFh] bits 3-0 Frame Control Destination 0000b MAIN Window Hardware Frame Control 0010b AUX Window Hardware Frame Control 0100b OSD Window Hardware Frame Control 0110b Image Fetcher Hardware Frame Control Other values Warp Hardware Frame Control Hardware Functional Specification Rev. 1.7 EPSON 287 Chapter 10 Registers S1D13515/S2D13515 REG[09E0h] Camera1 Frame Buffer 0 Address Register 0 Default = 00h Read/Write Camera1 Frame Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[09E1h] Camera1 Frame Buffer 0 Address Register 1 Default = 00h 0 Read/Write Camera1 Frame Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[09E2h] Camera1 Frame Buffer 0 Address Register 2 Default = 00h 0 Read/Write Camera1 Frame Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[09E3h] Camera1 Frame Buffer 0 Address Register 3 Default = 10h 0 Read/Write Camera1 Frame Buffer 0 Address bits 31-24 7 REG[09E3h] bits 7-0 REG[09E2h] bits 7-0 REG[09E1h] bits 7-0 REG[09E0h] bits 7-0 288 6 5 4 3 2 1 0 Camera1 Frame Buffer 0 Address bits [31:0] These bits specify the memory start address for Camera1 Frame Buffer 0 which is used for input image data from Camera1. These bits must be set such that the start address is 8 byte (64-bit) aligned. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09E4h] Camera1 Frame Buffer 1 Address Register 0 Default = 00h Read/Write Camera1 Frame Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[09E5h] Camera1 Frame Buffer 1 Address Register 1 Default = 00h 0 Read/Write Camera1 Frame Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[09E6h] Camera1 Frame Buffer 1 Address Register 2 Default = 00h 0 Read/Write Camera1 Frame Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[09E7h] Camera1 Frame Buffer 1 Address Register 3 Default = 10h 0 Read/Write Camera1 Frame Buffer 1 Address bits 31-24 7 REG[09E7h] bits 7-0 REG[09E6h] bits 7-0 REG[09E5h] bits 7-0 REG[09E4h] bits 7-0 6 5 4 3 2 1 0 Camera1 Frame Buffer 1 Address bits [31:0] These bits specify the memory start address for Camera1 Frame Buffer 1 which is used for input image data from Camera1. These bits must be set such that the start address is 8 byte (64-bit) aligned. Hardware Functional Specification Rev. 1.7 EPSON 289 Chapter 10 Registers S1D13515/S2D13515 REG[09E8h] Camera2 Frame Buffer 0 Address Register 0 Default = 00h Read/Write Camera2 Frame Buffer 0 Address bits 7-0 7 6 5 4 3 2 1 REG[09E9h] Camera2 Frame Buffer 0 Address Register 1 Default = 00h 0 Read/Write Camera2 Frame Buffer 0 Address bits 15-8 7 6 5 4 3 2 1 REG[09EAh] Camera2 Frame Buffer 0 Address Register 2 Default = 00h 0 Read/Write Camera2 Frame Buffer 0 Address bits 23-16 7 6 5 4 3 2 1 REG[09EBh] Camera2 Frame Buffer 0 Address Register 3 Default = 10h 0 Read/Write Camera2 Frame Buffer 0 Address bits 31-24 7 REG[09EBh] bits 7-0 REG[09EAh] bits 7-0 REG[09E9h] bits 7-0 REG[09E8h] bits 7-0 290 6 5 4 3 2 1 0 Camera2 Frame Buffer 0 Address bits [31:0] These bits specify the memory start address for Camera2 Frame Buffer 0 which is used for input image data from Camera2. These bits must be set such that the start address is 8 byte (64-bit) aligned. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09ECh] Camera2 Frame Buffer 1 Address Register 0 Default = 00h Read/Write Camera2 Frame Buffer 1 Address bits 7-0 7 6 5 4 3 2 1 REG[09EDh] Camera2 Frame Buffer 1 Address Register 1 Default = 00h 0 Read/Write Camera2 Frame Buffer 1 Address bits 15-8 7 6 5 4 3 2 1 REG[09EEh] Camera2 Frame Buffer 1 Address Register 2 Default = 00h 0 Read/Write Camera2 Frame Buffer 1 Address bits 23-16 7 6 5 4 3 2 1 REG[09EFh] Camera2 Frame Buffer 1 Address Register 3 Default = 10h 0 Read/Write Camera2 Frame Buffer 1 Address bits 31-24 7 REG[09EFh] bits 7-0 REG[09EEh] bits 7-0 REG[09EDh] bits 7-0 REG[09ECh] bits 7-0 6 5 4 3 2 1 0 Camera2 Frame Buffer 1 Address bits [31:0] These bits specify the memory start address for Camera2 Frame Buffer 1 which is used for input image data from Camera2. These bits must be set such that the start address is 8 byte (64-bit) aligned. Hardware Functional Specification Rev. 1.7 EPSON 291 Chapter 10 Registers S1D13515/S2D13515 REG[09F0h] Camera1 Frame Buffer Width Register 0 Default = 40h Read/Write Camera1 Frame Buffer Width bits 7-0 7 6 5 4 3 2 1 REG[09F1h] Camera1 Frame Buffer Width Register 1 Default = 01h Read/Write n/a 7 6 REG[09F1h] bits 2-0 REG[09F0h] bits 7-0 5 0 Camera1 Frame Buffer Width bits 10-8 4 3 2 1 0 Camera1 Frame Buffer Width bits [10:0] These bits specify the width of the Camera1 frame buffer, in pixels. Note The Camera1 frame buffer width must be set such that the width multiplied by the pixel format (in bpp, see REG[09F6h] bits 3-2) is divisible by 64. REG[09F2h] Camera1 Frame Buffer Height Register 0 Default = F0h Read/Write Camera1 Frame Buffer Height bits 7-0 7 6 5 4 3 2 1 REG[09F3h] Camera1 Frame Buffer Height Register 1 Default = 00h Read/Write n/a 7 6 REG[09F3h] bits 2-0 REG[09F2h] bits 7-0 5 0 Camera1 Frame Buffer Height bits 10-8 4 3 2 1 0 Camera1 Frame Buffer Height bits [10:0] These bits specify the height of the Camera1 frame buffer, in pixels. REG[09F4h] Camera1 Frame Buffer Virtual Width Register 0 Default = 40h Read/Write Camera1 Frame Buffer Virtual Width bits 7-0 7 6 5 4 3 2 1 REG[09F5h] Camera1 Frame Buffer Virtual Width Register 1 Default = 01h n/a 7 REG[09F5h] bits 4-0 REG[09F4h] bits 7-0 0 Read/Write Camera1 Frame Buffer Virtual Width bits 12-8 6 5 4 3 2 1 0 Camera1 Frame Buffer Virtual Width bits [12:0] These bits specify the virtual width of the Camera1 frame buffer, in pixels. Note The Camera1 frame buffer virtual width must be set such that the virtual width multiplied by the pixel format (in bpp, see REG[09F6h] bits 3-2) is divisible by 64. 292 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09F6h] Camera1 Write Control Register Default = 00h Camera1 DoubleBuffer Method Select Reserved 7 6 bit 7 Read/Write n/a 5 Camera1 Pixel Format bits 1-0 4 3 2 n/a Camera1 Vertical Flip Enable 1 0 Camera1 Double-Buffer Method Select This bit selects the double-buffering method used for Camera1 input image data. When this bit = 0b, method 0 is used. When this bit = 1b, method 1 is used. This method can be used when the LCD refresh rate is faster than the Camera1 input stream rate. Note 1. When this bit = 1b, Vertical Flip must be disabled. Vertical Flip for the destination (or consumer) must also be disabled (REG[0940h]/[0960h]/[0980h]/[09B0h] bit 5 = 0b). 2. When this bit = 1b, software frame control is not supported for double buffering to the destination window (REG[09D8h]/[09D9h]/[09DAh]/[09DBh] bit 0 must be set to 1b). Also, when this bit = 1b, the frame buffer ready bits for the destination windows are invalid (see REG[0942h]/[0962h]/[0982h]/[09B2h] bits 1-0). 3. When this bit = 1b, Camera1 cannot be the source for Warp Hardware Frame Control (see REG[09DCh] and REG[09DEh] bits 3-0). bit 6 Reserved This bit must be set to 0b. bits 3-2 Camera1 Pixel Format bits [1:0] These bits determine the RGB pixel format of the Camera1 image data stored in SDRAM. Table 10-50: Camera1 Pixel Format Selection bit 0 REG[09F6h] bits 3-2 Pixel Format 00b 8 bpp (RGB 3:3:2) 01b 16 bpp (RGB 5:6:5) 10b 24 bpp (RGB 8:8:8) 11b Reserved Camera1 Vertical Flip Enable This bit determines whether the image data input from the Camera1 interface is flipped around the X axis (vertical). When this bit = 0b, the Camera1 image data is not vertically flipped (disabled). When this bit = 1b, the Camera1 image data is vertically flipped (enabled). Hardware Functional Specification Rev. 1.7 EPSON 293 Chapter 10 Registers S1D13515/S2D13515 REG[09F8h] Camera2 Frame Buffer Width Register 0 Default = 40h Read/Write Camera2 Frame Buffer Width bits 7-0 7 6 5 4 3 2 1 REG[09F9h] Camera2 Frame Buffer Width Register 1 Default = 01h Read/Write n/a 7 6 REG[09F9h] bits 2-0 REG[09F8h] bits 7-0 5 0 Camera2 Frame Buffer Width bits 10-8 4 3 2 1 0 Camera2 Frame Buffer Width bits [10:0] These bits specify the width of the Camera2 frame buffer, in pixels. Note The Camera2 frame buffer width must be set such that the width multiplied by the pixel format (in bpp, see REG[09FEh] bits 3-2) is divisible by 64. REG[09FAh] Camera2 Frame Buffer Height Register 0 Default = F0h Read/Write Camera2 Frame Buffer Height bits 7-0 7 6 5 4 3 2 1 REG[09FBh] Camera2 Frame Buffer Height Register 1 Default = 00h Read/Write n/a 7 6 REG[09FBh] bits 2-0 REG[09FAh] bits 7-0 5 0 Camera2 Frame Buffer Height bits 10-8 4 3 2 1 0 Camera2 Frame Buffer Height bits [10:0] These bits specify height of the Camera2 frame buffer, in pixels. REG[09FCh] Camera2 Frame Buffer Virtual Width Register 0 Default = 40h Read/Write Camera1 Frame Buffer Virtual Width bits 7-0 7 6 5 4 3 2 1 REG[09FDh] Camera2 Frame Buffer Virtual Width Register 1 Default = 01h n/a 7 REG[09FDh] bits 4-0 REG[09FCh] bits 7-0 0 Read/Write Camera2 Frame Buffer Virtual Width bits 12-8 6 5 4 3 2 1 0 Camera2 Frame Buffer Virtual Width bits [12:0] These bits specify the virtual width of the Camera2 frame buffer, in pixels. Note The Camera2 frame buffer virtual width must be set such that the virtual width multiplied by the pixel format (in bpp, see REG[09FEh] bits 3-2) is divisible by 64. 294 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[09FEh] Camera2 Write Control Register Default = 00h Camera2 Double Buffer Method Select Reserved 7 6 bit 7 Read/Write n/a 5 Camera2 Pixel Format bits 1-0 4 3 2 n/a Camera2 Vertical Flip Enable 1 0 Camera2 Double Buffer Method Select This bit selects the double-buffering method used for Camera2 input image data. When this bit = 0b, method 0 is used. When this bit = 1b, method 1 is used. This method can be used when the LCD refresh rate is faster than the Camera2 input stream rate. Note 1. When this bit = 1b, vertical mirroring of the streaming Camera2 image is not supported. Therefore, Camera2 vertical mirroring must be disabled (REG[09FEh] bit 0 = 0b) and the destination window vertical mirroring must be disabled (REG[0940h]/[0960h]/[0980h]/[09B0h] bit 5 = 0b). 2. When this bit = 1b, software frame control is not supported for double buffering to the destination window (REG[09D8h]/[09D9h]/[09DAh]/[09DBh] bit 0 is ignored). Also, when this bit = 1b, the frame buffer ready bits for the destination windows are invalid (see REG[0942h]/[0962h]/[0982h]/[09B2h] bits 1-0). 3. When this bit = 1b, Camera2 cannot be the source for Warp Hardware Frame Control (see REG[09DCh] and REG[09DEh] bits 7-4). bit 6 Reserved This bit must be set to 0b. bits 3-2 Camera2 Pixel Format bits [1:0] These bits determine the RGB pixel format of the Camera2 image data stored in SDRAM. Table 10-51: Camera2 Pixel Format Selection bit 0 REG[09FEh] bits 3-2 Pixel Format 00b 8 bpp (RGB 3:3:2) 01b 16 bpp (RGB 5:6:5) 10b 24 bpp (RGB 8:8:8) 11b Reserved Camera2 Vertical Flip Enable This bit determines whether the image data input from the Camera2 interface is flipped around the X axis (vertical). When this bit = 0b, the Camera2 image data is not vertically flipped (disabled). When this bit = 1b, the Camera2 image data is vertically flipped (enabled). Hardware Functional Specification Rev. 1.7 EPSON 295 Chapter 10 Registers S1D13515/S2D13515 10.4.14 Interrupt Configuration Registers REG[0A00h] Interrupt Status Register 0 Default = 00h Sprite Interrupt Status (RO) I2S DAC Interrupt (RO) SDRAM Read/Write Buffer Interrupt Status (RO) 7 6 5 bit 7 Read/Write n/a I2S DAC DMA Interrupt Status (RO) Watchdog Timer Interrupt Status LCD2 Interrupt Status (RO) LCD1 Interrupt Status (RO) 4 3 2 1 0 Sprite Interrupt Status (Read Only) This bit indicates the status of the Sprite Interrupt which occurs when a sprite operation completes (REG[5008h] bit 1 = 1b) and the Sprite Operation Complete Interrupt Enable bit is set (REG[5006h] bit 1 = 1b). This interrupt can be configured to cause a Host interrupt signal (see REG[0A06h] bit 7) or a C33PE interrupt signal (see REG[0A0Eh] bit 7). When this bit = 0b, a Sprite Interrupt has not occurred. When this bit = 1b, a Sprite Interrupt has occurred. To clear this status bit, write a 1b to REG[5008h] bit 1. bit 6 I2S DAC Interrupt Status (Read Only) This bit indicates the status of the I2S DAC Interrupt which occurs when one of three I2S FIFO interrupts occurs. This bit is the combination (logical OR) of the I2S FIFO Threshold Interrupt Status, I2S FIFO Overrun Interrupt Status, and I2S FIFO Underrun Interrupt Status bits (REG[010Ch] bits 2-0). Each I2S FIFO interrupt status bit can be masked from causing an I2S DAC Interrupt using the corresponding interrupt enable bits in REG[0105h] bit 2-0. This interrupt can be configured to cause a Host interrupt signal (see REG[0A06h] bit 6) or a C33PE interrupt signal (see REG[0A0Eh] bit 6). When this bit = 0b, an I2S DAC Interrupt has not occurred. When this bit = 1b, an I2S DAC Interrupt has occurred. To clear this status bit, write a 1b to the corresponding interrupt status bit in REG[010Ch]. bit 5 SDRAM Read/Write Buffer Interrupt Status (Read Only) This bit indicates the status of the SDRAM Read/Write Buffer Interrupt which occurs when a transfer between one of the SDRAM buffers and SDRAM completes. This bit is the combination (logical OR) of the SDRAM Buffer 0 Done Interrupt Status/Clear and the SDRAM Buffer 1 Done Interrupt Status/Clear bits (REG[0242h]/[0252h] bit 3). Each SDRAM buffer done interrupt status bit can be masked from causing a SDRAM Read/Write Buffer Interrupt using the corresponding interrupt enable bits in REG[0240h]/[0250h] bit 3. This interrupt can be configured to cause a Host interrupt signal (see REG[0A06h] bit 5) or a C33PE interrupt signal (see REG[0A0Eh] bit 5). When this bit = 0b, a SDRAM Read/Write Buffer Interrupt has not occurred. When this bit = 1b, a SDRAM Read/Write Buffer Interrupt has occurred. To clear this status bit, clear both SDRAM Buffer Done Interrupt Status bits (REG[0242h] bit 3 = 0b and REG[0252h] bit 3 = 0b). 296 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 bit 3 Chapter 10 Registers I2S DAC DMA Interrupt Status (Read Only) This bit indicates the status of the I2S DAC DMA Interrupt which occurs when the I2S DMA logic finishes reading from a DAC DMA buffer and switches to reading from the other buffer. This bit mirrors the I2S DMA Interrupt Status bit in REG[0154h] bit 3. This interrupt can be configured to cause a Host interrupt signal (see REG[0A06h] bit 3). This interrupt bit goes to IRQ3 of the C33PE Interrupt Controller (see REG[0A42h] and REG[0A44h]. When this bit = 0b, an I2S DAC DMA Interrupt has not occurred. When this bit = 1b, an I2S DAC DMA Interrupt has occurred. To clear this status bit, write a 1b to REG[0154h] bit 3. bit 2 Watchdog Timer Interrupt Status This bit indicates the status of the Watchdog Timer Interrupt which occurs when the Watchdog Timer logic finishes counting. This interrupt can be configured to cause a Host interrupt signal (see REG[0A06h] bit 2). This interrupt bit goes to IRQ2 of the C33PE Interrupt Controller (see REG[0A42h] and REG[0A44h]. When this bit = 0b, an Watchdog Timer Interrupt has not occurred. When this bit = 1b, an Watchdog Timer Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 1 LCD2 Interrupt Status (Read Only) This bit indicates the status of the LCD2 Interrupt which occurs when a LCD2 VSYNC Interrupt occurs (REG[4037h] bit 3 = 1b) and the LCD2 VSYNC Interrupt is enabled (REG[4019h] bit 7 = 1b). When this bit = 0b, a LCD2 Interrupt has not occurred. When this bit = 1b, a LCD2 Interrupt has occurred. To clear this status bit, write a 1b to REG[4037h] bit 3. bit 0 LCD1 Interrupt Status (Read Only) This bit indicates the status of the LCD1 Interrupt which occurs when a LCD1 VSYNC Interrupt occurs (REG[4019h] bit 3 = 1b) and the LCD1 VSYNC Interrupt is enabled (REG[4019h] bit 7 = 1b). When this bit = 0b, a LCD1 Interrupt has not occurred. When this bit = 1b, a LCD1 Interrupt has occurred. To clear this status bit, write a 1b to REG[4019h] bit 3. Hardware Functional Specification Rev. 1.7 EPSON 297 Chapter 10 Registers S1D13515/S2D13515 REG[0A02h] Interrupt Status Register 1 Default = 00h Read/Write Manual C33PE to Host Interrupt Status Reserved Reserved Keypad Interrupt Status (RO) Timer 1 Interrupt Status Timer 0 Interrupt Status DMA Channel 1 Transfer Done Interrupt Status DMA Channel 0 Transfer Done Interrupt Status 7 6 5 4 3 2 1 0 bit 7 Manual C33PE to Host Interrupt Status This bit indicates the status of the Manual C33PE to Host Interrupt which can be triggered using the Manual C33PE to Host Interrupt Trigger bit, REG[0A46h] bit 0. The C33PE or the Host itself can trigger this interrupt. This interrupt will only cause a Host interrupt signal if REG[0A08h] bit 7 is set to 1b. When this bit = 0b, a Manual C33PE to Host Interrupt has not occurred. When this bit = 1b, a Manual C33PE to Host Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 6 Reserved The default value for this bit is 0b. bit 5 Reserved The default value for this bit is 0b. bit 4 Keypad Interrupt Status (Read Only) This bit indicates the status of the Keypad Interrupt which occurs when one of the 25 Keypad Interrupt Status/Clear bits are set in REG[01D0h] ~ REG[01D3h]. Each status bit can be masked from causing a Keypad Interrupt using the corresponding interrupt enable bits in REG[01C4h] ~ REG[01C7h]. This interrupt can be configured to cause a Host interrupt signal (see REG[0A08h] bit 4) or a C33PE interrupt signal (see REG[0A10h] bit 4). When this bit = 0b, a Keypad Interrupt has not occurred. When this bit = 1b, a Keypad Interrupt has occurred. To clear this status bit, clear all the status bits in REG[01D0h] ~ REG[01D3h]. bit 3 Timer 1 Interrupt Status This bit indicates the status of the Timer 1 Interrupt which occurs when Timer 1 is enabled (REG[0A84h] bit 1 = 1b) and the Timer 1 Period (REG[0A8Ah]) has passed. This bit is not masked by the Timer 1 Interrupt Enable bit, REG[0A08h] bit 3. This interrupt can be configured to cause a Host interrupt signal (see REG[0A08h] bit 3) or a C33PE interrupt signal (see REG[0A10h] bit 3). When this bit = 0b, a Timer 1 Interrupt has not occurred. When this bit = 1b, a Timer 1 Interrupt has occurred. To clear this status bit, write a 1b to this bit. 298 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 bit 2 Chapter 10 Registers Timer 0 Interrupt Status This bit indicates the status of the Timer 0 Interrupt which occurs when Timer 0 is enabled (REG[0A84h] bit 0 = 1b) and the Timer 0 Period (REG[0A88h] ~ REG[0A89h]) has passed. This bit is not masked by the Timer 0 Interrupt Enable bit, REG[0A08h] bit 2. This interrupt can be configured to cause a Host interrupt signal (see REG[0A08h] bit 2) or a C33PE interrupt signal (see REG[0A10h] bit 2). When this bit = 0b, a Timer 0 Interrupt has not occurred. When this bit = 1b, a Timer 0 Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 1 DMA Channel 1 Transfer Done Interrupt Status This bit indicates the status of the DMA Channel 1 Transfer Done Interrupt which occurs when a transfer on DMA Channel 1 completes. This bit is not masked by the DMA Channel 1 Transfer Done Interrupt Enable bit, REG[0A08h] bit 1. This interrupt can be configured to cause a Host interrupt signal (see REG[0A08h] bit 1) or a C33PE interrupt signal (see REG[0A10h] bit 1). When this bit = 0b, a DMA Channel 1 Transfer Done Interrupt has not occurred. When this bit = 1b, a DMA Channel 1 Transfer Done Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 0 DMA Channel 0 Transfer Done Interrupt Status This bit indicates the status of the DMA Channel 0 Transfer Done Interrupt which occurs when a transfer on DMA Channel 0 completes. This bit is not masked by the DMA Channel 1 Transfer Done Interrupt Enable bit, REG[0A08h] bit 1. This interrupt can be configured to cause a Host interrupt signal (see REG[0A08h] bit 0) or a C33PE interrupt signal (see REG[0A10h] bit 0). When this bit = 0b, a DMA Channel 0 Transfer Done Interrupt has not occurred. When this bit = 1b, a DMA Channel 0 Transfer Done Interrupt has occurred. To clear this status bit, write a 1b to this bit. Hardware Functional Specification Rev. 1.7 EPSON 299 Chapter 10 Registers S1D13515/S2D13515 REG[0A04h] Interrupt Status Register 2 Default = 00h bit 6 Read/Write n/a Image Fetcher Frame Start Interrupt Status OSD Window Frame Start Interrupt Status AUX Window Frame Start Interrupt Status MAIN Window Frame Start Interrupt Status Warp Logic Frame Buffer Switch Interrupt Status Warp Logic Luminance Table Interrupt Status Warp Logic Offset Table Interrupt Status 7 6 5 4 3 2 1 0 Image Fetcher Frame Start Interrupt Status This bit indicates the status of the Image Fetcher Frame Start Interrupt which occurs when the Image Fetcher has started processing a new frame and has latched the width and virtual width registers. This interrupt can be used to prevent the “tearing effect” when programming new width/virtual width values. It can also be used by software to control frame double-buffering. This interrupt can be configured to cause a Host interrupt signal (see REG[0A0Ah] bit 6) or a C33PE interrupt signal (see REG[0A12h] bit 6). When this bit = 0b, an Image Fetcher Frame Start Interrupt has not occurred. When this bit = 1b, an Image Fetcher Frame Start Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 5 OSD Window Frame Start Interrupt Status This bit indicates the status of the OSD Window Frame Start Interrupt which occurs when the Blending Engine has started processing a new OSD window frame and has latched the width and virtual width registers. This interrupt can be used to prevent the “tearing effect” when programming new width/virtual width values. It can also be used by software to control frame double-buffering. This interrupt can be configured to cause a Host interrupt signal (see REG[0A0Ah] bit 5) or a C33PE interrupt signal (see REG[0A12h] bit 5). When this bit = 0b, an OSD Window Frame Start Interrupt has not occurred. When this bit = 1b, an OSD Window Frame Start Interrupt has occurred. To clear this status bit, write a 1b to this bit. Note If this interrupt is enabled (REG[0A0Ah] bit 5 = 1b) before the OSD window is enabled (REG[0980h] bit 4 = 1b), the first occurrence of the OSD Window Frame Start Interrupt Status should be ignored and cleared (REG[0A04h] bit 5 = 1b). Any subsequent OSD Window Frame Start Interrupt Status is valid. 300 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 bit 4 Chapter 10 Registers AUX Window Frame Start Interrupt Status This bit indicates the status of the AUX Window Frame Start Interrupt which occurs when the Blending Engine has started processing a new AUX window frame and has latched the width and virtual width registers. This interrupt can be used to prevent the “tearing effect” when programming new width/virtual width values. It can also be used by software to control frame double-buffering. This interrupt can be configured to cause a Host interrupt signal (see REG[0A0Ah] bit 4) or a C33PE interrupt signal (see REG[0A12h] bit 4). When this bit = 0b, an AUX Window Frame Start Interrupt has not occurred. When this bit = 1b, an AUX Window Frame Start Interrupt has occurred. To clear this status bit, write a 1b to this bit. Note If this interrupt is enabled (REG[0A0Ah] bit 4 = 1b) before the AUX window is enabled (REG[0960h] bit 4 = 1b), the first occurrence of the AUX Window Frame Start Interrupt Status should be ignored and cleared (REG[0A04h] bit 4 = 1b). Any subsequent AUX Window Frame Start Interrupt Status is valid. bit 3 MAIN Window Frame Start Interrupt Status This bit indicates the status of the MAIN Window Frame Start Interrupt which occurs when the Blending Engine has started processing a new MAIN window frame and has latched the width and virtual width registers. This interrupt can be used to prevent the “tearing effect” when programming new width/virtual width values. It can also be used by software to control frame double-buffering. This interrupt can be configured to cause a Host interrupt signal (see REG[0A0Ah] bit 3) or a C33PE interrupt signal (see REG[0A12h] bit 3). When this bit = 0b, a MAIN Window Frame Start Interrupt has not occurred. When this bit = 1b, a MAIN Window Frame Start Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 2 Warp Logic Frame Buffer Switch Interrupt Status This bit indicates the status of the Warp Logic Frame Buffer Switch Interrupt which occurs when the Warp Logic switches from reading one frame buffer to the other frame buffer. This interrupt can be configured to cause a Host interrupt signal (see REG[0A0Ah] bit 2) or a C33PE interrupt signal (see REG[0A12h] bit 2). When this bit = 0b, a Warp Frame Buffer Switch Interrupt has not occurred. When this bit = 1b, a Warp Frame Buffer Switch Interrupt has occurred. To clear this status bit, write a 1b to this bit. Hardware Functional Specification Rev. 1.7 EPSON 301 Chapter 10 Registers bit 1 S1D13515/S2D13515 Warp Logic Luminance Table Interrupt Status This bit indicates the status of the Warp Logic Luminance Table Interrupt which occurs when the Warp Logic starts using a new luminance table address. It is used by software when updating the Warp Logic Luminance Table SDRAM Start Address registers (REG[0454h] ~ REG[0457h]). When this interrupt occurs, it means software can write the next luminance table start address value to the register. Each time software writes to the start address registers, an internal “start address written” bit inside the Warp Logic is set to indicate to the hardware that a new value has been written. Whenever the Warp Logic finishes processing a frame and starts a new frame, it latches the start address and sets this interrupt bit if its internal “start address written” bit is set. If the “start address written” bit is not set, no interrupt is generated. The “start address written” bit is automatically cleared whenever the start address is latched. This interrupt can be configured to cause a Host interrupt signal (see REG[0A0Ah] bit 1) or a C33PE interrupt signal (see REG[0A12h] bit 1). When this bit = 0b, a Warp Logic Luminance Table Interrupt has not occurred. When this bit = 1b, a Warp Logic Luminance Table Interrupt has occurred. To clear this status bit, write a 1b to this bit. bit 0 Warp Logic Offset Table Interrupt Status This bit indicates the status of the Warp Logic Offset Table Interrupt which occurs when the Warp Logic starts using a new offset table address. It is used by software when updated the Warp Logic Offset Table SDRAM Start Address registers (REG[0444h] ~ REG[0447h]). When this interrupt occurs, it means software can write the next offset table start address value to the register. Each time software writes to the start address registers, an internal “start address written” bit inside the Warp Logic is set to indicate to the hardware that a new value has been written. Whenever the Warp finishes processing a frame and starts a new frame, it latches the start address and sets this interrupt bit if its internal “start address written” bit is set. If the “start address written” bit is not set, no interrupt is generated. The “start address written” bit is automatically cleared whenever the start address is latched. This interrupt can be configured to cause a Host interrupt signal (see REG[0A0Ah] bit 0) or a C33PE interrupt signal (see REG[0A12h] bit 0). When this bit = 0b, a Warp Logic Offset Table Interrupt has not occurred. When this bit = 1b, a Warp Logic Offset Table Interrupt has occurred. To clear this status bit, write a 1b to this bit. 302 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0A06h] Host Interrupt Enable Register 0 Default = 00h Read/Write Sprite Interrupt Enable I2S DAC Interrupt Enable SDRAM Read/Write Buffer Interrupt Enable n/a I2S DAC DMA Interrupt Enable Watchdog Timer Interrupt Enable Host LCD2 Interrupt Enable Host LCD1 Interrupt Enable 7 6 5 4 3 2 1 0 Note The Host Interrupt Enable bit (see REG[0A0Ch] bit 2) is the master Host interrupt control. If REG[0A0Ch] bit 2 = 0b, an interrupt will not be sent to the Host regardless of the individual interrupt settings in this register. bit 7 Sprite Interrupt Enable This bit controls whether a Sprite Interrupt can cause a Host interrupt signal. The status of the Sprite Interrupt is indicated by the Sprite Interrupt Status bit, REG[0A00h] bit 7. When this bit = 0b, a Sprite Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Sprite Interrupt can cause a Host interrupt signal. bit 6 I2S DAC Interrupt Enable This bit controls whether an I2S DAC Interrupt can cause a Host interrupt signal. The status of the I2S DAC Interrupt is indicated by the I2S DAC Interrupt Status bit, REG[0A00h] bit 6. When this bit = 0b, an I2S DAC Interrupt cannot cause a Host interrupt signal. When this bit = 1b, an I2S DAC Interrupt can cause a Host interrupt signal. bit 5 SDRAM Read/Write Buffer Interrupt Enable This bit controls whether a SDRAM Read/Write Buffer Interrupt can cause a Host interrupt signal. The status of the SDRAM Read/Write Buffer Interrupt is indicated by the SDRAM Read/Write Buffer Interrupt Status bit, REG[0A00h] bit 5. When this bit = 0b, a SDRAM Read/Write Buffer Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a SDRAM Read/Write Buffer Interrupt can cause a Host interrupt signal. bit 3 I2S DAC DMA Interrupt Enable This bit controls whether an I2S DAC DMA Interrupt can cause a Host interrupt signal. The status of the I2S DAC DMA Interrupt is indicated by the I2S DAC DMA Interrupt Status bit, REG[0A00h] bit 3. When this bit = 0b, an I2S DAC DMA Interrupt cannot cause a Host interrupt signal. When this bit = 1b, an I2S DAC DMA Interrupt can cause a Host interrupt signal. bit 2 Watchdog Timer Interrupt Enable This bit controls whether a Watchdog Timer Interrupt can cause a Host interrupt signal. The status of the Watchdog Timer Interrupt is indicated by the Watchdog Timer Interrupt Status bit, REG[0A00h] bit 2. When this bit = 0b, a Watchdog Timer Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Watchdog Timer Interrupt can cause a Host interrupt signal. bit 1 Host LCD2 Interrupt Enable This bit controls whether a LCD2 Interrupt can cause a Host interrupt signal. The status of the LCD2 Interrupt is indicated by the LCD2 Interrupt Status bit, REG[0A00h] bit 1. When this bit = 0b, a LCD2 Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a LCD2 Interrupt can cause a Host interrupt signal. Hardware Functional Specification Rev. 1.7 EPSON 303 Chapter 10 Registers S1D13515/S2D13515 bit 0 Host LCD1 Interrupt Enable This bit controls whether a LCD1 Interrupt can cause a Host interrupt signal. The status of the LCD1 Interrupt is indicated by the LCD1 Interrupt Status bit, REG[0A00h] bit 0. When this bit = 0b, a LCD1 Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a LCD1 Interrupt can cause a Host interrupt signal. REG[0A08h] Host Interrupt Enable Register 1 Default = 80h Read/Write Manual C33PE to Host Interrupt Enable Reserved Reserved Keypad Interrupt Enable Host Timer 1 Interrupt Enable Host Timer 0 Interrupt Enable Host DMA Channel 1 Transfer Done Interrupt Enable 7 6 5 4 3 2 1 Host DMA Channel 0 Transfer Done Interrupt Enable 0 Note The Host Interrupt Enable bit (see REG[0A0Ch] bit 2) is the master Host interrupt control. If REG[0A0Ch] bit 2 = 0b, an interrupt will not be sent to the Host regardless of the individual interrupt settings in this register. bit 7 Manual C33PE to Host Interrupt Enable This bit controls whether a Manual C33PE to Host Interrupt can cause a Host interrupt signal. The status of the Manual C33PE to Host Interrupt is indicated by the Manual C33PE to Host Interrupt Status bit, REG[0A02h] bit 7. When this bit = 0b, a Manual C33PE to Host Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Manual C33PE to Host Interrupt can cause a Host interrupt signal. bit 6 Reserved The default value for this bit is 0b. bit 5 Reserved The default value for this bit is 0b. 304 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 bit 4 Chapter 10 Registers Keypad Interrupt Enable This bit controls whether a Keypad Interrupt can cause a Host interrupt signal. The status of the Keypad Interrupt is indicated by the Keypad Interrupt Status bit, REG[0A02h] bit 4. When this bit = 0b, a Keypad Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Keypad Interrupt can cause a Host interrupt signal. Note After enabling the keypad (REG[01C0h] bit 0 = 1b), all interrupts in REG[01C4h] ~ REG[01C7h] should be cleared before enabling the Keypad Host Interrupt. bit 3 Host Timer 1 Interrupt Enable This bit controls whether a Host Timer 1 Interrupt can cause a Host interrupt signal. The status of the Host Timer 1 Interrupt is indicated by the Host Timer 1 Interrupt Status bit, REG[0A02h] bit 3. When this bit = 0b, a Host Timer 1 Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Host Timer 1 Interrupt can cause a Host interrupt signal. bit 2 Host Timer 0 Interrupt Enable This bit controls whether a Host Timer 0 Interrupt can cause a Host interrupt signal. The status of the Host Timer 0 Interrupt is indicated by the Host Timer 0 Interrupt Status bit, REG[0A02h] bit 2. When this bit = 0b, a Host Timer 0 Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Host Timer 0 Interrupt can cause a Host interrupt signal. bit 1 Host DMA Channel 1 Transfer Done Interrupt Enable This bit controls whether a Host DMA Channel 1 Transfer Done Interrupt can cause a Host interrupt signal. The status of the Host DMA Channel 1 Transfer Done Interrupt is indicated by the Host DMA Channel 1 Transfer Done Interrupt Status bit, REG[0A02h] bit 1. When this bit = 0b, a Host DMA Channel 1 Transfer Done Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Host DMA Channel 1 Transfer Done Interrupt can cause a Host interrupt signal. bit 0 Host DMA Channel 0 Transfer Done Interrupt Enable This bit controls whether a Host DMA Channel 0 Transfer Done Interrupt can cause a Host interrupt signal. The status of the Host DMA Channel 0 Transfer Done Interrupt is indicated by the Host DMA Channel 0 Transfer Done Interrupt Status bit, REG[0A02h] bit 0. When this bit = 0b, a Host DMA Channel 0 Transfer Done Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Host DMA Channel 0 Transfer Done Interrupt can cause a Host interrupt signal. Hardware Functional Specification Rev. 1.7 EPSON 305 Chapter 10 Registers S1D13515/S2D13515 REG[0A0Ah] Host Interrupt Enable Register 2 Default = 00h Read/Write n/a Image Fetcher Frame Start Interrupt Enable OSD Window Frame Start Interrupt Enable AUX Window Frame Start Interrupt Enable MAIN Window Frame Start Interrupt Enable Warp Logic Frame Buffer Switch Interrupt Enable Warp Logic Luminance Table Interrupt Enable Warp Logic Offset Table Interrupt Enable 7 6 5 4 3 2 1 0 Note The Host Interrupt Enable bit (see REG[0A0Ch] bit 2) is the master Host interrupt control. If REG[0A0Ch] bit 2 = 0b, an interrupt will not be sent to the Host regardless of the individual interrupt settings in this register. bit 6 Image Fetcher Frame Start Interrupt Enable This bit controls whether an Image Fetcher Frame Start Interrupt can cause a Host interrupt signal. The status of the Image Fetcher Frame Start Interrupt is indicated by the Image Fetcher Frame Start Interrupt Status bit, REG[0A04h] bit 6. When this bit = 0b, an Image Fetcher Frame Start Interrupt cannot cause a Host interrupt signal. When this bit = 1b, an Image Fetcher Frame Start Interrupt can cause a Host interrupt signal. bit 5 OSD Window Frame Start Interrupt Enable This bit controls whether an OSD Window Frame Start Interrupt can cause a Host interrupt signal. The status of the OSD Window Frame Start Interrupt is indicated by the OSD Window Frame Start Interrupt Status bit, REG[0A04h] bit 5. When this bit = 0b, an OSD Window Frame Start Interrupt cannot cause a Host interrupt signal. When this bit = 1b, an OSD Window Frame Start Interrupt can cause a Host interrupt signal. bit 4 AUX Window Frame Start Interrupt Enable This bit controls whether an AUX Window Frame Start Interrupt can cause a Host interrupt signal. The status of the AUX Window Frame Start Interrupt is indicated by the AUX Window Frame Start Interrupt Status bit, REG[0A04h] bit 4. When this bit = 0b, an AUX Window Frame Start Interrupt cannot cause a Host interrupt signal. When this bit = 1b, an AUX Window Frame Start Interrupt can cause a Host interrupt signal. bit 3 MAIN Window Frame Start Interrupt Enable This bit controls whether a MAIN Window Frame Start Interrupt can cause a Host interrupt signal. The status of the MAIN Window Frame Start Interrupt is indicated by the MAIN Window Frame Start Interrupt Status bit, REG[0A04h] bit 3. When this bit = 0b, a MAIN Window Frame Start Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a MAIN Window Frame Start Interrupt can cause a Host interrupt signal. 306 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 2 Warp Logic Frame Buffer Switch Interrupt Enable This bit controls whether a Warp Logic Frame Buffer Switch Interrupt can cause a Host interrupt signal. The status of the Warp Logic Frame Buffer Switch Interrupt is indicated by the Warp Logic Frame Buffer Switch Interrupt Status bit, REG[0A04h] bit 2. When this bit = 0b, a Warp Logic Frame Buffer Switch Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Warp Logic Frame Buffer Switch Interrupt can cause a Host interrupt signal. bit 1 Warp Logic Luminance Table Interrupt Enable This bit controls whether a Warp Logic Luminance Table Interrupt can cause a Host interrupt signal. The status of the Warp Logic Luminance Table Interrupt is indicated by the Warp Logic Luminance Table Interrupt Status bit, REG[0A04h] bit 1. When this bit = 0b, a Warp Logic Luminance Table Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Warp Logic Luminance Table Interrupt can cause a Host interrupt signal. bit 0 Warp Logic Offset Table Interrupt Enable This bit controls whether a Warp Logic Offset Table Interrupt can cause a Host interrupt signal. The status of the Warp Logic Offset Table Interrupt is indicated by the Warp Logic Offset Table Interrupt Status bit, REG[0A04h] bit 0. When this bit = 0b, a Warp Logic Offset Table Interrupt cannot cause a Host interrupt signal. When this bit = 1b, a Warp Logic Offset Table Interrupt can cause a Host interrupt signal. REG[0A0Ch] Host Interrupt Control Register Default = 04h n/a Host Interrupt Pin Tri-state Enable 7 6 Read/Write n/a Host Interrupt Pin Polarity n/a Host Interrupt Enable 5 4 3 2 n/a 1 0 bit 6 Host Interrupt Pin Tri-state Enable When this bit = 0b, the INT pin is driven based on the configuration of the Host Interrupt Pin Polarity bit, REG[0A0Ch] bit 4. When this bit = 1b, the INT pin is active low and is high impedance (Hi-Z) when no interrupt has occurred. bit 4 Host Interrupt Pin Polarity When REG[0A0Ch] bit 6 = 0b, this bit controls the polarity of the Host interrupt pin, INT. When this bit = 0b, the INT pin is active high when a Host interrupt is triggered. When this bit = 1b, the INT pin is active low when a Host interrupt is triggered. bit 2 Host Interrupt Enable This bit is the Host Interrupt master control. When this bit = 0b, the interrupt status bits in REG[0A00h] ~ REG[0A04h] cannot cause a Host interrupt (INT pin is disabled). When this bit = 1b, the interrupt status bits in REG[0A00h] ~ REG[0A04h] can cause a Host interrupt (INT pin is enabled) when the corresponding interrupt enable bit is set (see REG[0A06h] ~ REG[0A0Ah]. Hardware Functional Specification Rev. 1.7 EPSON 307 Chapter 10 Registers S1D13515/S2D13515 REG[0A0Eh] through REG[0A46h] REG[0A0Eh] through REG[0A46h] are typically used by the C33PE and are not accessed by the Host. REG[0A0Eh] C33PE Device Interrupt Enable Register 0 Default = 00h C33PE Sprite Interrupt Enable C33PE I2S DAC Interrupt Enable C33PE SDRAM Read/Write Buffer Interrupt Enable 7 6 5 Read/Write n/a 4 3 2 C33PE LCD2 Interrupt Enable C33PE LCD1 Interrupt Enable 1 0 Note C33PE Interrupt Enable bit 0 must be set (REG[0A42h] bit 0 = 1b) or an interrupt will not be sent to the C33PE regardless of the individual interrupt settings in this register. bit 7 C33PE Sprite Interrupt Enable This bit controls whether a Sprite Interrupt can cause a C33PE interrupt signal. The status of the Sprite Interrupt is indicated by the Sprite Interrupt Status bit, REG[0A00h] bit 7. When this bit = 0b, a Sprite Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a Sprite Interrupt can cause a C33PE interrupt signal. bit 6 C33PE I2S DAC Interrupt Enable This bit controls whether an I2S DAC Interrupt can cause a C33PE interrupt signal. The status of the I2S DAC Interrupt is indicated by the I2S DAC Interrupt Status bit, REG[0A00h] bit 6. When this bit = 0b, an I2S DAC Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, an I2S DAC Interrupt can cause a C33PE interrupt signal. bit 5 C33PE SDRAM Read/Write Buffer Interrupt Enable This bit controls whether a SDRAM Read/Write Buffer Interrupt can cause a C33PE interrupt signal. The status of the SDRAM Read/Write Buffer Interrupt is indicated by the SDRAM Read/Write Buffer Interrupt Status bit, REG[0A00h] bit 5. When this bit = 0b, a SDRAM Read/Write Buffer Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a SDRAM Read/Write Buffer Interrupt can cause a C33PE interrupt signal. bit 1 C33PE LCD2 Interrupt Enable This bit controls whether a LCD2 Interrupt can cause a C33PE interrupt signal. The status of the LCD2 Interrupt is indicated by the LCD2 Interrupt Status bit, REG[0A00h] bit 1. When this bit = 0b, the LCD2 Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, the LCD2 Interrupt can cause a C33PE interrupt signal. bit 0 C33PE LCD1 Interrupt Enable This bit controls whether a LCD1 Interrupt can cause a C33PE interrupt signal. The status of the LCD1 Interrupt is indicated by the LCD1 Interrupt Status bit, REG[0A00h] bit 0. When this bit = 0b, the LCD1 Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, the LCD1 Interrupt can cause a C33PE interrupt signal. 308 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0A10h] C33PE Device Interrupt Enable Register 1 Default = 00h Read/Write n/a Reserved Reserved C33PE Keypad Interrupt Enable C33PE Timer 1 Interrupt Enable C33PE Timer 0 Interrupt Enable C33PE DMA Channel 1 Transfer Done Interrupt Enable C33PE DMA Channel 0 Transfer Done Interrupt Enable 7 6 5 4 3 2 1 0 Note C33PE Interrupt Enable bit 0 must be set (REG[0A42h] bit 0 = 1b) or an interrupt will not be sent to the C33PE regardless of the individual interrupt settings in this register. bit 6 Reserved The default value for this bit is 0b. bit 5 Reserved The default value for this bit is 0b. bit 4 C33PE Keypad Interrupt Enable This bit controls whether a Keypad Interrupt can cause a C33PE interrupt signal. The status of the Keypad Interrupt is indicated by the Keypad Interrupt Status bit, REG[0A02h] bit 4. When this bit = 0b, a Keypad Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a Keypad Interrupt can cause a C33PE interrupt signal. bit 3 C33PE Timer 1 Interrupt Enable This bit controls whether a Timer 1 Interrupt can cause a C33PE interrupt signal. The status of the Timer 1 Interrupt is indicated by the Timer 1 Interrupt Status bit, REG[0A02h] bit 3. When this bit = 0b, a Timer 1 Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a Timer 1 Interrupt can cause a C33PE interrupt signal. bit 2 C33PE Timer 0 Interrupt Enable This bit controls whether a Timer 0 Interrupt can cause a C33PE interrupt signal. The status of the Timer 0 Interrupt is indicated by the Timer 0 Interrupt Status bit, REG[0A02h] bit 2. When this bit = 0b, a Timer 0 Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a Timer 0 Interrupt can cause a C33PE interrupt signal. bit 1 C33PE DMA Channel 1 Transfer Done Interrupt Enable This bit controls whether a DMA Channel 1 Transfer Done Interrupt can cause a C33PE interrupt signal. The status of the DMA Channel 1 Transfer Done Interrupt is indicated by the DMA Channel 1 Transfer Done Interrupt Status bit, REG[0A02h] bit 1. When this bit = 0b, a DMA Channel 1 Transfer Done Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a DMA Channel 1 Transfer Done Interrupt can cause a C33PE interrupt signal. Hardware Functional Specification Rev. 1.7 EPSON 309 Chapter 10 Registers S1D13515/S2D13515 bit 0 C33PE DMA Channel 0 Transfer Done Interrupt Enable This bit controls whether a DMA Channel 0 Transfer Done Interrupt can cause a C33PE interrupt signal. The status of the DMA Channel 0 Transfer Done Interrupt is indicated by the DMA Channel 0 Transfer Done Interrupt Status bit, REG[0A02h] bit 0. When this bit = 0b, a DMA Channel 0 Transfer Done Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a DMA Channel 0 Transfer Done Interrupt can cause a C33PE interrupt signal. REG[0A12h] C33PE Device Interrupt Enable Register 2 Default = 00h Read/Write n/a C33PE Image Fetcher Frame Start Interrupt Enable C33PE OSD Window Frame Start Interrupt Enable C33PE AUX Window Frame Start Interrupt Enable C33PE MAIN Window Frame Start Interrupt Enable C33PE Warp Logic Frame Buffer Switch Interrupt Enable C33PE Warp Logic Luminance Table Interrupt Enable C33PE Warp Logic Offset Table Interrupt Enable 7 6 5 4 3 2 1 0 Note C33PE Interrupt Enable bit 0 must be set (REG[0A42h] bit 0 = 1b) or an interrupt will not be sent to the C33PE regardless of the individual interrupt settings in this register. bit 6 C33PE Image Fetcher Frame Start Interrupt Enable This bit controls whether an Image Fetcher Frame Start Interrupt can cause a C33PE interrupt signal. The status of the Image Fetcher Frame Start Interrupt is indicated by the Image Fetcher Frame Start Interrupt Status bit, REG[0A04h] bit 6. When this bit = 0b, an Image Fetcher Frame Start Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, an Image Fetcher Frame Start Interrupt can cause a C33PE interrupt signal. bit 5 C33PE OSD Window Frame Start Interrupt Enable This bit controls whether an OSD Window Frame Start Interrupt can cause a C33PE interrupt signal. The status of the OSD Window Frame Start Interrupt is indicated by the OSD Window Frame Start Interrupt Status bit, REG[0A04h] bit 5. When this bit = 0b, an OSD Window Frame Start Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, an OSD Window Frame Start Interrupt can cause a C33PE interrupt signal. bit 4 C33PE AUX Window Frame Start Interrupt Enable This bit controls whether an AUX Window Frame Start Interrupt can cause a C33PE interrupt signal. The status of the AUX Window Frame Start Interrupt is indicated by the AUX Window Frame Start Interrupt Status bit, REG[0A04h] bit 4. When this bit = 0b, an AUX Window Frame Start Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, an AUX Window Frame Start Interrupt can cause a C33PE interrupt signal. 310 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 3 C33PE MAIN Window Frame Start Interrupt Enable This bit controls whether a MAIN Window Frame Start Interrupt can cause a C33PE interrupt signal. The status of the MAIN Window Frame Start Interrupt is indicated by the MAIN Window Frame Start Interrupt Status bit, REG[0A04h] bit 3. When this bit = 0b, a MAIN Window Frame Start Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a MAIN Window Frame Start Interrupt can cause a C33PE interrupt signal. bit 2 C33PE Warp Logic Frame Buffer Switch Interrupt Enable This bit controls whether a Warp Logic Frame Buffer Switch Interrupt can cause a C33PE interrupt signal. The status of the Warp Logic Frame Buffer Switch Interrupt is indicated by the Warp Logic Frame Buffer Switch Interrupt Status bit, REG[0A04h] bit 2. When this bit = 0b, a Warp Logic Frame Buffer Switch Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a Warp Logic Frame Buffer Switch Interrupt can cause a C33PE interrupt signal. bit 1 C33PE Warp Logic Luminance Table Interrupt Enable This bit controls whether a Warp Logic Luminance Table Interrupt can cause a C33PE interrupt signal. The status of the Warp Logic Luminance Table Interrupt is indicated by the Warp Logic Luminance Table Interrupt Status bit, REG[0A04h] bit 1. When this bit = 0b, a Warp Logic Luminance Table Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a Warp Logic Luminance Table Interrupt can cause a C33PE interrupt signal. bit 0 C33PE Warp Logic Offset Table Interrupt Enable This bit controls whether a Warp Logic Offset Table Interrupt can cause a C33PE interrupt signal. The status of the Warp Logic Offset Table Interrupt is indicated by the Warp Logic Offset Table Interrupt Status bit, REG[0A04h] bit 0. When this bit = 0b, a Warp Logic Offset Table Interrupt cannot cause a C33PE interrupt signal. When this bit = 1b, a Warp Logic Offset Table Interrupt can cause a C33PE interrupt signal. REG[0A20h] C33PE Interrupt 0 Control Register 0 Default = 10h Read/Write C33PE Interrupt 0 Vector Number bits 7-0 7 bits 7-0 6 5 4 3 2 1 0 C33PE Interrupt 0 Vector Number bits [7:0] These bits specify the vector number for C33PE interrupt 0. Hardware Functional Specification Rev. 1.7 EPSON 311 Chapter 10 Registers S1D13515/S2D13515 REG[0A21h] C33PE Interrupt 0 Control Register 1 Default = 0Fh Read/Write n/a 7 6 bits 3-0 C33PE Interrupt 0 Priority Level bits 3-0 5 4 3 2 1 0 C33PE Interrupt 0 Priority Level bits [3:0] These bits specify the priority level for C33PE interrupt 0. REG[0A22h] C33PE Interrupt 1 Control Register 0 Default = 11h Read/Write C33PE Interrupt 1 Vector Number bits 7-0 7 6 bits 7-0 5 4 3 2 1 C33PE Interrupt 1 Vector Number bits [7:0] These bits specify the vector number for C33PE interrupt 1. REG[0A23h] C33PE Interrupt 1 Control Register 1 Default = 01h Read/Write n/a 7 0 6 bits 3-0 C33PE Interrupt 1 Priority Level bits 3-0 5 4 3 2 1 0 C33PE Interrupt 1 Priority Level bits [3:0] These bits specify the priority level for C33PE interrupt 1. REG[0A24h] C33PE Interrupt 2 Control Register 0 Default = 12h Read/Write C33PE Interrupt 2 Vector Number bits 7-0 7 6 bits 7-0 5 4 3 2 1 C33PE Interrupt 2 Vector Number bits [7:0] These bits specify the vector number for C33PE interrupt 2. REG[0A25h] C33PE Interrupt 2 Control Register 1 Default = 01h Read/Write n/a 7 0 6 bits 3-0 C33PE Interrupt 2 Priority Level bits 3-0 5 4 3 2 1 0 C33PE Interrupt 2 Priority Level bits [3:0] These bits specify the priority level for C33PE interrupt 2. REG[0A26h] C33PE Interrupt 3 Control Register 0 Default = 13h Read/Write C33PE Interrupt 3 Vector Number bits 7-0 7 bits 7-0 312 6 5 4 3 2 1 0 C33PE Interrupt 3 Vector Number bits [7:0] These bits specify the vector number for C33PE interrupt 3. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0A27h] C33PE Interrupt 3 Control Register 1 Default = 01h Read/Write n/a 7 6 bits 3-0 C33PE Interrupt 3 Priority Level bits 3-0 5 4 3 2 1 0 C33PE Interrupt 3 Priority Level bits [3:0] These bits specify the priority level for C33PE interrupt 3. REG[0A28h] C33PE Interrupt 4 Control Register 0 Default = 14h Read/Write C33PE Interrupt 4 Vector Number bits 7-0 7 6 bits 7-0 5 4 3 2 1 C33PE Interrupt 4 Vector Number bits [7:0] These bits specify the vector number for C33PE interrupt 4. REG[0A29h] C33PE Interrupt 4 Control Register 1 Default = 01h Read/Write n/a 7 0 6 bits 3-0 C33PE Interrupt 4 Priority Level bits 3-0 5 4 3 2 1 0 C33PE Interrupt 4 Priority Level bits [3:0] These bits specify the priority level for C33PE interrupt 4. REG[0A2Ah] C33PE Interrupt 5 Control Register 0 Default = 15h Read/Write C33PE Interrupt 5 Vector Number bits 7-0 7 6 bits 7-0 5 4 3 2 1 C33PE Interrupt 5 Vector Number bits [7:0] These bits specify the vector number for C33PE interrupt 5. REG[0A2Bh] C33PE Interrupt 5 Control Register 1 Default = 0Fh Read/Write n/a 7 0 6 bits 3-0 C33PE Interrupt 5 Priority Level bits 3-0 5 4 3 2 1 0 C33PE Interrupt 5 Priority Level bits [3:0] These bits specify the priority level for C33PE interrupt 5. REG[0A2Ch] C33PE Interrupt 6 Control Register 0 Default = 16h Read/Write C33PE Interrupt 6 Vector Number bits 7-0 7 bits 7-0 6 5 4 3 2 1 0 C33PE Interrupt 6 Vector Number bits [7:0] These bits specify the vector number for C33PE interrupt 6. Hardware Functional Specification Rev. 1.7 EPSON 313 Chapter 10 Registers S1D13515/S2D13515 REG[0A2Dh] C33PE Interrupt 6 Control Register 1 Default = 0Dh Read/Write n/a 7 6 bits 3-0 C33PE Interrupt 6 Priority Level bits 3-0 5 4 3 2 1 0 C33PE Interrupt 6 Priority Level bits [3:0] These bits specify the priority level for C33PE interrupt 6. REG[0A2Eh] C33PE Interrupt 7 Control Register 0 Default = 17h Read/Write C33PE Interrupt 7 Vector Number bits 7-0 7 6 bits 7-0 5 4 3 2 1 C33PE Interrupt 7 Vector Number bits [7:0] These bits specify the vector number for C33PE interrupt 7. REG[0A2Fh] C33PE Interrupt 7 Control Register 1 Default = 0Ch Read/Write n/a 7 0 6 bits 3-0 C33PE Interrupt 7 Priority Level bits 3-0 5 4 3 2 1 0 C33PE Interrupt 7 Priority Level bits [3:0] These bits specify the priority level for C33PE interrupt 7. REG[0A40h] C33PE Manual Interrupt Trigger Register Default = 00h Write Only C33PE Manual Interrupt Trigger bits 7-0 7 bits 7-0 6 5 4 3 2 1 0 C33PE Manual Interrupt Trigger bits [7:0] (Write Only) These bits allow manual triggering of the corresponding C33PE interrupts. When each interrupt is triggered, the corresponding bit in REG[0A44h] will indicate a 1b showing the interrupt status until the interrupt is cleared. Only the interrupts enabled using REG[0A42h] will cause an interrupt request to the C33PE. Writing a 0b to this bit has no hardware effect. Writing a 1b to this bit manually triggers the corresponding interrupt. Note 1. C33PE Interrupt 0 is triggered by devices, which includes any of the enabled interrupts from REG[0A00h] ~ REG[0A04h]. These interrupts should be enabled specifically for the C33PE using REG[0A0Eh] ~ REG[0A12h]. 2. Interrupt 0 corresponds to the C33PE devices interrupt and cannot be controlled from this register. 314 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0A42h] C33PE Interrupt Enable Register Default = E1h Read/Write C33PE Interrupt Enable bits 7-0 7 6 bits 7-0 5 4 3 2 1 C33PE Interrupt Enable bits [7:0] These bits control the corresponding C33PE interrupts. The raw status of these interrupts is available in the C33PE Interrupt Status register, REG[0A44h]. When this bit = 0b, the corresponding interrupt is disabled. When this bit = 1b, the corresponding interrupt is enabled. REG[0A43h] C33PE NMI Interrupt Enable Register Default = 80h C33PE NMI Interrupt Enable 7 0 Read/Write n/a 6 bit 7 5 4 3 2 1 0 C33PE NMI Interrupt Enable This bit controls the C33PE NMI interrupt. When this bit = 0b, the NMI interrupt is not triggered. When this bit = 1b, the NMI interrupt is triggered when the Timer 0 Period (REG[0A88h] ~ REG[0A89h]) is exceeded. REG[0A44h] C33PE Interrupt Status Register Default = 00h Read/Write C33PE Interrupt Status bits 7-0 7 bits 7-0 6 5 4 3 2 1 0 C33PE Interrupt Status bits [7:0] These bits indicate the raw status of the corresponding C33PE interrupt. These bits are not masked by the corresponding bit in the C33PE Interrupt Enable register, REG[0A42h]. When this bit = 0b, the corresponding interrupt has not occurred. When this bit = 1b, the corresponding interrupt has occurred. To clear these interrupts (except interrupt 0, 2, and 3 which are read only), write a 1b to the corresponding status bit. Note Interrupt 0 corresponds to the C33PE devices interrupt and cannot be controlled from this register. Interrupt 2 corresponds to the Watchdog Interrupt which can be read and cleared in Interrupt Status Register 0 (REG[0A00h]) bit 2. Interrupt 3 corresponds to the I2S DAC DMA interrupt which can be read and cleared in the I2S DMA Status Register (REG[0154h] bit 3). Hardware Functional Specification Rev. 1.7 EPSON 315 Chapter 10 Registers S1D13515/S2D13515 REG[0A46h] C33 to Host Interrupt Trigger Register Default = 00h Write Only Manual C33PE to Host Interrupt Trigger n/a 7 bit 0 316 6 5 4 3 2 1 0 Manual C33PE to Host Interrupt Trigger (Write Only) This bit is the trigger for the Manual C33PE to Host Interrupt. This interrupt is used by the C33PE to signal the Host. The status of the Manual C33PE to Host Interrupt is indicated by the Manual C33PE to Host Interrupt Status bit, REG[0A02h] bit 7. This interrupt will only cause a Host interrupt signal if REG[0A08h] bit 7 is set to 1b. Writing a 0b to this bit has no hardware effect. Writing a 1b to this bit triggers a Manual C33PE to Host Interrupt. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.15 Timer Configuration Registers REG[0A80h] Timer Clock Configuration Register 0 Default = 24h Read/Write Timer Clock Divide Select bits 7-0 7 6 5 4 3 2 1 REG[0A81h] Timer Clock Configuration Register 1 Default = 00h Read/Write n/a 7 6 REG[0A81h] bits 3-0 REG[0A80h] bits 7-0 0 Timer Clock Divide Select bits 11-8 5 4 3 2 1 0 Timer Clock Divide Select bits [11:0] These bits determine the divide ratio for the Timer Clock (LSCLK) which is used for Timer 0, Timer 1, and the Watchdog Timer. The Timer Clock is derived from the input clock INCLK1 which is sourced from either CLKI or OSCI depending on the setting of CNF0. For further details on the clock structure, see Section Chapter 9, “Clocks” on page 128. The divide ratio should be set appropriately for use by the timers according to the following formula. Time Clock Divide Ratio = 1: (REG[0A81h] bits 3-0, REG[0A80h] bits 7-0) + 1 REG[0A84h] Timer Control Register Default = 01h Read/Write n/a 7 6 5 4 Watchdog Time-out Action Watchdog Timer Enable Timer 1 Enable Timer 0 Enable 3 2 1 0 bit 3 Watchdog Time-out Action These bit only has an effect when the Watchdog Timer is enabled, REG[0A84h] bit 2 = 1b. This bit determines what happens when a Watchdog Timer time-out occurs. A time-out occurs when the Watchdog Timer Period is reached (see REG[0A86h] ~ REG[0A87h]). To reset the counter and prevent a time-out from occurring, periodically write the value of 2371h to the Watchdog Timer Clear registers, REG[0A8Ch] ~ REG[0A8Dh]. When this bit = 0b, a watchdog timer time-out generates an IRQ2 interrupt. When this bit = 1b, the watchdog timer time-out generates a system reset. bit 2 Watchdog Timer Enable This bit controls the Watchdog Timer. The Watchdog Timer Period bits (REG[0A86h] ~ REG[0A87h]) must be set before the timer is enabled. When this bit = 0b, the Watchdog Timer is disabled. (default) When this bit = 1b, the Watchdog Timer is enabled. bit 1 Timer 1 Enable This bit controls Timer 1. The Timer 1 Period bits (REG[0A8Ah] bits 7-0) must be set before the timer is enabled. The status of the timer is indicated by the Timer 1 Interrupt Status bit, REG[0A02h] bit 3. When this bit = 0b, Timer 1 is disabled. (default) When this bit = 1b, Timer 1 is enabled. Hardware Functional Specification Rev. 1.7 EPSON 317 Chapter 10 Registers S1D13515/S2D13515 bit 0 Timer 0 Enable This bit controls Timer 0 which can be used to generate a C33PE NMI interrupt (see REG[0A43h]). The Timer 0 Period bits (REG[0A88h] ~ REG[0A89h]) must be set before the timer is enabled. The status of the timer is indicated by the Timer 0 Interrupt Status bit, REG[0A02h] bit 2. When this bit = 0b, the Timer 0 is disabled. (default) When this bit = 1b, the Timer 0 is enabled. REG[0A86h] Watchdog Timer Period Register 0 Default = 00h Read/Write Watchdog Timer Period bits 7-0 7 6 5 4 3 2 1 REG[0A87h] Watchdog Timer Period Register 1 Default = 00h 0 Read/Write Watchdog Timer Period bits 15-8 7 REG[0A87h] bits 7-0 REG[0A86h] bits 7-0 6 5 4 3 2 1 0 Watchdog Timer Period bits [15:0] These bits only have an effect when the Watchdog Timer is enabled, REG[0A84h] bit 2 = 1b. These bits determine the period, in number of Timer Clocks (LSCLK), that the timer counts before triggering the Watchdog Time-out Action (see REG[0A84h] bit 3). To reset the counter and prevent a time-out from occurring, periodically write the value of 2371h to the Watchdog Timer Clear registers, REG[0A8Ch] ~ REG[0A8Dh]. The Watchdog Timer period is defined by the following formulas. Initial Timer Period max. = ((REG[0A87h] bits 7-0, REG[0A86h] bits 7-0) - 1) x LSCLKs Initial Timer Period min. = ((REG[0A87h] bits 7-0, REG[0A86h] bits 7-0) - 2) x LSCLKs Subsequent Timer Period = ((REG[0A87h] bits 7-0, REG[0A86h] bits 7-0) - 1) x LSCLKs Note The Watchdog Timer Period bits must not be set to 0000h as this value causes a delay of 65536 LSCLKs. 318 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0A88h] Timer 0 Period Register 0 Default = E8h Read/Write Timer 0 Period bits 7-0 7 6 5 4 3 2 1 REG[0A89h] Timer 0 Period Register 1 Default = 03h Read/Write n/a 7 6 REG[0A89h] bits 3-0 REG[0A88h] bits 7-0 0 Timer 0 Period bits 11-8 5 4 3 2 1 0 Timer 0 Period bits [11:0] These bits only have an effect when the Timer 0 is enabled, REG[0A84h] bit 0 = 1b. These bits determine the period, in number of Timer Clocks (LSCLK), that the timer counts before triggering the Timer 0 Interrupt Status bit, REG[0A02h] bit 2. The Timer 0 period is defined by the following formulas. Initial Timer Period max. = ((REG[0A89h] bits 3-0, REG[0A88h] bits 7-0) - 1) x LSCLKs Initial Timer Period min. = ((REG[0A89h] bits 3-0, REG[0A88h] bits 7-0) - 2) x LSCLKs Subsequent Timer Period = ((REG[0A89h] bits 3-0, REG[0A88h] bits 7-0) - 1) x LSCLKs Note The Timer 0 Period bits must not be set to 000h as this value causes a delay of 8192 LSCLKs. REG[0A8Ah] Timer 1 Period Register Default = 00h Read/Write Timer 1 Period bits 7-0 7 bits 7-0 6 5 4 3 2 1 0 Timer 1 Period bits [7:0] These bits only have an effect when Timer 1 is enabled, REG[0A84h] bit 1 = 1b. These bits determine the period, in number of Timer Clocks (LSCLK), that the timer counts before triggering the Timer 1 Interrupt Status bit, REG[0A02h] bit 3. The Timer 1 period is defined by the following formulas. Initial Timer Period max. = (REG[0A8Ah] bits 7-0 - 1) x LSCLKs Initial Timer Period min. = (REG[0A8Ah] bits 7-0 - 2) x LSCLKs Subsequent Timer Period = (REG[0A8Ah] bits 7-0 - 1) x LSCLKs Note The Timer 1 Period bits must not be set to 00h as this value causes a delay of 8192 LSCLKs. Hardware Functional Specification Rev. 1.7 EPSON 319 Chapter 10 Registers S1D13515/S2D13515 REG[0A8Ch] Watchdog Timer Clear Register 0 Default = 00h Write Only Watchdog Timer Clear bits 7-0 7 6 5 4 3 2 1 REG[0A8Dh] Watchdog Timer Clear Register 1 Default = 00h 0 Write Only Watchdog Timer Clear bits 15-8 7 6 5 4 3 2 1 0 REG[0A8Dh] bits 7-0 REG[0A8Ch] bits 7-0 Watchdog Timer Clear bits [15:0] (Write Only) When the watchdog timer is enabled (REG[0A84h] bit 2 = 1b), software should periodically write these bits with the 16-bit value of 2371h which will restart the watchdog timer and prevent a time-out from occurring. 320 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.16 SPI Flash Memory Interface Registers REG[0B00h] SPI Flash Read Data Register Default =FFh Read Only SPI Flash Read Data bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 SPI Flash Read Data bits [7:0] (Read Only) These bits contain the 8-bit value read when a “dummy” write is written to the SPI Flash Memory interface. REG[0B02h] SPI Flash Write Data Register Default = 00h Write Only SPI Flash Write Data bits 7-0 7 6 bits 7-0 5 4 3 2 1 SPI Flash Write Data bits [7:0] (Write Only) These bits are the write data register for the SPI Flash Memory interface. When a value is written to this register, a serial output transfer of the specified value is initiated on the SPI Flash Memory interface. REG[0B03h] SPI Flash Data Control Register Default = 00h Read/Write SPI Flash Data Output Enable n/a 7 bit 0 0 6 5 4 3 2 1 0 SPI Flash Data Output Enable This bit controls data output for the SPI Flash Memory interface data line (SPIDIO pin). When this bit = 0b, the SPIDIO pin is high impedance allowing SPI Flash Memory reads when the SPI Flash Read Mode is set to 0b, REG[0B04h] bit 7 = 0b. When this bit = 1b, the SPIDIO pin is driven allowing SPI Flash Memory writes when the SPI Flash Read Mode is set to 0b, REG[0B04h] bit 7 = 0b. Hardware Functional Specification Rev. 1.7 EPSON 321 Chapter 10 Registers S1D13515/S2D13515 REG[0B04h] SPI Flash Control Register Default = 11h SPI Flash Read Mode Reserved 7 6 bit 7 Read/Write SPI Flash Clock Divide Select bits 2-0 5 4 SPI Flash Clock Phase Select SPI Flash Clock Polarity Select SPI Flash Enable 2 1 0 3 SPI Flash Read Mode This bit selects the mode for reading the SPI Flash Memory. When this bit = 0b, the SPI Flash Memory is read by firmware through the registers at REG[0B00h]. When this bit = 1b, the SPI Flash Memory is read by firmware at base address 2000_0000h. In this mode, the contents of the flash memory is read by the Serial Flash Read logic which handles serial reads and deserialization of the read data. This mode makes the serial flash memory device accessible like a memory-mapped parallel flash device. Note When this bit = 1b, writes to the SPI Flash Memory are not possible. bit 6 Reserved This bit is reserved and MUST be set to 1b. bits 5-3 SPI Flash Clock Divide Select bits [2:0] These bits select the divide ratio for the SPI Flash clock. The source for the SPI Flash clock is the external SDRAM clock. Table 10-52: SPI Flash Clock Divide Ratio Selection REG[0B04h] bits 5-3 SPI Flash Clock Divide Ratio REG[0B04h] bits 5-3 SPI Flash Clock Divide Ratio 000b 1:2 100b 1:6 001b 1:3 101b 1:7 010b 1:4 110b 1:8 011b 1:5 111b 1:9 Note For odd SPI clock divides the SPICLK output does not maintain 50/50 duty cycle. bit 2 322 SPI Flash Clock Phase Select This bit selects the SPI Flash clock phase. For a summary of the SPI Flash Memory clock phase and polarity settings, see Table 10-53 “SPI Flash Clock Phase and Polarity,” on page 323. EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 1 SPI Flash Clock Polarity Select (CPOL) This bit selects the SPI Flash clock polarity. The following table summarizes the SPI Flash clock polarity and phase settings. Table 10-53 : SPI Flash Clock Phase and Polarity REG[0B04h] bit 2 REG[0B04h] bit 1 0b 1b bit 0 Valid Data Clock Idling Status 0b Rising edge of SPI Flash Clock Low 1b Falling edge of SPI Flash Clock High 0b Falling edge of SPI Flash Clock Low 1b Rising edge of SPI Flash Clock High SPI Flash Enable This bit controls the SPI Flash Memory interface logic. When this bit = 0b, the SPI Flash Memory interface is disabled and the SPI Flash Read Port at 2000_0000h must not be accessed. When this bit = 1b, the SPI Flash Memory interface is enabled. REG[0B06h] SPI Flash Status Register Default = 04h Read Only n/a 7 6 5 4 SPI Flash Busy Flag SPI Flash Write Data Register Empty Flag SPI Flash Read Data Overrun Flag SPI Flash Read Data Ready Flag 3 2 1 0 bit 3 SPI Flash Busy Flag (Read Only) This bit indicates the state of the SPI Flash Memory interface. When this bit = 0b, the SPI Flash Memory interface is not busy. When this bit = 1b, the SPI Flash Memory interface is busy. bit 2 SPI Flash Write Data Register Empty Flag (Read Only) This bit indicates when the SPI Flash Write Data register is empty which occurs when data written to the register is latched for serialization/transmission. When this bit = 0b, the SPI Flash Write Data register is not empty. When this bit = 1b, the SPI Flash Write Data register is empty. (default) To clear this flag, write data to the SPI Flash Write Data register, REG[0B02h]. bit 1 SPI Flash Read Data Overrun Flag (Read Only) This bit indicates when new data is loaded into the SPI Flash Read Data register before the existing data has been read (REG[0B06h] bit 0 = 1b while the new data is loaded). In this this case, the old data is no longer available and must be re-read. When this bit = 0b, a SPI Flash Read Data overrun has not occurred. When this bit = 1b, an SPI Flash Read Data overrun has occurred. To clear this flag, read the SPI Flash Read Data register, REG[0B00h]. Hardware Functional Specification Rev. 1.7 EPSON 323 Chapter 10 Registers S1D13515/S2D13515 bit 0 SPI Flash Read Data Ready Flag (Read Only) This bit indicates when read data from the SPI Flash Memory is available (or ready) in the SPI Flash Read Data register, REG[0B00h]. When this bit = 0b, SPI Flash Memory read data is not ready. When this bit = 1b, SPI Flash Memory read data is ready. To clear this flag, read the SPI Flash Read Data register, REG[0B00h]. REG[0B0Ah] SPI Flash Chip Select Control Register Default = 00h Read/Write SPI Flash Chip Select Enable n/a 7 bit 0 6 5 4 3 2 1 0 SPI Flash Chip Select Enable This bit only has an effect when the SPI Flash Read Mode bit is set to 0b, REG[0B04h] bit 7 = 0b. This bit controls chip select (SPICS pin) for the SPI Flash Memory interface. When this bit = 0b, chip select is disabled. When this bit = 1b, chip select is enabled. Note The chip select output pin for the Serial Flash Memory interface is active low. Therefore, SPICS is high when this bit = 0b, and SPICS is low when this bit = 1b. 324 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers 10.4.17 Cache Control Register REG[0C00h] C33 Instruction Cache Control Register Default = 00h Read/Write n/a 7 6 5 4 3 2 Reserved C33 Instruction Cache Enable 1 0 bit 1 Reserved This bit must be set to 0b. bit 0 C33 Instruction Cache Enable This bit controls the C33 Instruction Cache. The C33 Instruction Cache can be enabled only when the C33 is enabled (REG[001Ch] bit 6 = 1b) and not in a reset state (REG[001Dh] bit 0 ≠ 1b). This bit can be read to determine whether the cache has been enabled or disabled after writing to this bit, however, enable/disable sequencing logic delays when the actual state of the cache is reflected in this bit. If this bit is written while the C33 is not running, the read back value of this bit will not change. When this bit = 0b, the C33 Instruction Cache is disabled. When this bit = 1b, the C33 Instruction Cache is enabled. Hardware Functional Specification Rev. 1.7 EPSON 325 Chapter 10 Registers S1D13515/S2D13515 10.4.18 Camera Interface Registers REG[0D00h] Camera1 Enable Register Default = 00h Camera1 Software Reset (WO) 7 Read/Write n/a 6 5 4 Reserved Reserved Camera1 Interface Enable 2 1 0 3 bit 7 Camera1 Software Reset (Write Only) This bit performs a software reset of the Camera1 logic and resets the Camera1 registers (REG[0D00h] ~ REG[0D35h]) to their default values. Writing a 0b to this bit has no effect. Writing a 1b to this bit initiates a Camera1 software reset. bit 2 Reserved This bit must be set to 0b. bit 1 Reserved This bit must be set to 0b. bit 0 Camera1 Interface Enable This bit enables the Camera1 interface logic. When this bit = 0b, the Camera1 interface is disabled. When this bit = 1b, the Camera1 interface is enabled. REG[0D02h] Camera1 Clock Configuration Register Default = 00h Camera1 Clock Output Disable 7 bit 7 Read/Write Camera1 Clock Divide Select bits 4-0 6 5 4 3 2 Reserved Camera1 Clock Polarity 1 0 Camera1 Clock Output Disable This bit controls the Camera1 clock (CM1CLKOUT). When this bit = 0b, the Camera1 clock is enabled. When this bit = 1b, the Camera1 clock is disabled. Note For SPI 2 Stream Mode, (see Section 5.4, “Configuration Pins” on page 32) when the Camera1 Interface is configured for RGB stream input mode, REG[0D02h] bit 7 should be set to 1b. bits 6-2 Camera1 Clock Divide Select bits [4:0] These bits specify the divide ratio used to generate the Camera1 Clock Output (CM1CLKOUT). The source of the clock is the system clock and the divide ratio is programmable using the following formula. Camera1 Clock Divide Ratio = (REG[0D02h] bits 6-2) + 1 bit 1 Reserved This bit must be set to 0b. 326 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers bit 0 Camera1 Clock Polarity This bit selects the Camera1 input clock (CM1CLKIN) polarity. When this bit = 0b, the Camera1 input signals are latched on the rising edge of the CM1CLKIN signal. (default) When this bit = 1b, the Camera1 input signals are latched on the falling edge of the CM1CLKIN signal. REG[0D04h] Camera1 Signal Polarity Register Default = 00h Read/Write n/a 7 6 5 4 Reserved CM1VREF Polarity CM1HREF Polarity CM1DATEN Polarity 3 2 1 0 bit 3 Reserved This bit must be set to 0b. bit 2 CM1VREF Polarity This bit selects the VSYNC signal polarity for Camera1. When this bit = 0b, the CM1VREF signal is active low. (default) When this bit = 1b, the CM1VREF signal is active high. bit 1 CM1HREF Polarity This bit selects the HSYNC signal polarity for Camera1. When this bit = 0b, the CM1HREF signal is active low. (default) When this bit = 1b, the CM1HREF signal is active high. bit 0 CM1DATEN Polarity This bit only has an effect when the Camera1 Use Data Enable bit is set to 1b, REG[0D06h] bit 7 = 1b. This bit selects the data enable signal polarity for Camera1. When this bit = 0b, the Camera1 data enable is active high. (default) When this bit = 1b, the Camera1 data enable is active low. REG[0D06h] Camera1 Configuration Register 0 Default = 00h Camera1 ITU-R BT.656 Enable n/a Camera1 YUV Offset Enable 7 6 5 bit 7 Read/Write Camera1 YUV Data Format bits 1-0 4 3 Camera1 Interface Mode bits 1-0 2 n/a 1 0 Camera1 ITU-R BT.656 Enable This bit controls the camera interface type for Camera1. When this bit = 0b, ITU-R BT.656 mode is disabled (normal camera). In this mode the hsync, vsync, clock, and data signals are independent input signals. (default) When this bit = 1b, ITU-R BT.656 mode is enabled. In this mode the hsync and vsync signal information is embedded in the data signals and the CM1VREF and CM1HREF input pins are ignored. Note When ITU-R BT656 mode is enabled (REG[0D06h] bit 7 = 1b), REG[0D32h] ~ REG[0D35h] have no effect and are ignored. Hardware Functional Specification Rev. 1.7 EPSON 327 Chapter 10 Registers S1D13515/S2D13515 bit 5 Camera1 YUV Offset Enable This bit controls whether a UV offset is applied to the incoming Camera1 data and must be configured based on the YUV data type of the camera (see also REG[0D1Eh] bit 4). Table 10-54 : Camera1 YUV Offset Selection bits 4-3 REG[0D06h] bit 5 YUV Data Type Data Range 1 (REG[0D1Eh] bit 4 = 0b) Data Range 2 (REG[0D1Eh] bit 4 = 1b) 0b Straight Binary 0 ≤ U ≤ 255 0 ≤ V ≤ 255 16 ≤ Cb ≤ 240 16 ≤ Cr ≤ 240 1b Offset Binary -128 ≤ U ≤ 127 -128 ≤ V ≤ 127 -112 ≤ Cb ≤ 112 -112 ≤ Cr ≤ 112 Camera1 YUV Data Format bits [1:0] When the Camera1 interface mode is set for 8-bit YUV 4:2:2 (REG[0D06h] bits 2-1 = 00b), these bits select the YUV data sequence order format for Camera1. Table 10-55: Camera1 YUV Data Format Selection bits 2-1 REG[0D06h] bits 4-3 8-bit YUV Data Format 00b (default) (1st) UYVY (last) 01b (1st) VYUY (last) 10b (1st) YUYV (last) 11b (1st) YVYU (last) Camera1 Interface Mode bits [1:0] These bits select the interface mode for Camera1. Table 10-56: Camera1 Interface Mode Selection REG[0D06h] bits 2-1 Camera Interface Mode 00b (default) 8-bit YUV 4:2:2 01b Reserved 10b 24-bit RGB 8:8:8 11b Reserved Note For SPI 2 Stream Mode, (see Section 5.4, “Configuration Pins” on page 32) when the Camera1 Interface is configured for RGB stream input mode, REG[0D02h] bit 7 should be set to 1b. 328 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0D07h] Camera1 Configuration Register 1 Default = 00h Read/Write Camera1 Use Data Enable n/a 7 6 bit 0 5 4 3 2 1 0 Camera1 Use Data Enable This bit controls Camera1 Data Enable which is typically used when 24-bit RGB streaming is selected, REG[0D06h] bits 2-1 = 10b. If Camera1 Data Enable is enabled, the polarity of the signal can be configured using the CM1DATEN Polarity bit, REG[0D04h] bit 0. The Camera1 signals are available on the Host Interface Pins (SPI 2-stream mode, see Section 5.4, “Configuration Pins” on page 32) when 24-bit RGB streaming is selected. For pin mapping details, see Section 5.5, “Host Interface Pin Mapping” on page 34. When this bit = 0b, Camera1 Data Enable is not used. When this bit = 0b, Camera1 Data Enable is used. REG[0D08h] Camera1 Input Frame Control Register Default = 00h Read/Write n/a Camera1 Frame Capture Start/Stop Camera1 Frame Event Select Camera1 Frame Event Enable Camera1 Frame Event Control 7 6 5 4 3 Reserved 2 1 0 bit 6 Camera1 Frame Capture Start/Stop This bit is used to start or stop frame capturing for Camera1. When this bit = 0b, Camera1 frame capturing is stopped after the current frame. When this bit = 1b, Camera1 frame capturing is started on the next frame. bit 5 Camera1 Frame Event Select This bit selects which edge of the frame causes the frame event. The frame event status is not indicated by the Camera1 Frame Event Status bit (REG[0D0Eh] bit 5) until it is triggered by the condition specified by the Camera1 Frame Event Control bit (REG[0D08h] bit 3). When this bit = 0b, the frame event is caused by the start of a frame. When this bit = 1b, the frame event is caused by the end of a frame. bit 4 Camera1 Frame Event Enable This bit controls whether the frame event can occur. If enabled, the status of the frame event is indicated by the Camera1 Frame Event Status bit (REG[0D0Eh] bit 5). When this bit = 0b, the frame event is disabled. When this bit = 1b, the frame event is enabled. bit 3 Camera1 Frame Event Control This bit determines what triggers the frame event. The frame event will occur at the next frame start/end after the trigger takes place. When this bit = 0b, the frame event is triggered by Camera1 VSYNC. When this bit = 1b, the frame event is triggered by a Camera1 Frame Capture Stop, REG[0D08h] bit 6 = 0b. bits 2-0 Reserved The default value for these bits is 000b. Hardware Functional Specification Rev. 1.7 EPSON 329 Chapter 10 Registers S1D13515/S2D13515 REG[0D09h] Camera1 Flag Clear Register Default = 00h Write Only n/a 7 6 5 4 Reserved Reserved Camera1 Frame Event Clear 2 1 0 3 bit 2 Reserved The default value of this bit is 0b. bit 1 Reserved The default value of this bit is 0b. bit 0 Camera1 Frame Event Clear (Write Only) This bit is used to clear the Camera1 Frame Event Status bit, REG[0D0Eh] bit 5. Writing a 0b to this bit has no effect. Writing a 1b to this bit clears the Camera1 Frame Event Status bit. REG[0D0Ah] Camera1 Input Horizontal Size Register 0 Default = 00h Read/Write Camera1 Input Horizontal Size bits 7-0 7 6 5 4 3 2 1 REG[0D0Bh] Camera1 Input Horizontal Size Register 1 Default = 00h Read/Write n/a 7 6 5 0 Camera1 Input Horizontal Size bits 10-8 4 3 2 1 0 REG[0D0Bh] bits 2-0 REG[0D0Ah] bits 7-0 Camera1 Input Horizontal Size bits [10:0] These bits specify the horizontal size of the Camera1 input image, in pixels. The input horizontal size is calculated as follows. For interlaced modes (see REG[0D30h] bits 1-0) when ITU-R BT.656 mode is enabled (REG[0D06h] bit 7 = 1b): Input horizontal size = HDP For interlaced modes when ITU-R BT.656 mode is disabled (REG[0D06h] bit 7 = 0b): Input horizontal size = HDP + HNDP For progressive mode (REG[0D30h] bits 1-0 = 00b): Input horizontal size = HDP 330 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0D0Ch] Camera1 Input Vertical Size Register 0 Default = 00h Read/Write Camera1 Input Vertical Size bits 7-0 7 6 5 4 3 2 1 REG[0D0Dh] Camera1 Input Vertical Size Register 1 Default = 00h Read/Write n/a 7 6 5 0 Camera1 Input Vertical Size bits 10-8 4 3 2 1 0 REG[0D0Dh] bits 2-0 REG[0D0Ch] bits 7-0 Camera1 Input Vertical Size bits [10:0] These bits specify the vertical size of the Camera1 input image, in pixels. The input vertical size is calculated as follows. For interlaced modes (see REG[0D30h] bits 1-0) when ITU-R BT.656 mode is enabled (REG[0D06h] bit 7 = 1b): Input vertical size = VDP For interlaced modes when ITU-R BT.656 mode is disabled (REG[0D06h] bit 7 = 0b): Input vertical size = VDP + VNDP For progressive mode (REG[0D30h] bits 1-0 = 00b): Input vertical size = VDP REG[0D0Eh] Camera1 Status Register Default = 0Xh n/a 7 bit 5 Read Only Camera1 Frame Event Status Camera1 Effective Capture Status Camera1 Effective Frame Status Camera1 Raw VSYNC Status Reserved Reserved 5 4 3 2 1 0 6 Camera1 Frame Event Status (Read Only) This bit indicates the status of the Camera1 Frame Event. The frame event is configured using the Camera1 Frame Event Select/Enable/Control bits (REG[0D08h] bits 5-3). When this bit = 0b, a frame event has not occurred. When this bit = 1b, a frame event has occurred. To clear this bit, write a 1b to REG[0D09h] bit 0. bit 4 Camera1 Effective Capture Status (Read Only) The camera input interface has a programmable frame sampling rate. Frame capture occurs at the effective rate which is selected by the Camera1 Frame Sampling Select bits, REG[0D08h] bits 2-0. This bit indicates if the Camera1 input interface is capturing a frame whether the frame is valid or not. When this bit = 0b, a frame is not being captured. When this bit = 1b, a frame is being captured. Hardware Functional Specification Rev. 1.7 EPSON 331 Chapter 10 Registers S1D13515/S2D13515 bit 3 Camera1 Effective Frame Status (Read Only) This bit indicates if the Camera1 input interface is capturing a valid frame. When this bit = 0b, a frame is not being captured. When this bit = 1b, a valid frame has been captured. bit 2 Camera1 Raw VSYNC Status (Read Only) This bit indicates the current state of the CM1VREF input pin. The polarity of this pin is controlled by the CM1VREF Polarity bit, REG[0D04h] bit 2. When REG[0D04h] bit 2 = 0b: When this bit = 0b, the CM1VREF input is low. When this bit = 1b, the CM1VREF input is high. When REG[0D04h] bit 2 = 1b: When this bit = 0b, the CM1VREF input is high. When this bit = 1b, the CM1VREF input is low. bit 1 Reserved The default value of this bit is 0b. bit 0 Reserved The default value of this bit is 0b. REG[0D0Fh] is Reserved This register is Reserved and should not be written. 332 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0D10h] Camera1 Resizer X Start Position Register 0 Default = 00h Read/Write Camera1 Resizer X Start Position bits 7-0 7 6 5 4 3 2 1 REG[0D11h] Camera1 Resizer X Start Position Register 1 Default = 00h Read/Write n/a 7 6 REG[0D11h] bits 2-0 REG[0D10h] bits 7-0 5 0 Camera1 Resizer X Start Position bits 10-8 4 3 2 1 0 Camera1 Resizer X Start Position bits [10:0] These bits specify the Camera1 resizer horizontal (X) start position, relative to the top left corner of the camera input image, in pixels. The resizer is used for cropping and/or defining the area of the camera image that will be down-scaled (see REG[0D18h] ~ REG[0D1Ah]). REG[0D12h] Camera1 Resizer Y Start Position Register 0 Default = 00h Read/Write Camera1 Resizer Y Start Position bits 7-0 7 6 5 4 3 2 1 REG[0D13h] Camera1 Resizer Y Start Position Register 1 Default = 00h Read/Write n/a 7 6 REG[0D13h] bits 2-0 REG[0D12h] bits 7-0 5 0 Camera1 Resizer Y Start Position bits 10-8 4 3 2 1 0 Camera1 Resizer Y Start Position bits [10:0] These bits specify the Camera1 resizer vertical (Y) start position, relative to the top left corner of the camera input image, in pixels. The resizer is used for cropping the camera input image and/or defining the area of the camera image that will be down-scaled (see REG[0D18h] ~ REG[0D1Ah]). REG[0D14h] Camera1 Resizer X End Position Register 0 Default = 00h Read/Write Camera1 Resizer X End Position bits 7-0 7 6 5 4 3 2 1 REG[0D15h] Camera1 Resizer X End Position Register 1 Default = 00h Read/Write n/a 7 REG[0D15h] bits 2-0 REG[0D14h] bits 7-0 6 5 0 Camera1 Resizer X End Position bits 10-8 4 3 2 1 0 Camera1 Resizer X End Position bits [10:0] These bits specify the Camera1 resizer horizontal (X) end position, relative to the top left corner of the camera input image, in pixels. The resizer is used for cropping the camera input image and/or defining the area of the camera image that will be down-scaled (see REG[0D18h] ~ REG[0D1Ah]). Hardware Functional Specification Rev. 1.7 EPSON 333 Chapter 10 Registers S1D13515/S2D13515 REG[0D16h] Camera1 Resizer Y End Position Register 0 Default = 00h Read/Write Camera1 Resizer Y End Position bits 7-0 7 6 5 4 3 2 1 REG[0D17h] Camera1 Resizer Y End Position Register 1 Default = 00h Read/Write n/a 7 6 REG[0D17h] bits 2-0 REG[0D16h] bits 7-0 5 0 Camera1 Resizer Y End Position bits 10-8 4 3 2 1 0 Camera1 Resizer Y End Position bits [10:0] These bits specify the Camera1 resizer vertical (Y) end position, relative to the top left corner of the camera input image, in pixels. The resizer is used for cropping the camera input image and/or defining the area of the camera image that will be down-scaled (see REG[0D18h] ~ REG[0D1Ah]). REG[0D18h] Camera1 Resizer Horizontal Scaling Rate Register Default = 00h Read/Write Camera1 Resizer Horizontal Scaling Rate bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 Camera1 Resizer Horizontal Scaling Rate bits [7:0] The Camera1 resizer supports down-scaling (reduction) of the camera input image. These bits specify the horizontal scaling rate for the Camera1 resizer according to the following formula. Camera1 horizontal scaling rate = REG[0D18h] bits 7-0 ÷ 128 REG[0D19h] Camera1 Resizer Vertical Scaling Rate Register Default = 00h Read/Write Camera1 Resizer Vertical Scaling Rate bits 7-0 7 bits 7-0 334 6 5 4 3 2 1 0 Camera1 Resizer Vertical Scaling Rate bits [7:0] The Camera1 resizer supports down-scaling (reduction) of the camera input image. These bits specify the vertical scaling rate for the Camera1 resizer according to the following formula. Camera1 vertical scaling rate = REG[0D19h] bits 7-0 ÷ 128 EPSON Hardware Functional Specification Rev. 1.7 S1D13515/S2D13515 Chapter 10 Registers REG[0D1Ah] Camera1 Resizer Scaling Control Register Default = 00h Read/Write Camera1 Resizer Scaling Mode bits 1-0 n/a 7 6 bits 1-0 5 4 3 2 1 0 Camera1 Resizer Scaling Mode bits [1:0] These bits determine the Camera1 resizer scaling mode. Before selecting a scaling mode, set the horizontal (REG[0D18h]) and/or vertical (REG[0D19h]) scaling rates. Table 10-57: Camera1 Resizer Scaling Mode Selection REG[0D1Ah] bits 1-0 Resizer Scaling Mode 00b no scaling 01b V/H reduction 10b V: Reduction, H: Average 11b Reserved REG[0D1Ch] is Reserved This register is Reserved and should not be written. REG[0D1Eh] Camera1 YRC Control Register 0 Default = 00h n/a 7 bits 6-5 Camera1 YRC RGB Pixel Output Format bits 1-0 6 5 Read/Write Camera1 YRC YUV Input Data Type 4 Camera1 YRC YUV Transfer Mode bits 2-0 3 2 1 Camera1 YRC Bypass Enable 0 Camera1 YRC RGB Pixel Output Format bits [1:0] These bits specify the RGB pixel format output by the Camera1 YRC (YUV to RGB Converter). The output from the Camera1 YRC goes to the Camera1 Writer which writes the image data to external SDRAM. For further information on the Camera1 Writer, see Section 22.6, “Camera Writer” on page 540. Table 10-58: RGB Pixel Format Selection bit 4 REG[0D1Eh] bits 6-5 RGB Pixel Format 00b RGB 3:3:2 01b RGB 5:6:5 10b RGB 8:8:8 11b Reserved Camera1 YRC YUV Input Data Type This bit selects the input data type for the Camera1 YRC (YUV to RGB Converter). When this bit = 0b, the input data type is YUV (0