PBL3766N

September 1997 PBL 3766, PBL 3766/6 Subscriber Line Interface Circuit Description The PBL 3766 Subscriber Line Interface Circuit (SLIC) is a monolithic integrated circuit, manufactured in 75 V bipolar technology. The PBL 3766 SLIC facilitates the design of cost effective, high performance on-premises (ONS) analog line interface cards for PABX systems and terminal adapters. Small package size and few required external components result in a miniaturized design. The PBL 3766 programmable, constant current loop feed system can operate with battery supply voltages between -24 V and -58 V. The SLIC incorporates loop current and ring trip detection functions as well as a ring relay driver. The two- to four-wire and four- to two-wire voice frequency (vf) signal conversion, i.e. the hybrid function, is provided by the SLIC in conjunction with either a conventional or a programmable CODEC/filter. The PBL 3766 package is a 22 pin, plastic dual-in-line (batwing) or a 28-pin, plastic j-leaded chip carrier (PLCC). The differences between PBL 3766 and PBL 3766/6 are the specifications for balance, output offset voltage, and insertion loss. Key Features • Low cost • Few external components • Programmable, constant current loop feed • Line feed characteristics independent of battery supply variations • -24 V to -58 V battery supply voltage range • Detectors – programmable loop current detector – ring trip detector • Ring relay driver • Hybrid function with conventional or programmable CODEC/filters • Line terminating impedance, complex or real, set by a simple external network or controlled by a programmable CODEC/filter Ring Relay Driver 5/3 RINGRLY • Idle noise typ. -83 dBmp, typ. 7 dBrnC • Low on-hook power dissipation: 20 mW @ -28 V, 35 mW @ -48 V • Tip-ring open circuit state for subscriber loop power denial • On-hook transmission 13/10 DT 23/20 C1 C2 Ring Trip Detector Input/Output Decoder and Control 12/9 TIPX HPT HPR RINGX VCC VEE VBAT GND 27/21 20/15 21/16 28/22 4/2 18/13 3, 6, 10, 17, 24/ 5, 6, 17, 18 2/1 9/7 11/8 E0 DET 7/4 RSG Loop Current Detector 22/19 19/14 RD VTX P L B P 66 37 16/12 RSN VF Signal Transmission Figure 1. Block diagram. Pin numbers PLCC/DIP. 4-1 B L 37 Two-wire Interface Line Feed Controller and Longitudinal Signal Suppression 14/11 RDC 66 PBL 3766 Absolute Maximum Ratings Parameter Symbol Min Max Unit Temperature and humidity Storage temperature range Operating temperature range Operating junction temperature Storage humidity Power supply, -10 °C < TAmb < 80 °C VCC with respect to GND VEE with respect to GND VBat with respect to GND Power dissipation Continuous power dissipation at TAmb ≤ 70 °C Peak power dissipation at TAmb = 70°C, t < 10 ms, trep > 10 sec. Relay driver Ring relay supply voltage Ring relay current Ring trip comparator Input voltage Input current Digital inputs, outputs (C1, C2, E0, DET) Input voltage Output voltage (DET disabled) Output current (DET enabled) TIPX or RINGX terminals, VBAT = -50 V TIPX or RINGX voltage, continuous, (Note 1) TIPX or RINGX pulse = tω < 10 ms, trep > 10 s (Notes 2, 3) TIPX or RINGX pulse = tω < 1 µs, trep > 10 s (Notes 2, 3) TIP or RING pulse = tω < 250 ns, trep > 10 s (Notes 2, 3) TIPX or RINGX current Active Stand-by TStg TCase TJ RH VCC VEE VBat PD PDP VRRly IRRly VDT IDT VID VOD IOD VT, VR VT, VR VT, VR VT, VR ILdc + ILodc ILdc -60 -10 -10 5 +150 +110 +140 95 °C °C °C % RH -0.5 -6.5 -70 6.5 0.5 VEE+0,7 1.5 4 V V V W W VBat 0 50 V mA VBat -2 0 2 V mA 0 0 VCC VCC 5 V V mA VBat VBat - 20 VBat - 40 VBat - 70 0.5 5 10 15 80 25 V V V V mA mA Recommended Operating Conditions Parameter Symbol Min Max Unit Case temperature VCC with respect to ground VEE with respect to ground VBat with respect to ground (Note 4) TCase VCC VEE VBat 0 4.75 -5.25 -58 90 5.25 -4.75 -24 °C V V V Notes 1. 2. 3. 4. With a diode (D2) connected in series with the VBat supply, as shown in figure 11, -70 V may be continuously applied to the TIPX or RINGX lead. These voltage ratings require a diode (D2) to be installed in series with the VBat supply as shown in figure 11. VT and VR are referenced to ground. tω is the pulse width of a rectangular test pulse and trep is the pulse repetition rate. -24 V < VBat < -21 V may be used in applications requiring maximum vf signal amplitudes less than 3 Vpk (8.75 dBm, 600 ohms). 4-2 PBL 3766 Electrical Characteristics 0 °C < TAmb < 70 °C, VCC = +5 V ±5 %, VEE = -5 V ±5 %, VBat = -48 V, RSG = 0 ohm , RDC = 41.7 kohms, RD = ∞, ZL = 600 ohms, CHP = 33 nF, CDC = 1.5 µF unless otherwise specified. Parameter Ref Fig. Conditions Min Typ Max Unit Two-wire port Overload level, VTRO Input impedance, ZTRX Longitudinal impedance, ZLoT, ZLoR Longitudinal current limit, ILoT, ILoR Longitudinal to metallic balance, BLM PBL 3766 PBL 3766/6 Longitudinal to metallic balance, BLME 2 ZL = 600 ohms, 1% THD, Note 1 Note 2 f < 100 Hz active state, C2, C1 = 1, 0 IEEE standard 455-1985 0.2 kHz ≤ f ≤ 3 kHz 3.1 25 20 40 VPk ohm/wire mApk/wire 53 48 3 |VTR| 0.05kHz ≤ f ≤ 3.4kHz BLME = 20 · log |ELo| 58 58 dB dB PBL 3766 PBL 3766/6 Longitudinal to four-wire balance, BLFE 53 48 3 |VTX| 0.05kHz ≤ f ≤ 3.4kHz BLFE = 20 · log |ELo| 58 58 dB dB PBL 3766 PBL 3766/6 Metallic to longitudinal balance, BMLE 53 48 4 BMLE = 20 · log |ETR| |VLo| 0.2kHz ≤ f ≤ 3.4kHz , ERX = 0 50 48 4 BFLE = 20 · log |ERX| |VLo| 0.2kHz ≤ f ≤ 3.4kHz , ETR source removed 40 58 58 dB dB PBL 3766 PBL 3766/6 Four-wire to longitudinal balance, BFLE 55 55 dB dB 55 dB C TIPX 27/21 VTX 19/14 Figure 2. Overload level, VTRO, two-wire port. 1 ωC < RL, RL = 600 ohms, < RL V TRO I Ldc PBL 3766 RINGX 28/22 RSN 16/12 RT E RX RT = 600 kohms, RRX = 300 kohms RRX Figure 3. Longitudinal to metallic (BLME) and longitudinal to four-wire (BLFE) balance. 1 ωC 20 kohms, 1% THD, Note 4 r = 20 · log |ZTRX + ZL| 25 27 23 30 32 25 -5 0 -43 -48 3.1 dB dB dB V V V V VPk -40 -55 0.2 kHz < f < 3.4 kHz IRSN = 0 0.3 kHz ≤ f ≤ 3.4 kHz 0.3 kHz ≤ f ≤ 3.4 kHz 7.3 mA, KLThOn = 455 V output may be monitored by circuits on The on-hook to off-hook loop current the line card, which perform the ringtrip detector threshold, ILThOff, for a specific RD function (hardware ringtrip). value is calculated from The ringing source may be balanced or 1 1 unbalanced, superimposed on the VBat ILThOff = KLThOff ·  +  supply voltage. A ring relay, energized by  RD 62500  the SLIC ring relay driver, connects the where ringing source to tip and ring. For unbalILThOff is in amperes for RD in ohms. anced ringing systems the loop current ILThOff > 8.0 mA, KLThOff = 500 V sensing resistor, RRT, is placed in series with the return lead to ground. With a lower voltage battery it may be Figures 15 and 16 show examples of desirable to decrease the loop current detector thresholds. For more information unbalanced and balanced ringing systems. For either ringing system the on this issue, please contact the factory. ringtrip detection function is based on a During dial pulsing the loop current polarity change at the inputs of the ringtrip detector is aided by a speed-up circuit, acting on the RDC output at loop closures. comparator. In the unbalanced case the dc voltage The speed-up circuit will charge the CDC drop across resistor RRT is zero, as long capacitor at a more rapid rate than that set as the telephone remains on-hook. With by the (CDC· RDC· 41700)/(RDC+ 41700) time constant, resulting in the loop current the telephone off-hook during ringing, dc loop current will flow, causing a voltage reaching the detector threshold value drop across RRT. The RRT voltage is faster and therefore minimizing dial pulse applied to the comparator input DT via distortion. resistor R1. R2 shifts the voltage level to Loop Current Detector - Filter Capacitor be compatible with the inverting input VEE reference voltage. CRT removes part of To increase the loop current detector the ac component of the ringing signal. noise immunity, a filter capacitor may be The inverting comparator input is added from terminal RD to ground. A biased at VEE, which is more negative suggested value for CD is than DT when the telephone is on-hook RD + 62500 and is more positive than DT when the CD = 2π · (RD · 62500) · f3dB telephone goes off-hook during ringing. Complete removal of the ringing signal where ac component at the DT input is not CD is in farads for RD in ohms f3dB = 500 Hz necessary. Some residual ac component at the DT input may, under certain Note that CD may not be required if the operating conditions, cause the DET DET output is software filtered. 4-14 Control Inputs Overview The PBL 3766 SLIC has two TTL compatible control inputs, C1 and C2. A decoder in the SLIC interprets the control input conditions and sets up the commanded operating state. Open Circuit State (C2, C1 = 0, 0) In the Open Circuit State the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. PBL 3766 TIPX 27/21 + I Ldc GND VTR -2.5 V 14/11 41.7 kΩ RDC RL VTR 28/22 1 RINGX VBat I Ldc + Comp VTR > VSG Ref VTR < VSG Ref 1 0 C DC RDC VSG Ref RSG 7/4 0.6 Figure 12. Battery feed (C2, C1 = 1, 0; active state). 5·105 VSGRef = 12.5 + RSG + 25 kΩ VSG = -7.50 – 3.0·105 RSG + 25 kΩ R SG Saturation Guard I Ldc 1000 VSG V EE 16/12 RSN PBL 3766 I L (mA) 40 30 20 10 0 RDC = 21.0 kohms RDC = 41.2 kohms RDC = 82.5 kohms Figure 13. PBL 3766 loop feed examples. RSG = 0 ohms VBat = -58 V to -42 V 0 500 1000 R L (ohms) 1500 2000 I LTIPX TIPX RINGX 27/21 28/22 I LRINGX Ring trip Comparator 2-Wire Interface I LTIPX - I LRINGX 2K Input Decoder VCC 13/10 12/9 C1 C2 Figure 14. Loop current detector. On-hook to off-hook loop current threshold, ILThOff : ILThOff = 8.0 mA for RD → ∞ For ILThOff > 8.0 mA: RD = 1 , ILThOff /KLThOff - 1/62500 62.5 kΩ VEE + - MUX 11/8 9/7 DET E0 PBL 3766 1.25V 22/19 18/13 RD VEE CD RD -5V KLThOff = 500 V (includes factor K) 4-15 PBL 3766 This causes the SLIC to present a high impedance to the line. Power dissipation is at a minimum. No detectors are active. Ringing State (C2, C1 = 0, 1) The ring relay driver, RINGRLY, is activated and the ring trip comparator is connected to the detector out-put, DET. The TIPX and RINGX terminals are in the high impedance state and signal transmission is inhibited. Active State (C2, C1 = 1, 0) TIPX is the terminal closest to ground potential and sources loop current, while RINGX is the more negative terminal and sinks loop current. Vf signal transmission is normal. The loop current detector is activated and connected to the DET output. Stand-By State (C2, C1 = 1, 1) In the stand-by state the line drive amplifiers are disconnected. The loop feed is converted to resistive form according to IL ≈ VBat - 3 V RL + 1800 Ω = loop current (A) where IL VBat = battery supply voltage (V) RL = loop resistance (ohm) The short circuit loop current (ILSh) for VBat = -48V is then limited to ILSh ≈ 25.0 mA. The loop current detector is activated in the stand-by state and is gated to the DET output. Table 1 summarizes the above description of the control inputs. RRT R1 CRT DT 23/20 DR + To DET - R2 TIP E RG KR VEE PBL 3766 Figure 15. Example ring trip network, unbalanced ringing. Note: Ericsson Components unbalanced ring trip network PBA 3310 contains a two-pole filter. RING VBat E RG+ RRT1 150Ω DT R1 150kΩ RRT2 150Ω E RG-48V -48V TIP RF1 RF2 RING KR Protection 23/20 DR + To DET R2 150kΩ C1 470nF C2 470nF R3 3.1MΩ - VEE TIPX 27/21 RINGX 28/22 PBL 3766 Figure 16. Example ring trip network, balanced ringing. 4-16 PBL 3766 dissipators, when transients are clamped TTL compatible enable input E0 controls and of being fuses, when the line is exposed to a power cross. Ericsson the function of the DET output. E0, when set to logic level low, enables Components AB offers a series of thick the DET output, which is a collector output film resistors networks (e g PBR 51-series and PBR 53-series) designed for this with internal pull-up resistor (approx. application. 15 kohms) to VCC. A DET output at logic Also devices with a build in resetable level low indicates triggered detector fuse function is offered (e g PBR 52condition (loop current above threshold series) including positive temperature current or telephone off-hook during coefficient (PTC) resistors, working as ringing). A DET output at logic level high resetable fuses, in series with thick film indicates a non triggered detector resistors. Note that it is important to condition. E0, when set to logic level high disables always use PTC's in series with resistors the DET output; i.e. it appears as a resist- not sensitive to temperature, as the PTC will act as a capacitance for fast or connected to VCC. Table 2 summarizes the above descrip- transients and therefore the ability to protect the SLIC will be reduced. tion of the enable input. If there is a risk for overvoltages on the Overvoltage Protection VBat terminal on the SLIC, then this terminal should also be protected. The PBL 3766 SLIC must be protected against overvoltages and power crosses. Overtemperature Protection Refer to Maximum Ratings, TIPX and A ring lead to ground short circuit fault RINGX terminals for maximum allowable condition, as well as other improper continuous and transient voltages, that operating modes, may cause excessive may be applied to the SLIC. The circuit shown in figure 11 utilizes series resistors SLIC power dissipation. If junction temperature increases beyond 160 °C, (RF, RF) together with a programmable the temperature guard will trigger, causing overvoltage protector (e g Texas Instrument TISP PBL1), serving as a secondary the SLIC to be set to a high impedance state. In this high impedance state power protection. dissipation is reduced and the junction The protection network in figure 11 is designed to meet requirements in CCITT temperature will return to a safe value. Once below 140 °C junction temperature K20, Table 1. The TISP PBL1 is a dual the SLIC is returned back to its normal forward-conducting buffered p-gate overvoltage protector. The protector gate operating mode and will remain in that state assuming the fault condition has references the protection (clamping) voltage to negative supply voltage (i e the been removed. Table 1. PBL 3766 operating states battery voltage, V ). As the protection Bat Enable Input (E0) Power-up Sequence The voltage at pin VBAT sets the substrate voltage, which must at all times be kept more negative than the voltage at any other terminal. This is to maintain correct junction isolation between devices on the chip. To prevent possible latch-up, the correct power-up sequence is to connect ground and VBat, then other supply voltages and signal leads. Should the VBat supply voltage be absent, a diode with a 2 A current rating, connected with its cathode to VEE and anode to VBat, ensures the presence of the most negative supply voltage at the VBAT terminals. The VBat voltage should not be applied at a faster rate than ∂VBat/∂t = 4 V/µsec or with a time constant formed by a 5.1 ohm resistor in series with the VBAT pin and a 0.47 microfarad capacitor from the VBAT pin to ground. One resistor may be shared by several SLICs. Printed Circuit Board Layout Care in PCB layout is essential for proper function. The components connecting to the RSN input should be placed in close proximity to that pin, such that no interference is injected into the RSN terminal. A ground plane surrounding the RSN pin is advisable. The CHP capacitor should be placed close to terminals HPT and HPR to avoid un-wanted disturbances. voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimised. Positive overvoltages are clamped to ground by an internal diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage. If sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition, clamping the over-voltage close to ground. A gate decoupling capacitor, CTISP is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. Without the capacitor even the low inductance in the track to the VBat supply will limit the current and delay the activation of the thyristor clamp. The fuse resistors RF serve the dual purposes of being non-destructive energy State number C2 C1 SLIC operating state Active detector DET Output Note 1. 1 2 3 4 0 0 1 1 0 1 0 1 Open circuit Ringing Active Stand-by No active detector Ring trip detector Loop curr. detector Loop curr. detector Logic level high Ring trip status Loop current status Loop current status Note 1. E0 = 0, i.e. the DET output is enabled. A logic low level at the DET output indicates a triggered detector. Table 2. Enable input E0 Enable state E0 DET output status Active detector 1 2 0 1 Active High impedance Note 2. Loop current or ring trip detector Note 1. None Notes 1. Detector selected according to Table 1. 2. In the high impedance state the DET output appears as a 15 kohms resistor to VCC 4-17 PBL 3766 Ordering Information Package Temp. Range Part No. Plastic DIP 22 pin Plastic DIP 22 pin PLCC 28 pin PLCC 28 pin 0 °C to 70 °C 0 °C to 70 °C 0 °C to 70 °C 0 °C to 70 °C PBL 3766N PBL 3766/6N PBL 3766QN PBL 3766/6QN Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Components AB. These products are sold only according to Ericsson Components AB' general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. 1522-PBL 3766 Uen Rev. B © Ericsson Components AB September 1997 This product is an original Ericsson product protected by US, European and other patents. Ericsson Components AB S-164 81 Kista-Stockholm, Sweden Telephone: (08) 757 50 00 4-18