PBL386102QNT

February 1999 PBL 386 10/2 Subscriber Line Interface Circuit Description The PBL 386 10/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in PBX, Terminal adapters and other telecommunications equipment. The PBL 386 10/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 10/2 emulates a transformer equivalent dc-feed, programmable between 2x25 Ω and 2x900 Ω, with short loop current limiting adjustable to max 65 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 10/2 is compatible with loop start signalling. Two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating impedance could be complex or real to fit every market. Longitudinal line voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 10/2 package is 28-pin PLCC. Key Features • Selectable overhead voltage principle – All adaptive: The overhead voltage follows 0.6 VPeak < signals < 5 VPeak. – Semi adaptive: The overhead voltage follows 2.5 VPeak < signals < 5 VPeak. • Metering 1.6Vrms • High and low battery with automatic switching • Battery supply as low as -10V • Only +5V in addition to GND and battery (VEE optional) • 35 mW on-hook power dissipation in active state • Long loop battery feed tracks VBat for maximum line voltage • 44V open loop voltage @ -48 V battery feed • Constant loop voltage for line leakage 10 s, Note 2 TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 TIP or RING, pulse < 250 ns, tRep > 10 s, Note 3 TStg TAmb TJ VCC VEE VBat VBat VBat2 PD VG -55 -40 -40 -0.4 VBat -75 -80 VBat +150 +110 +140 6.5 0.4 0.4 0.4 0.4 1.5 °C °C °C V V V V V W V V -5 VCC BGND +13 75 mA VDT, VDR IDT, IDR VID VOD IOD ITIPX, IRINGX VTA, VRA VTA, VRA VTA, VRA VTA, VRA VBat -5 -0.4 -0.4 VCC 5 VCC VCC 30 V mA V V mA -110 VBat VBat - 20 VBat - 40 VBat - 70 +110 2 5 10 15 mA V V V V Recommended Operating Condition Parameter Symbol Min Max Unit Ambient temperature VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND VBat2 with respect to BGND TAmb VCC VEE VBat VBat2 0 4.75 VBat -58 VBat +70 5.25 -4.75 -10 -10 °C V V V V Notes 1. 2. 3. The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V. A pulse ≤1µs is increased to the greater of |-70V| and |VBat -40V|. RF1 and RF2 ≥ 20 Ω are also required. Pulse is supplied to TIP and RING outside RF1 and RF2. 2 PBL 386 10/2 Electrical Characteristics 0 °C ≤ TAmb ≤ +70 °C, VCC = +5V ±5 %, VEE = -5V ± 5%, VBat = -58V to -40V, RLC=18.7kΩ, (IL = 27 mA), ZL = 600 Ω, RLD = 50 kΩ, RF1, RF2 = 0 Ω, RRef = 15kΩ, CHP = 68nF, CLP=0.33 µF, RT = 120 kΩ, RSG = 24 kΩ, RRX = 120 kΩ, AOV- and VBat2-pin not connected, unless otherwise specified. Current definition: current is positive if flowing into a pin. Ref fig Parameter Conditions Min Typ Max Unit Two-wire port Overload level, VTRO Off-Hook, ILDC ≥ 10 mA On-Hook, ILDC ≤ 5 mA Input impedance, ZTR Longitudinal impedance, ZLoT, ZLoR Longitudinal current limit, ILoT, ILoR Longitudinal to metallic balance, BLM 2 Active state 1% THD, Note 1 2.5 1.4 ZT/200 20 35 VPeak VPeak Ω/wire mArms /wire dB dB Note 2 0 < f < 100 Hz active state 12 IEEE standard 455-1985,ZTRX = 736 Ω 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 3 active state 0.2 kHz ≤ f ≤ 1.0 kHz 1.0 kHz < f < 3.4 kHz 3 active state 0.2 kHz ≤ f ≤ 1.0 kHz 1.0 kHz < f < 3.4 kHz 4 active state 0.2 kHz < f < 3.4 kHz 59 59 53 53 70 70 Longitudinal to metallic balance, BLME E BLME = 20 • Log Lo VTR Longitudinal to four-wire balance, BLFE ELo BLFE = 20 • Log VTX Metallic to longitudinal balance, BMLE VTR BMLE = 20 • Log VLo 70 70 dB dB 70 70 dB dB 40 58 dB Figure 2. Overload level, VTRO, two-wire port RL VTRO C TIPX VTX ILDC 1 2.5 VPeak. If pin is connected to AGND then no internal overhead voltage is set. The overhead voltage adapts to 0.6 VPeak < signals < 5 VPeak. Programmable Saturation Guard. The resistive part of the DC feed characteristic is programmed by a resistor connected from this pin to VBAT. Low Pass saturation guard filter capacitor connected here to filter out noise and improve PSRR. Other end of CLP connects to VBAT. Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The ring trip network connects to this input. Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The ring trip network connects to this input. -5V to VBAT power supply. A 15kohm resistor should be connected between this pin and AGND. Not Used. Must be left open. Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor connected from this pin to AGND. Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor connected from this pin to AGND. +5 V power supply. C1, C2 and C3 are digital inputs Controlling the SLIC operating states. Refer to section Operating states for details. No Connect. Must be left open. Detector output. Active low when indicating loop or ring trip detection, active high when indicating ground key detection Receive Summing Node. 400 times the current flowing into this pin equals the metallic (transversal) current flowing from TIPX to RINGX. Programming networks for two-wire impedance and receive gain connect to the receive summing node. Analog Ground, should be tied together with BGND. Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire impedance programming network connects between VTX and RSN. Ring Relay driver output. Tip Sense should be connected to TIPX. No Connect. Must be left open. High Pass connection for ac/dc separation capacitor CHP. Other end of CHP connects to RINGX (pin 26). The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). Battery Ground, should be tied together with AGND. The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). } RSN 20 21 AGND VTX 22 23 24 25 26 27 28 RRLY TS NC HP RINGX BGND TIPX 8 PBL 386 10/2 VBAT2 28 27 LP 5 DT 6 DR 7 VEE 8 REF 9 NU 10 PLC 11 26 4 3 2 1 RINGX BGND VBAT TIPX PSG AOV 25 HP 24 NC* 23 TS 22 RRLY 21 VTX 20 AGND 19 RSN PLD 12 VCC 13 C3 14 C2 15 C1 16 NC* 17 DET 18 * Pins must be left open. Figure 7. Pin configuration, 28 pin PLCC package, top view. SLIC Operating States State 0 1 2 3 4 5 6 7 C3 0 0 0 0 1 1 1 1 C2 0 0 1 1 0 0 1 1 C1 0 1 0 1 0 1 0 1 SLIC operating state Open circuit Ringing state Active state Not applicable Not applicable Active state Not applicable Not applicable Active detector Detector is set high Ring trip detector (active low) Loop detector (active low) Ground key detector (active high) - Table 1. SLIC operating states. 9 PBL 386 10/2 + ZL VTR TIP RF ZTR TIPX IL EL RHP + G2-4S IL VTX + VTX - + RING RF RINGX ZT - Z RX RSN I L /α RSN + VRX PBL 386 10/2 Figure 9. Simplified ac transmission circuit. - Functional Description and Applications Information Transmission General A simplified ac model of the transmission circuits is shown in figure 9. Circuit analysis yields: VTX VTR = (1) - I • 2RF G2-4S L VTX VRX I (2) + =L ZRX αRSN ZT VTR = IL • ZL - EL (3) VRX is the analogue ground referenced receive signal. αRSN is the receive summing node current to metallic loop current gain. The nominal value of αRSN = 400 Two-Wire Impedance To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the fuse resistor RF, let VRX = 0. From (1) and (2): ZT ZTR = - 2RF αRSN • G2-4S Thus with ZTR, G2-4S, αRSN, and RF known: ZT = αRSN • G2-4S • (2RF - |ZTR|) Two-Wire to Four-Wire Gain From (1) and (2) with VRX = 0: G2-4 = VTX = VTR ZT/αRSN ZT - 2RF αRSN • G2-4S Four-Wire to Two-Wire Gain From (1), (2) and (3) with EL = 0: G4-2 = VTX ZT ZL • = VTR ZRX ZT • ( ZL + 2RF) -G αRSN 2-4S where: VTX is a ground referenced version of the ac metallic voltage between the TIPX and RINGX terminals. VTR is the ac metallic voltage between tip and ring. EL is the line open circuit ac metallic voltage. IL is the ac metallic current. RF is a fuse resistor. G2-4S is the SLIC two-wire to fourwire gain (transmit direction) with a nominal value of -0.5. ZL is the line impedance. ZT determines the SLIC TIPX to RINGX impedance for signal in the 0 - 20kHz frequency range. ZRX controls four- to two-wire gain. In applications where 2RF - ZT/(αRSN • G2-4S) is chosen to be equal to ZL, the expression for G4-2 simplifies to: G4-2 = ZT 1 • ZRX 2 • G2-4S Four-Wire to Four-Wire Gain From (1), (2) and (3) with EL = 0: G4-4 = G2-4S • ( ZL + 2RF) VTX ZT • = VRX ZRX ZT - G2-4S • ( ZL + 2RF) αRSN 10 PBL 386 10/2 Hybrid Function The hybrid function can easily be implemented utilizing the uncommitted amplifier in conventional CODEC/filter combinations. Please, refer to figure 10. Via impedance ZB a current proportional to VRX is injected into the summing node of the combination CODEC/filter amplifier. As can be seen from the expression for the four-wire to four-wire gain a voltage proportional to VRX is returned to VTX. This voltage is converted by RTX to a current flowing into the same summing node. These currents can be made to cancel by letting: VTX VRX + = 0 (EL = 0) RTX ZB The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the balance network ZB can be calculated from: V ZB = - RTX • RX = VTX ZT αRSN - G2-4S • ( ZL + 2RF) G2-4S • ( ZL + 2RF) The PBL 386 10/2 SLIC may also be used together with programmable CODEC/ filters. The programmable CODEC/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information. Longitudinal Impedance A feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will appear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leaving metallic voltages well within the SLIC common mode range. The SLIC longitudinal impedance per wire, ZLoT and ZLoR, appears as typically 20 Ω to longitudinal disturbances. It should be noted that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. Capacitors CTC and CRC If RFI filtering is needed, the capacitors designated CTC and CRC in figure 12, connected between TIPX and ground as well as between RINGX and ground, may be mounted. CTC and CRC work as RFI filters in conjunction with suitable series impedances (i.e. resistances, inductances). Resistors RF1 and RF2 may be sufficient, but series inductances can be added to form a second order filter. Current-compensated inductors are suitable since they suppress common-mode signals with minimum influence on return loss. Recommended values for CTC and CRC are below 1 nF. Lower values impose smaller degradation on return loss and longitudinal balance, but also attenuate radio frequencies to a smaller extent. The influence on the impedance loop must also be taken into consideration when programming the CODEC. CTC and CRC contribute to a metallic impedance of 1/(π•f•CTC) = 1/(π•f•CRC), a TIPX to ground impedance of 1/(2•π•f•CTC) and a RINGX to ground impedance of 1/(2•π•f•CRC). AC - 3DC Separation Capacitor, CHP The high pass filter capacitor connected between terminals HP and RINGX p r o vides the separation of the ac and dc signals. CHP positions the low end frequency response break point of the ac loop in the SLIC. Refer to table 1 for recommended value of CHP. Example: A CHP value of 68 nF will position the low end frequency response 3dB break point of the ac loop at 13 Hz (f3dB) according to f3dB = 1/(2•π•RHP•CHP) where RHP = 180 kΩ. Z - RTX • RX • ZT When choosing RTX, make sure the output load of the VTX terminal is (RTX//RT in figure 12) > 20 kΩ. If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended. Contact Ericsson Microelectronics for assistance. RFB RTX VTX VT ZT Z RX RSN ZB PBL 386 10/2 Combination CODEC/Filter V RX Figure 10. Hybrid function. 11 PBL 386 10/2 High-Pass Transmit Filter When CODEC/filter with a singel 5 V power supply is used, it is necessary to separate the different signal reference voltages between the SLIC and the CODEC/filter. In the transmit direction this can be done by connecting a capacitor between the VTX output of the SLIC and the CODEC/filter input. This capacitor will also form, together with RTX and/or the input impedance of the CODEC/filter, a high-pass RC filter. It is recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a fast enough response for the dc steps that may occur with DTMF signaling. Capacitor CLP The capacitor CLP, which connects between the terminals LP and VBAT, positions the high end frequency break point of the low pass filter in the dc loop in the SLIC. CLP together with CHP and ZT (see section TwoWire Impedance) forms the total two wire output impedance of the SLIC. The choice of these programming components influence the power supply rejection ratio (PSRR) from VBAT to the two wire side in the low frequency range. RFeed RSG CLP CHP [Ω] [kΩ] [nF] [nF] 2•25 4.02 330 68 23.7 330 68 2•50 2•200 147 100 33 2•400 301 47 33 2•800 619 22 33 Table 1. RSG, CLP and CHP values for different feeding characteristics. Table 1 suggest values of CLP and CHP for different feeding characteristics. For values outside table 1, please contact Ericsson Microelectronics for assistance. Adaptive Overhead Voltage, AOV The Adaptive Overhead Voltage feature minimises the power dissipation and at the same time provides a flexible solution for differing system requirements and possible future changes concerning voice, metering and other signal levels. This is done by using an overhead voltage which automatically adapts to the signal level (voice + metering). With the AOV-pin left open, the PBL 386 10/2 will behave as a SLIC with fixed overhead voltage for signals in the 0 - 20kHz frequency range and with an ampli- Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst undersampled). tude less than 2.5VPeak11. For signal amplitudes between 2.5VPeak and 5.0VPeak, the AOV-function will expand the overhead voltage making it possible for the signal, Vt, to propagate through the SLIC without distortion (see figure 11). The expansion of the overhead voltage occurs instantaneously. When the signal amplitude decreases, the overhead voltage returns to its initial value with a time constant of approximately one second. If the AOV-pin is connected to AGND, the overhead voltage will automatically be adjusted for signal levels between 0.6 VPeak and 5.0 VPeak. AOV In the Constant Current Region When the overhead voltage is automatically increased, the apparent battery (VApp, reference F in figure 13), will be reduced by the signal amplitude minus 2.5 VPeak(11), (Vt - 2.5(11)). In the constant current region this change will not affect the line current as long as VTR < VApp - (ILConst • RFeed) - (Vt- 2.5(11)), (references A-C in figure 13). AOV In the Resistive Loop Feed Region The saturation guard will be activated when the SLIC is working in the resistive loop feed region, i.e. VTR > VApp - (ILConst • RFeed) - (Vt - 2.5(11)) (references D in figure 13). If the signal amplitude is greater than 2.5VPeak11 the line current, IL, will be reduced corresponding to the formula ∆IL = | (Vt - 2.5(11))/(RL + RFeed) |. This reduction of line current will introduce a transversal signal into the two-wire which under some circumstances may be audible (e g when sending metering signals > 2.5 VPeak without any speech signal burying the transversal signal generated from the linecurrent reduction). The sum of all signals should not exceed 5.0 VPeak. Line Feed If VTR < VApp - (ILConst • RFeed), the PBL 386 10/ 2 SLIC will emulate constant current feed (references A-C in figure 13). For VTR > VApp - (ILConst • RFeed) the PBL 386 10/2 SLIC will emulate resistive loop feed programmable between 2•25 Ω12 and 2•900 Ω (references D in figure 13). The current limitation region is adjustable between 0 mA and 65 mA13. When the line current is approaching open loop conditions, the overhead voltage is reduced. To ensure maximum open loop voltage, even with telephone line leakage, this occurs at a line current of approximately 5 mA (references E in figure 13). After the overhead voltage reduction, the line voltage is kept nearly constant with a steep slope corresponding to 2 • 25 Ω(reference G in figure 13). The open loop voltage, VTRMax, measured between the TIPX and RINGX terminals is tracking the battery voltage VBat (references H in figure 13). VTRMax is programmable by connecting the AOV-pin to AGND or by leaving the AOV-pin open. 12 PBL 386 10/2 VTRMax is defined as the battery voltage on the VBat terminal minus the Battery Over Head voltage, VBOH, according to the equation VTRMax(at IL = 0 mA) = |VBat| - VBOH Refer to table 2 for typical VBOH values. VBOH(typ) [V] 3.7 3.2 If the VB2 voltage is not available, an optional external power management resistor, RPM, may be connected between the VBAT2-pin and the VBAT-pin to move power dissipation outside the chip. Calculation of the external power management resistor to locate the maximum power dissipation outside the SLIC is according to: RPM = |VBat| - 3 ILProg Analog Temperature Guard The widely varying environmental conditions in which SLICs operate may lead to the chip temperature limitations being exceeded. The PBL 386 10/2 SLIC reduces the dc line current and the longitudinal current limit when the chip temperature reaches approximately 145°C and increases it again automatically when the temperature drops. The detector output, DET, is forced to a logic low level when the temperature guard is active. AOV-PIN NC AOV-PIN to AGND Table 2. The battery overhead voltages at open loop conditions. Resistive Loop Feed Region The resistive loop feed (reference D in figure 13) is programmed by connecting a resistor RSG , between terminals PSG and VBAT according to the equation RFeed = RSG + 40 + 2RF 400 Metering Applications It is very easy to use PBL 386 10/2 in metering applications; simply connect a suitable resistor (RM) in series with a capacitor (CM) between pin RSN and the metering source. Capacitor CM decouples all DC-voltages that may be superimposed on the metering signal. Choose 1/(2πRMCM) ≥ 5kHz to suppress low frequency disturbances from the metering puls generator. The metering signal gain can be calculated from the equation: G4-2Metering = ZT ZM VTR = VMeter Loop Monitoring Functions The loop current, ground key and ring trip detectorsreport their status through a common output, DET. The status of the detector pin, DET, is selected via the three bit control interface C1, C2 and C3. Please refer to section Control Inputs for a description of the control interface. Constant Current Region The current limit (reference C in figure 13) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation: RLC = 500 ILProg 14 • ZLM ZT - G2-4S • (ZLM + 2RF) αRSN Battery Switch (VBAT2) To reduce short loop power dissipation, a second lower battery voltage may be connected to the device through an external diode at terminal VBAT2. The SLIC automatically switches between the two battery supply voltages without need for external control. The silent battery switching occurs when the line voltage passes the value |VBat2| - 40•IL - 6 15 Connect the terminal VBAT2 to the second power supply via the diode DB2 in figure 14. An optional diode DBB connected between terminal VBAT and the VB2 power supply, see figure 12, will make sure that the SLIC continues to work on the second battery even if the first battery voltage disappears. where Vmeter is the voltage of the signal at the metering generator, is the line impedance seen by the ZLM 12 or 16 kHz metering signal, G2-4S is the transmit gain through the SLIC, i e -0.5. In metering applications with resistive line feeding characteristic and very strict requirements (as mentioned earlier in chapter “AOV in resistive loop feed region“), the metering signal level should not exceed 2.2 VRMS 16, since a reduction of the line current will generate a transversal, and sometimes audible, signal (which is not the case in the constant current region). 13 PBL 386 10/2 R FB PBL 386 10/2 KR RRLY VTX AGND RSN DET R TX out RT R RX RB + +12 V /+5V C GG R F1 C RC VB C TC D B2 C HP TS NC RING HP RINGX BGND TIPX VBAT VBAT2 out NC C1 C2 C3 VCC PLD PLC NC REF VEE OVP TIP R F2 CODEC/ Filter VB2 DB VB CB R1 E RG R RF R RT R2 C LP D BB C B2 R SG VCC R LD R LC SYSTEM CONTROL INTERFACE AOV PSG LP DR DT R REF VEE C1 R3 R4 C2 +5 V C VCC VCC C VEE VBAT