PBL38615-1

Preliminary Information February 2000 PBL 386 15/1 Subscriber Line Interface Circuit Description The PBL 386 15/1 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in ISDN Network Terminal Adapters, DAML, FITL and other short loop telecommunication equipment which often are remote powered, and by that, the available power is limited. The PBL 386 15/1 has been optimized for low total line interface cost, low power and requires a minimum of external components. The PBL 386 15/1 has constant current feed, programmable to max 30mA. The SLIC uses a first battery voltage for On-hook . A second battery voltage is used for Off-hook and must be connected, to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The loop current controls the switching between On-hook and Off-hook battery. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 15/1 is compatible with loop start signalling. Two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating impedance could be complex or real to fit every market. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 15/1 package is a very PCB space efficient 28-pin SSOP. Applications • • • • ISDN Network terminals DAML FITL Shortloop applications Key Features • Small footprint with SSOP package • On-hook and Off-hook battery with automatic switching, controlled by loop current • On-hook battery current is limited to 6 mA • 37 mW on-hook power dissipation in active state • Metering 0.5 Vrms (0.7 Vpeak) • Adaptive Overhead Voltage The overhead voltage follows 1Vpeak 10 s, Note 2 TIP or RING, pulse < 250 ns, tRep > 10 s, Note 3 TStg TAmb TJ VCC VEE VBat2 VBat VBat2 PD VG -55 -40 -40 -0.4 VBat VBat -75 -80 +150 +110 +140 6.5 0.4 0.4 0.4 0.4 0.8 °C °C °C V V V V V W V V -5 VCC BGND +13 75 mA VDT, VDR IDT, IDR VID VOD IOD ITIPX, IRINGX VTA, VRA VTA, VRA VTA, VRA VTA, VRA VBat -5 -0.4 -0.4 VCC 5 VCC VCC 30 V mA V V mA -110 VBat VBat - 20 VBat - 40 VBat - 70 +110 2 5 10 15 mA V V V V Recommended Operating Condition Parameter Symbol Min Max Unit Ambient temperature VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND VBat2 with respect to BGND TAmb VCC VEE VBat VBat2 -40 4.75 VBat -58 VBat +85 5.25 -4.75 -10 -10 °C V V V V Notes 1. 2. 3. The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V. A pulse ≤ 1µs is increased to the greater of |-70V| and |VBat -40V|. RF1 and RF2 ≥ 20 Ω is also required. Pulse is supplied to TIP and RING outside RF1 and RF2. 2 PBL 386 15/1 Electrical Characteristics -40 °C ≤ TAmb ≤ +85 °C, VCC = +5V ± 5 %, VEE = -5V ± 5%, VBat = -58V to -40V, VBat2 = -22V, RLC=18.7kΩ (IL = 27 mA), RL = 600 Ω, RLD = 50 kΩ, RF1, RF2 = 0 Ω, RRef = 15kΩ, CHP = 68nF, CLP=0.47 µF, RT = 120 kΩ, RRX = 120 kΩ, Current definition: current is positive if flowing into a pin. Active state includes active normal and active reverse states unless otherwise specified. Battery definition: VBat = On-hook battery, VBat2 = Off-hook battery. Ref fig Parameter Conditions Min Typ Max Unit Two-wire port Overload level, VTRO Off-Hook, ILDC ≥ 10 mA On-Hook, ILDC ≤ 5 mA Metering ILDC ≥ 10 mA Input impedance, ZTR Longitudinal impedance, ZLoT, ZLoR Longitudinal current limit, ILoT, ILoR Longitudinal to metallic balance, BLM 2 Active state 1% THD, Note 1 1.0 1.0 0.7 ZT/200 20 VPeak VPeak VPeak 35 Ω/wire mArms /wire dB dB ZLTTX = 200 Ω, f = 16 kHz Note 2 0 < f < 100 Hz active state 12 IEEE standard 455-1985, ZTRX = 736 Ω 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 3 active state 0.2 kHz ≤ f ≤ 1.0 kHz 1.0 kHz < f < 3.4 kHz 3 active state 0.2 kHz ≤ f ≤ 1.0 kHz 1.0 kHz < f < 3.4 kHz 4 active state 0.2 kHz < f < 3.4 kHz 40 59 59 53 53 70 70 Longitudinal to metallic balance, BLME E BLME = 20 • Log Lo VTR Longitudinal to four-wire balance, BLFE E BLFE = 20 • Log Lo VTX Metallic to longitudinal balance, BMLE V BMLE = 20 • Log TR ;ERX = 0 VLo 70 70 dB dB 70 70 dB dB 58 dB C Figure 2. Overload level, VTRO, two-wire port RL VTRO ILDC TIPX VTX PBL 386 15/1 RINGX RSN RT 1 20 kΩ. If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended. VTX RTX VT ZT Z RX ZB PBL 386 15/1 Combination CODEC/Filter V RX RSN Figure 10. Hybrid function. 11 PBL 386 15/1 High-Pass Transmit Filter When CODEC/filter with a single 5 V power supply is used, it is necessary to separate the different signal reference voltages between the SLIC and the CODEC/filter. In the transmit direction this can be done by connecting a capacitor between the VTX output of the SLIC and the CODEC/filter input. This capacitor will also form, together with RTX and/or the input impedance of the CODEC/filter, a high-pass RC filter. It is recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a fast enough response for the dc steps that may occur with DTMF signaling. 1 VPeak Capacitor CLP The capacitor CLP, which connects between the terminals LP and VBAT2, positions the high end frequency break point of the low pass filter in the dc loop in the SLIC. CLP together with CHP and ZT (see section TwoWire Impedance) forms the total two wire output impedance of the SLIC. RFEED [Ω] 2•25 CLP [nF] 470 CHP [nF] 68 2.50 V 2.50 V 2.50 V Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst undersampled). During operation the influence of the adaptive overhead function will not effect the SLIC performance in the constant current region of operation (see figure 11). If, however, the SLIC is in the off-hook, constant voltage region of operation then the influence of the adaptive headroom will be apparent as a slight decrease in line voltage (and hence line current) as the SLIC adjusts to accommodate the larger (voice + metering) signal. The open loop voltage, VTRMAX, measured between the TIPX and RINGX terminals tracks the battery voltage VBAT(references J in figure 17). According to the formula: VTRMAX = | VBAT | -4.6 When the line current is approaching open loop conditions (references G in figure 17) the overhead voltage is reduced. The line voltage is kept nearly constant with a steep slope corresponding to 2x25 Ω (references H in figure 17), to ensure maximum open loop voltage, even with a leaking telephone line. Table 1. CLP and CHP values. Adaptive Overhead Voltage, AOV The Adaptive Overhead Voltage feature minimizes the power dissipation and at the same time provides a flexible solution for different system requirements and possible future changes concerning voice, metering and other signal levels. This is done by using an overhead voltage which automatically adapts to the signal level (voice + metering). The PBL38615/1 will behave as a SLIC with fixed overhead for signals in the 020kHz range and with an amplitude less than 1Vpeak. For signal amplitudes between 1VPeak and 2.5VPeak the adaptive overhead function will expand the overhead voltage making it possible for the signal to propagate through the SLIC without distortion ( This is the total sum of voice and metering signal). The expansion of the overhead occurs instantaneously. When the signal amplitude decreases, the overhead returns to its initial value with a time constant of approximately one second (see figure 11). Line Feed If VTR < | VBAT2 | -5.7 approx (See formula C in figure 17). the PBL 386 15/1 SLIC will emulate constant current feed. (references A-C in figure 17). The constant current region is adjustable between 18 mA and 30 mA. If VTR > | VBAT2 | -5.7 approx (See formula C in figure 17). the PBL 38615/1 SLIC will emulate a constant voltage feed with 2 x 25 Ω source impedance (references C-E in figure 17). This section is made as steep as possible to switch battery faster. If the loop current is less than 5.5mA then the SLIC will automatically switch to supply the DC feed via Vbat rather than Vbat2 (references E in figure 17). This will not give any disturbances on the line. Constant Current Region The constant current (reference A-C in figure 17) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation: RLC = 500 10.4 • In (ILProg • 32) ILProg ILProg Can simplifies to: 500 RLC = ILProg 12 PBL 386 15/1 Battery Switch To reduce short loop power dissipation, a second battery voltage, Off-hook, must be connected to the device via an external diode at terminal VBAT2. The SLIC automatically switches between the two battery supply voltages without need for external control. The silent battery switching to VBAT occurs when the line current is below 5.5 mA. This means that the current in the Onhook battery is limited to 6 mA. To calculate the switching voltage use this formula (See formula C in figure 17): VTR =| VB2 | -4.4 - 50 · ILProg If metering is used see section Metering Applications down below. Connect the terminal VBAT2 to the second power supply via the diode DB2 in figure 15. A diode DBB connected between VB and the VB2 power supply, see figure 15, will make sure that the SLIC continues to work on the second battery even if the first battery voltage disappears. The current commute between the different batteries as shown in figure 12, note that some current is sourced from VB (typ. 0.5 mA, internal bias current) when the line current is sourced from VB2. The next chart (figure 13) is showing what power dissipation the SLIC is using with different batteries and variation of the line. mA 30 25 20 15 IB 10 5 0 IB2 0Ω 1000Ω 2500Ω 5000Ω 7500Ω 10000Ω ∞Ω Figure 12. Chart describing current in Vbat and Vbat2. mW 800 28 V 700 600 22 V 500 400 300 200 100 0 0Ω 1000Ω 2500Ω 5000Ω 7500Ω 10000Ω ∞Ω 25 V VBAT 2 Figure 13. Chart describing Power dissipation with different Vbat2. Metering Applications, TTX It is very easy to use PBL 386 15/1 in metering applications; simply connect a suitable resistor (RTTX) in series with a capacitor (CTTX) between pin RSN and the metering source. Capacitor CTTX decouples all DC-voltages that may be superimposed on the metering signal. The metering signal gain can be calculated from the equation: G4-2TTX = VTR = VTTX where: VTTX is the wanted metering voltage between the TIP and RING terminals ZLTTX is the line impedance seen by the 12 or 16 kHz metering signal, G2-4S is the transmit gain through the SLIC, i e 0.5. It is possible to mix voice voltage and metering voltage up to 2.5 Vpeak (1.7 Vrms), using AOV. Use following formula to calculate the switching voltage of the Battery Switch to get enough signal space. VTR =| VB2 | -3.4 -Vvoice-VTTX- 50 · ILProg where: Vvoice is the voice voltage, normaly 1 Vpeak VTTX is the the metering voltage in peak. ZT . ZLTTX RTTX ZT + G2-4S . (ZLTTX + 2RF) αRSN 13 PBL 386 15/1 Silent Polarity Reversal The reversal time is set by a capacitor, Csprv, between the pin SPR and AGND. The reversal has a setup time and reversal time see figure 14. The setup time is different in Active- to Reversal-state and Reversal- to Active state but the silent polarity reversal time is the same Active- to Reversal-state and Reversal- to Active state. To calculate the silent polarity reversal time use following formula: tr =CSPR . 9500 Active- to Reversal-state and Reversalto Active state and the setup time use following formulas. Active → Reversal: tAct → Rev = CSPR . 17500 Reversal → Active: tRev → Act = CSPR . 15500 The time is measured between 10% and 90% of the line voltage. The reversal time is independent of line load and line current. C2 = 5 V, C1 = 0 V CSPR = 4.7 µF / 6V RL = 600 Ω RFEED = 2 *25 Ω Figure 14. Silent Polarity Reversal Loop Current Detector The loop current detector indicates that the telephone is off hook and that DC current is flowing in the loop by putting the output pin DET, to a logic low level when selected. The loop current detector threshold value, ILTh, where the loop current detector changes state, is programmable with the RLD resistor. RLD connects between pin PLD and ground and is calculated according to: 500 RLD = ILTh Ground Key Detector The ground key detector indicates when the ground key is pressed (active) by putting the output pin DET to a logic high level when selected. The ground key detector circuit senses the difference between TIPX and RINGX currents. The detector is triggered when the difference exceeds the current threshold. Ring Trip Detector Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced e g superimposed on the battery voltage or ground. The unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC ring relay driver connects the ringing source to tip and ring. The ring trip function is based on a polarity change at the comparator input when the line goes off-hook. In the on-hook state no dc current flows through the loop and the voltage at comparator input DT is more positive than the voltage at input DR. When the line goes off-hook, while the ring relay is energized, dc current flows and the comparator input voltage reverses polarity. Figure 15 gives an example of a ring trip detection network. This network is applicable, when the ring voltage superimposed on the battery voltage is injected on the ring lead of the two-wire port. The dc voltage across sense resistor RRT is monitored by the ring trip comparator input DT and DR via the filter network R1, R2, R3, R4, C1 and C2. DT is more positive than DR, with the line on-hook (no dc current). The DET output will report logic level high, i.e. the detector is not tripped. When the line goes off-hook, while ringing, a dc current will flow Analog Temperature Guard The widely varying environmental conditions in which SLICs operate may lead to the chip temperature limitations being exceeded. The PBL 386 15/1 SLIC reduces the dc line current and the longitudinal current limit when the chip temperature reaches approximately 145°C and increases it again automatically when the temperature drops. The detector output, DET, is forced to a logic low level when the temperature guard is active. The Active state temperature guard is exclusively viewed at detector output see section Active Temperature guard. Loop Monitoring Functions The loop current, ground key and ring trip detectors report their status through a common output, DET. The status of the detector pin, DET, is selected via the three bit control interface C1, C2 and C3. Please refer to section Control Inputs for a description of the control interface. 14 PBL 386 15/1 KR +12 V /+5V CGG PBL 386 15/1 RTX RRLY TS VTX AGND RSN DET C1 C2 C3 VCC PLD PLC SPR REF VEE NC out RT RRX RB + RING RF1 CRC VB CTC CHP HP RINGX BGND TIPX VBAT VBAT2 out CODEC/ Filter OVP TIP RF2 DB2 VB2 DBB CB2 VCC RLD RLC CSPR RREF VEE SYSTEM CONTROL INTERFACE DB VB NC PSG R1 ERG RRF RRT R2 CB CLP LP DT DR NC C1 R3 R4 C2 +5 V CVCC VCC CVEE VBAT