PBL386502SHT

June 1999 PBL 386 50/2 Subscriber Line Interface Circuit Description The PBL 386 50/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in Central Office Metering applications and other telecommunications equipment. The PBL 386 50/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 50/2 emulates resistive loop feed, programmable between 2x50 Ω and 2x900 Ω, with short loop current limiting adjustable to max 45 mA. In the current limited region the loop feed is nearly constant current with a slight slope corresponding to 2x30kΩ. A second, lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 50/2 is compatible with both loop and ground start signaling. Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable two-wire impedance, complex or real, is set by a simple external network. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 50/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC. Key Features • 24-pin SSOP package • Programmable two-wire signal headroom for 2.2 Vrms metering • High and low battery with automatic switching • Only +5 V feed in addition to battery • Selectable transmit gain (0.5x or 0.25x) • 70 mW on-hook power dissipation in active state • On-hook transmission • Long loop battery feed tracks Vbat for maximum line voltage • No power-up sequence • 43V open loop voltage @ -48V battery feed • Constant loop voltage for line leakage 10 kΩ @ -48V) • Full longitudinal current capability during on-hook state • Analog over temperature protection permits transmission while the protection circuit is active • Line voltage measurement Ring Relay Driver RRLY • Polarity reversal • Ground key detector • Tip open state with ring ground detector DT DR TIPX RINGX HP Ring Trip Comparator Input Decoder and Control C1 C2 C3 DET Ground Key Detector VCC P B L LP PLD REF VTX VBAT2 VBAT Off-hook Detector PBL 386 50/2 AGND BGND VF Signal Transmission RSN PTG 24-pin SOIC, 24-pin SSOP, 28-pin PLCC Figure 1. Block diagram. 1 38 PB 6L 50 /2 Two-wire Interface Line Feed Controller and Longitudinal Signal Suppression POV PSG PLC 38 6 50 /2 PBL 386 50/2 Maximum Ratings Parameter Symbol Min Max Unit Temperature, Humidity Storage temperature range Operating temperature range Operating junction temperature range, Note 1 Power supply, 0°C ≤ TAmb ≤ -70°C VCC with respect to A/BGND VBat2 with respect to A/BGND VBat with respect to A/BGND, continuous VBat with respect to A/BGND, 10 ms Power dissipation Continuous power dissipation at TAmb ≤ +70 °C Ground Voltage between AGND and BGND Relay Driver Ring relay supply voltage Ring trip comparator Input voltage Input current Digital inputs, outputs (C1, C2, C3, DET) Input voltage Output voltage TIPX and RINGX terminals, 0°C < TAmb < +70°C, VBat = -50V Maximum supplied TIPX or RINGX current TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3 TStg TAmb TJ VCC VBat2 VBat VBat PD VG -55 -40 -40 -0.4 VBat -75 -80 +150 +110 +140 6.5 0.4 0.4 0.4 1.5 °C °C °C V V V V W V -0,3 0,3 BGND+14 V VDT, VDR IDT, IDR VID VOD ITIPX, IRINGX VTA, VRA VTA, VRA VTA, VRA VTA, VRA VBat -5 -0.4 -0.4 AGND 5 VCC VCC +100 2 5 10 15 V mA V V -100 -80 VBat -10 VBat -25 VBat -35 mA V V V V Recommended Operating Condition Parameter Symbol Min Max Unit Ambient temperature VCC with respect to AGND VBat with respect to AGND AGND with respect to BGND TAmb VCC VBat VG 0 4.75 -65 -100 +70 5.25 -8 100 °C V V mV Notes 1. 2. 3. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability. With the diodes DVB and DVB2 included, see figure 12. RF1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2. 2 PBL 386 50/2 Electrical Characteristics 0 °C ≤ TAmb ≤ +70 °C, PTG = Open (see pin description), ROV = ∞, VCC= +5V ±5 %, VBat= -58V to -40V, VBat2 = -32V, RLC=32.4 kΩ, IL = 27 mA. RL = 600 Ω, RF1= RF2= RP1= RP2=0, RRef = 49.9 kΩ, CHP = 47 nF, CLP=0.15 µF, RT = 60 kΩ, RSG = 0 kΩ, RRX = 60 kΩ, RR = 11 kΩ unless otherwise specified. Current definition: current is positive if flowing into a pin. Parameter Ref fig Conditions Min Typ Max Unit Two-wire port Overhead voltage, VTRO ,ILdc > 18mA On-Hook, ILdc < 5mA Over load level, metering Input impedance, ZTR Longitudinal impedance, ZLOT, ZLOR Longitudinal current limit, ILOT, ILOR Longitudinal to metallic balance, BLM (IEEE standard 455-1985, ZTRX=736Ω) Longitudinal to metallic balance, BLME ELo BLME = 20 · Log VTR Longitudinal to four-wire balance, BLFE BLFE = 20 · Log ELo VTX 4 2 Active state, ROV = ∞ 0.2 kHz < f < 3.4 kHz 1% THD, Note 1 f≤16kHz, ZLAC =200Ω, Adj. by ROV Note 2 0 < f < 100 Hz active state Normal polarity: 0.2 kHz < f < 1.0 kHz 1.0 kHz < f < 3.4 kHz Reverse polarity: 0.2 kHz < f < 3.4 kHz Normal polarity: 0.2 kHz < f < 1.0 kHz 1.0 kHz < f < 3.4 kHz Reverse polarity: 0.2 kHz < f < 3.4 kHz 0.2 kHz < f < 3.4 kHz 2.7 1.1 5.0 ZT/200 20 18 55 55 55 61 61 61 40 75 70 68 50 35 VPeak VPeak VPeak Ω/wire mArms /wire dB dB dB dB dB dB dB 3 3 Metallic to longitudinal balance, BMLE VTR BMLE = 20 · Log ; ERX = 0 VLo C TIPX VTX Figure 2. Overhead voltage, VTRO, twowire port 1