AD22650-QH14NAR

ESMT AD22650 3-Vrms Cap-Less Line Driver with Adjustable Gain Features Applications  Operation Voltage: 3V to 5.5V  Cap-less Output - Eliminates Output Capacitors - Improves Low Frequency Response - Reduces POP/Clicks  Low Noise and THD - SNR > 102dB - Typical Vn < 12uVrms - THD+N < 0.02%  Maximum Output Voltage Swing into 2.5k Load - 2Vrms at 3.3V Supply Voltage - 3Vrms at 5V Supply Voltage  Differential Input  External Gain Setting from 1V/V to 10V/V  Fast Start-up Time : 0.5ms  Integrated De-Pop Control  External Under Voltage Protection  Thermal Protection  Less External Components Required  +/-8kV IEC ESD Protection at line outputs     LCD / PDP TVs CD / DVD players Set-Top Boxes Home Theater in Box Description The AD22650 is a 3-Vrms cap-less stereo line driver. The device is ideal for single supply electronics. Cap-less design can eliminate output dc-blocking capacitors for better low frequency response and save cost. The AD22650 is capable of delivering 3-Vrms output into a 2.5kΩload with 5V supply. The gain settings can be set by users from 1V/V to 10V/V externally. The AD22650 has internal and external under voltage protection to prevent POP noise. Build-in shutdown control and de-pop control sequence also help AD22650 to be a pop-less device. The AD22650 is available in a 14-pin TSSOP package. Ordering Information Product ID AD22650-QH14NAT Package Packing Comments 96 Units / Tube TSSOP-14 AD22650-QH14NAR 100 Tubes / Small Box Green(HF) 2.5k Units Tape & Reel Simplified Application Circuit Right Input Right Output AD22650 Left Output Left Input Pin Assignments Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 1/24 ESMT AD22650 TSSOP-14 (Top View) LINP 1 14 RINP LINN 2 13 RINN 12 OUTR 11 UVP OUTL 3 SGND 4 EN 5 10 PGND PVSS 6 9 PVDD CN 7 8 CP AD22650 Pin Description Type (1) No. Name Pin Description 1 LINP I Left channel OP positive input 2 LINN I Left channel OP negative input 3 OUTL O Left channel OP output 4 SGND P Signal ground 5 EN I Enable input, active high 6 PVSS P Supply voltage 7 CN I/O Charge-pump flying capacitor negative terminal 8 CP I/O Charge-pump flying capacitor positive terminal 9 PVDD P Positive supply 10 PGND P Power ground 11 UVP I Under-voltage protection input, internally pulled high 12 OUTR O Right channel OP output 13 RINN I Right channel OP negative input 14 RINP I Right channel OP positive input (1) I=input, O=output, P=power Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 2/24 ESMT AD22650 Functional Block Diagram LINP RINP LINN RINN OUTL OUTR SGND Over Temperature Protection Under Voltage Protection Depop Circuit UVP EN PGND PVSS PVDD Charge Pump CN CP Available Package Package Type Device No. Θja (℃/W)(1) Θjc (℃/W)(2) TSSOP-14 AD22650 100 32 (1) Θja is measured at room temperature (TA=25℃), natural convection environment test board, which is constructed with a thermal efficient, 2-layers PCB. The measurement is tested using the JEDEC51-3 thermal measurement standard. (2) Θjc represents the heat resistance for the heat flow between the chip and package’s top surface. Marking Information AD22650 Line 1 : LOGO Line 2 : Product No. Line 3 : Tracking Code ESMT AD22650 Tracking Code Date Code Line 4 : Date Code Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 3/24 ESMT AD22650 Absolute Maximum Ratings(1) SYMBOL PARAMETER VALUE UNIT -0.3 to 6.0 V VSS -0.3 to VDD+0.3 V 16 Ω -0.3 to VDD+0.3 V Supply Voltage, VDD to GND VI Input Voltage RL Minimum load impedance EN to GND Tstg Storage temperature range -65 to 150 ℃ TJ Maximum operating junction temperature range -40 to 150 ℃ (1) The absolute maximum ratings are limiting values of operation, safety of the device cannot be guaranteed if beyond those values. Recommended Operating Conditions SYMBOL PARAMETER Min VDD Supply Voltage VIH High Level Input Voltage EN VIL Low Level Input Voltage EN TA Operating Ambient Temperature Range -40 RL Load Resistance 16 NOM 3.0 Max UNIT 5.5 V 60 % of VDD 40 % of VDD 85 ℃ Ω Electrical Characteristics PVDD=3.3V, TA=25℃, RL=2.5kΩ, CFLY=CPVSS=1μF, CIN=1μF, RI=10kΩ, RF=20kΩ (unless otherwise noted) SYMBOL PARAMETER TEST CONDITIONS IDD VDD Supply Current EN=VDD ISD VDD Shutdown Current EN=0V, VDD =5.5V Input Current EN pin II THD+N=1%, VDD=3.3V, VO Output Voltage (Outputs In Phase) fIN=1kHz THD+N=1%, VDD=5V, fIN=1kHz THD+N=1%, VDD=5V, fIN=1kHz, RL=100k THD+N=1%, VDD=3.3V, fIN=1kHz, RL=32Ω THD+N=1%, VDD=5V, fIN=1kHz, Po Output Power RL=32Ω (Outputs In Phase) THD+N=1%, VDD=3.3V, fIN=1kHz, RL=16Ω THD+N=1%, VDD=5V, fIN=1kHz, RL=16Ω THD+N Min NOM Max UNIT 7 15 mA 5 μA 0.1 2.2 3.4 Vrms 3.5 19 53 mW 13 38 Total Harmonic VO=2Vrms, fIN=1kHz 0.002 Distortion Plus Noise Po=10mW, fIN=1kHz, RL=32Ω 0.04 Elite Semiconductor Microelectronics Technology Inc. μA % Publication Date: Sep. 2018 Revision: 1.9 4/24 ESMT AD22650 Electrical Characteristics (Con’t) PVDD=3.3V, TA=25℃, RL=2.5kΩ, CFLY=CPVSS=1μF, CIN=1μF, RI=10kΩ, RF=20kΩ (unless otherwise noted) SYMBOL THD+N Crosstalk PARAMETER Total Harmonic Distortion Plus Noise Channel Separation TEST CONDITIONS 0.06 VO=2Vrms, fIN=1kHz -110 Po=10mW, fIN=1kHz, RL=32Ω -74 11 Output Noise RI=10k, RF=10k VOS Output Offset Voltage VDD=3V to 5.5V, Input Grounded Power Supply Rejection VDD=3V to 5.5V, Vrr=200mVrms, Ratio fIN=1kHz RI RF fCP Input Resistor Range Feedback Resistor Range Charge-Pump Frequency Maximum capacitive Load VUVP NOM Po=10mW, fIN=1kHz, RL=16Ω VN PSRR Min External Under Voltage Detection Max UNIT % dB 15 μVrms 5 mV -80 -60 dB 1 10 47 kΩ 4.7 20 100 kΩ 400 500 600 kHz -5 220 pF 1.25 V 5 μA 150 ℃ 0.5 ms External Under Voltage IHYS Detection Hysteresis Current TSD Tstart-up Over Temperature Protection Level Start-up Time Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 5/24 ESMT AD22650 Typical Characteristics PVDD=3.3V, TA=25℃, RL=2.5kΩ, CFLY=CPVSS=1μF, CIN=1μF, RI=10kΩ, RF=20kΩ (unless otherwise noted)  Total Harmonic Distortion + Noise (THD+N) vs. Output Power 10 THD+N (%) 1 PVDD=3.3V R L=2.5kohm f in=1kHz 0.1 0.01 0.001 0.0001 100m 200m 500m 800m 1 2 3 4 5 2 3 4 5 Vo - Output Voltage per channel (V) 10 THD+N (%) 1 PVDD=5V R L=2.5kohm f in=1kHz 0.1 0.01 0.001 0.0001 100m 200m 500m 800m 1 Vo - Output Voltage per channel (V) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 6/24 ESMT AD22650 10 PVDD=3.3V R L=32ohm 5 f in=1kHz 2 THD+N (%) 1 0.5 0.2 0.1 0.05 0.02 0.01 300u 500u 1m 2m 5m 10m 20m 50m 80m 20m 50m 80m Po - Output Power per channel (W) 10 5 PVDD=5V R L=32ohm f in=1kHz 2 THD+N (%) 1 0.5 0.2 0.1 0.05 0.02 0.01 300u 500u 1m 2m 5m 10m Po - Output Power per channel (W) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 7/24 ESMT AD22650 10 PVDD=3.3V R L=16ohm 5 f in=1kHz 2 THD+N (%) 1 0.5 0.2 0.1 0.05 0.02 0.01 300u 500u 1m 2m 5m 10m 20m 50m 80m 20m 50m 80m Po - Output Power per channel (W) 10 5 PVDD=5V R L=16ohm f in=1kHz 2 THD+N (%) 1 0.5 0.2 0.1 0.05 0.02 0.01 300u 500u 1m 2m 5m 10m Po - Output Power per channel (W) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 8/24 ESMT AD22650  Total Harmonic Distortion + Noise (THD+N) vs. Signal Frequency 10 THD+N (%) 1 PVDD=3.3V RL=2.5kohm VO=2Vrms 0.1 CIN=1μF CIN=10μF 0.01 0.001 0.0001 20 50 100 200 500 1k 2k 5k 10k 20k fin - Input frequency (Hz) 10 THD+N (%) 1 PVDD=5V RL=2.5kohm VO=2Vrms 0.1 CIN=1μF CIN=10μF 0.01 0.001 0.0001 20 50 100 200 500 1k 2k 5k 10k 20k fin - Input frequency (Hz) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 9/24 ESMT AD22650  Phase vs. Signal Frequency +330 +280 PVDD=3.3V R L=2.5kohm VO=2Vrms Phase (deg) +230 +180 +130 +80 +30 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k 50k 100k 200k fin - Input frequency (Hz) +330 Phase (deg) +280 PVDD=5V RL=2.5kohm VO=2Vrms +230 +180 +130 +80 +30 20 50 100 200 500 1k 2k 5k 50k 100k 200k fin - Input frequency (Hz) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 10/24 ESMT AD22650  Gain vs. Signal Frequency +10 +9 +8 PVDD=3.3V R L=2.5kohm VO=2Vrms Gain (dBV) +7 +6 +5 +4 +3 +2 +1 +0 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k 10k 20k 50k 100k 200k fin - Input frequency (Hz) +10 +9 +8 PVDD=5V R L=2.5kohm VO=2Vrms Gain (dBV) +7 +6 +5 +4 +3 +2 +1 +0 20 50 100 200 500 1k 2k 5k fin - Input frequency (Hz) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 11/24 ESMT +10 +9 +8 AD22650 PVDD=3.3V RL=32ohm PO=10mW Gain (dBV) +7 +6 +5 +4 +3 +2 +1 +0 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k 10k 20k 50k 100k 200k fin - Input frequency (Hz) +10 +9 PVDD=5V RL=32ohm PO=40mW +8 Gain (dBV) +7 +6 +5 +4 +3 +2 +1 +0 20 50 100 200 500 1k 2k 5k fin - Input frequency (Hz) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 12/24 ESMT +10 +9 +8 AD22650 PVDD=3.3V RL=16ohm PO=10mW Gain (dBV) +7 +6 +5 +4 +3 +2 +1 +0 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k 10k 20k 50k 100k 200k fin - Input frequency (Hz) +10 +9 PVDD=5V RL=16ohm PO=30mW +8 Gain (dBV) +7 +6 +5 +4 +3 +2 +1 +0 20 50 100 200 500 1k 2k 5k fin - Input frequency (Hz) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 13/24 ESMT Application Information  Line Driver Amplifiers Operation A conventional inverting line-driver amplifier always requires an output dc-blocking capacitor and a bypass capacitor, see Figure 1. DC blocking capacitors are large in size and cost a lot. It also restricts the output low frequency response. POP will occur if the charge and discharge processes on output Besides, it needs to wait for a long time to charge VOUT from 0V capacitors are not carefully take cared. to VDD/2. For a cap-less line driver, see figure 2, a negative supply voltage (-VDD) is produced by the integrated charge-pump, and feeds to line driver’s negative supply instead of ground. The positive input can directly connect to ground without a CBYPASS, and VOUT is biased at ground which can eliminate the output dc-blocking capacitors. The output voltage swing is doubled compared to conventional amplifiers. RF Conventional SingleEnded Amplifier VDD VIN CIN VDD RIN COUT + VOUT VOUT VDD/2 RL GND CBYPASS Figure 1. Conventional Line Driver Amplifier RF Cap-less Solution VDD VIN CIN VDD RIN - VOUT + VOUT GND RL -VDD -VDD Figure 2. Cap-less Line Driver Amplifier Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 14/24 ESMT  External Under-Voltage Protection The external under-voltage protection is used to mute the line-driver before any input voltage change to generate a POP. The threshold of UVP pin is designed to 1.25V. By using a resistor divider, users can decide the UVP level and hysteresis level. The levels can be obtained by following equations: VUVP = (1.25V − 6µA × R13) × (R11 + R12) / R12 Hysteresis = 5µA × R13 × (R11 + R12) / R12 With the condition R13 >> (R11 // R12). For example, to obtain VUVP=2.67V, Hysteresis=0.37V, R11=1.5kΩ, R12=1kΩ, R13=30kΩ. VSYSTEM R11 R13 UVP R12 Figure 3-1. Application Circuit of UVP Pin The UVP pin voltage ripple needs to take care during chip enable state within 2mS. The UVP pin ripple lower 1.25V~1.475V by 2~4 times will trigger test mode in Line Driver. To put a capacitor parallel with UVP pin can improve test mode mis-operating triggered while VSTSTEM is not stable during power up initially. VUVP pin voltage threshold 1.475V is necessary. 2mS EN Power on sequence for Line Driver UVP pin is pulled high internally, and therefore it can be floated to disable the external under-voltage protection feature. Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 15/24 ESMT  Charge-Pump Operation The charge-pump is used to generate a negative supply voltage to supply to line-driver. It needs two external capacitors, CFLY and CPVSS, for normal operation, see figure 4 (a). The operation can be analyzed with two phase. In phase I, see figure 4 (b), CFLY is charged to PVDD, and in phase II, see figure 4 (c), the charges on CFLY are shared with CPVSS, that makes PVSS a negative voltage. After an adequate clock cycles, PVSS will be equaled to –PVDD. Low ESR capacitors are recommended, and the typical value of CFLY and CPVSS is 1μF. A smaller capacitance can be used, but the maximum output voltage may be reduced. PVDD Req C FLY CP CFLY CN CP CP PVSS CFLY CN CN + PVDD C PVSS + PVDD CPVSS (a) PVSS (b) + PVDD - PVDD (c) Figure 4. Charge-Pump Operation  Enable Function The enable function is used to reduce power consumption while the device is not in use. When a logic low is applied to this pin, the overall circuits are turned off. Line driver output and PVSS are pulled to ground. When a logic high is applied to enable pin, the PVSS is started to build-up and line driver output signal is released after about 0.5ms typically.  Decoupling Capacitors A low ESR power supply decoupling capacitor is required for better performance. The capacitor should place as close to chip as possible, the value is typically 1μF. For filtering low frequency noise signals, a 10μF or greater capacitor placed near the chip is recommended.  Input Blocking Capacitors (CIN) An input blocking capacitor is required to block the dc voltage of the audio source and allows the input to bias at a proper dc level for optimum operation. The input capacitor and input resistor (RI) form a high-pass filter with the corner frequency determined as following equation: fC = 1 2πRI C IN Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 16/24 ESMT  Gain Setting Resistors (RI and RF) The line driver’s gain is determined by RI and RF. The typical configurations of the amplifier are inverting, non-inverting, and differential input, see figure 5. The gain equations are listed as follows: (a) Inverting configuration : AV = − RF RI (b) Non-inverting configuration : AV = 1 + © Differential-input configuration : AV = RF RI RF RI RF RF RF RI CIN IN- RI CIN RI CIN RI OUT IN OUT OUT CIN IN (a) Inverting Input RF IN+ (b) Non-inverting Input (c) Differential Input Figure 5. Line Driver Amplifier Configurations The values of RI and RF must be chosen with consideration of stability, frequency response and noise. The recommended value of RI is in the range from 1kΩ to 47kΩ, and RF is from 4.7kΩ to 100kΩ for. The gain is in the range from -1V/V to -10V/V for inverting configuration. Table 1 lists the recommended resistor values for different configurations. Inverting Input Non-inverting Differential Input Gain (V/V) Input Gain (V/V) Gain (V/V) 22 -1 2 1 15 30 -2 3 2 33 68 -2.1 3.1 2.1 10 100 -10 11 10 RI (kΩ) RF (kΩ) 22 Table 1. Recommended Resistor Values Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 17/24 ESMT  Second-Order Filter Configuration AD22650 can be used like a standard OPAMP. Several filter topologies can be implemented by using AD22650, both single-ended and differential input configuration, see figure 6. For inverting input 1 R2 , the high-pass filter’s cutoff frequency is , the R1 2πR1C 3 configuration, the overall gain is − low-pass filter’s cutoff frequency is 1 , The detail component values are listed on table 2π R 2 R3C1C 2 2. R2 C1 R2 IN- C3 R1 R3 C1 C3 IN R1 C2 R3 OUT C2 IN+ OUT C3 R1 R3 R2 C1 (a) Inverting Input (b) Differential Input Figure 6. Second-order Active Low-Pass Filter High Low Pass Pass (Hz) (kHz) -1 1.6 -1.5 Gain C1 (pF) C2 (pF) C3 (μF) R1 (kΩ) R2 (kΩ) R3 (kΩ) 40 100 680 10 10 10 24 1.3 40 68 680 15 8.2 12 30 -2 1.6 60 33 150 6.8 15 30 47 -2 1.6 30 47 470 6.8 15 30 43 -3.33 1.2 30 33 470 10 13 43 43 -10 1.5 30 22 1000 22 4.7 47 27 (V/V) Table 2. Second-order Low-Pass Filter Specifications  Over-Temperature Protection AD22650 provide an over-temperature protection to limit the junction temperature to 150℃. As junction temperature exceeds 150℃, internal thermal sensor will turn off the drivers immediately. The drivers will turn on again if the junction temperature is smaller than 130℃. A 20℃ hysteresis is designed to lower the average junction temperature during continuous thermal overload conditions, increasing lifetime of the chip. Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 18/24 ESMT Typical Application Circuit  Inverting Input Line Driver Amplifier VSYSTEM RL R12 1.5kΩ 1kΩ 10kΩ RINN 1μF R13 30kΩ CFLY 1μF 1μF CN CPVSS L-ch Output 1μF Enable Control 10kΩ RI CIN PVSS EN OUTL LINN LINP RF 20kΩ L-ch Input SGND Over Temperature Protection Depop Circuit Charge Pump Under Voltage Protection RINP R-ch Output OUTR RF CP 20kΩ PVDD R-ch Input 10μF LDO R11 2.5kΩ RI UVP 1μF PGND CIN 2.5kΩ RL  Non-inverting Input Line Driver Amplifier VSYSTEM CIN 1μF RI RL 10kΩ 10μF LDO R11 2.5kΩ R12 1.5kΩ 1kΩ CIN 1μF 1μF R13 CFLY 1μF L-ch Input RF 20kΩ CN CPVSS L-ch Output 1μF PVSS EN SGND LINN LINP RX OUTL Over Temperature Protection Depop Circuit Charge Pump Under Voltage Protection CP PVDD 30kΩ UVP RINN RINP RX R-ch Output OUTR RF PGND 20kΩ R-ch Input 1μF Enable Control CIN 2.5kΩ 1μF CIN 10kΩ RI RL Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 19/24 ESMT  Differential Input Line Driver Amplifier CIN R-ch Input VSYSTEM RI 1μF 10kΩ RL CIN 10μF LDO R11 2.5kΩ 1μF R12 1.5kΩ 1kΩ R-ch Output CP PVDD CFLY 1μF 10kΩ RF RI 20kΩ CN PVSS EN OUTL LINN RF LINP 20kΩ SGND Over Temperature Protection Depop Circuit Charge Pump Under Voltage Protection UVP RINN 1μF R13 30kΩ PGND RF OUTR 20kΩ RINP RF 20kΩ RI 10kΩ CPVSS L-ch Output 1μF Enable Control L-ch Input 1μF 2.5kΩ CIN RL 10kΩ 1μF RI CIN  Inverting Input Second-Order Active Low-Pass Filter (load support >= 600Ω only) R-ch Output VSYSTEM 30kΩ R2 43kΩ R12 1.5kΩ 1kΩ PGND 1μF CFLY 1μF 1μF C2 6.8uF C3 CN CPVSS 470pF L-ch Input PVSS EN SGND LINP LINN OUTL Over Temperature Protection Depop Circuit Charge Pump Under Voltage Protection UVP R13 30kΩ OUTR C2 470pF CP 15kΩ 10μF LDO R11 C1 47pF PVDD R3 RINP R-ch Input R1 RINN C3 6.8uF 15kΩ 43kΩ R1 R3 47pF Enable Control C1 R2 30kΩ L-ch Output Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 20/24 ESMT  Differential Input Second-Order Active Low-Pass Filter (load support >= 600Ω only) R-ch Output 30kΩ VSYSTEM R2 C3 6.8uF C1 R1 R3 15kΩ 43kΩ 10μF LDO R11 47pF R12 1.5kΩ 1kΩ R-ch Input C2 R3 470pF 43kΩ 1μF R13 30kΩ CP PVDD PGND CFLY 1μF C3 R1 R2 CN PVSS EN SGND 30kΩ 47pF OUTL 15kΩ LINN 6.8uF LINP Over Temperature Protection Depop Circuit Charge Pump Under Voltage Protection UVP C1 OUTR R2 30kΩ 47pF RINN R1 15kΩ RINP C3 6.8uF C1 CPVSS L-ch Input 470pF 6.8uF C3 1μF 43kΩ C2 R3 15kΩ 43kΩ R1 R3 Enable Control 47pF C1 R2 30kΩ L-ch Output Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 21/24 ESMT Package Outline Drawing TSSOP-14L 14 13 12 11 10 9 8 E 1 2 3 4 5 6 DETAIL A E1 7 C TOP VIEW D A A1 b e SIDE VIEW Symbol A A1 b c D E E1 e L L DETAIL A Dimension in mm Min Max -1.20 0.05 0.15 0.19 0.30 0.09 0.16 4.90 5.10 4.30 4.50 6.30 6.50 0.65 BSC 0.45 0.75 Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 22/24 ESMT Revision History Revision Date Description 0.1 2011.11.02 Initial version 0.2 2011.12.15 Modify the ordering information 0.3 2012.03.29 Modify the description of TJ in Absolute Maximum Ratings Remove the description of TJ in Recommended Operating Conditions 1.0 2012.09.14 Remove “Preliminary” 1.1 2012.12.14 Modify the Pin Description 1.2 2013.05.06 1.3 2013.06.17 Modify the minimum VIH and maximum VIL of EN 1.4 2013.07.18 Modify ISD max spec from 100uA to 5uA with VDD =5.5V 1.5 2014.02.11 Modify TA from 0~70’C to -40~85’C 1.6 2015.03.11 Change minimum load from 600ohm to 16ohm Add 16 and 32ohm data into Electrical Characteristics and Typical Characteristics Modify Package Outline Drawing 1.7 2016.02.15 Added UVP description into datasheet. 1.8 2018.01.04 Update typical application circuit 1.9 2018.09.07 Update UVP description. Modify the Pin Description and the External Under Voltage Protection Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 23/24 ESMT Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Microelectronics Technology Inc. Publication Date: Sep. 2018 Revision: 1.9 24/24