AD6255A

ESMT Features Compliant with USB Specification v1.1, and USB 2.0 full speed Embedded high efficiency, high performance class D stereo amplifier Support I2S input and I2S output interface of master mode Sampling frequencies(Fs)：48kHz +6dB enhancement(Theater function) Support recording function Support both bus-powered and self-powered operation Supports Win Me//2000/XP and MacOS True plug-and-play application, no driver is required for basic USB speaker application Support volume/mute control with external button Built-in 5V to 3.3V regulator for internal device operation Total efficiency 80% for 8Ω load @ -1dB 1kHz sine wave input Loudspeaker PSNR & DR (A-weighting) 80dB (PSNR), 78dB (DR) with Bead filter AD6255A Class-D Audio Power Amplifier with USB / I2S Interface and Recording function 82dB (PSNR), 78dB (DR) with Chock filter Anti-pop design Over-temperature protection Under-voltage shutdown Short-circuit detection 12 MHz Crystal Input 32-pin LQFP(Pb free) Description AD6255A is a single chip of Class-D audio amplifier with USB/I2S interface and supports recording function. When using the power supplied from the USB port, AD6255A can drive a pair of up to 1W speakers due to the built-in, high efficiency and high performance class D amplifiers. The device also has an I2S input port and I2S output port. The I2S input port allows other external audio sources to use the class D amplifier to share the speakers. The I2S output port allows other high performance audio device (i.e. AD8356A/AD8256A) to be controlled by AD6255A. Functional Block Diagram Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.3 1/15 ESMT Pin Assignment AD6255A Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name MSDA MSCL PDO Type I/O O O O O O I O P O O P P O O 2 2 Description I C’s SDA of Master mode I C’s SCL of master mode Power-down output (Note1) Serial audio output (Note1) L/R clock output(Fs) (Note1) BCLK output(64xFs) (Note1) Serial audio data input Master clock(256xFs) Ground for right channel Right channel outputRight channel output+ Supply for right channel Supply for left channel Left channel output+ Left channel output- Characteristics Schmitt trigger TTL input buffer SDATAO LRCIN BCLK SDATAI MCLK GNDR RB RA VDDR VDDL LA LB Schmitt trigger TTL input buffer Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.3 2/15 ESMT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GNDL USB/I S 2 AD6255A P I I I O I P O P I/O I/O I I I I O I Ground for left channel Low is USB mode, high is I2S mode Mode selection bit 1 Mode selection bit 0 Crystal output Crystal input Ground 3.3V regulator output 5V supply voltage USB data DUSB data D+ Theater mode, high active Volume down, low active Volume up, low active Power-down and mute of Class D Error output Reset signal Schmitt trigger TTL input buffer With internal pull-up resistor With internal pull-up resistor Schmitt trigger TTL input buffer Open-Drain output Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer SEL1 SEL0 XO XI GND REGO VDD USBDM USBDP THEATER VOLDN VOLUP MUTE ERROR RESET Note1: Must be strapped resistor 1MΩ to 3.3V(REGO) or GND. BCLK, LRCIN and PDO must be strapped to GND. SDATAO is strapped by 1MΩ to GND when AD6255A’s volume/mute is controlled by external button, otherwise strapped by 1MΩ to 3.3V when AD6255A is I2C slave mode for SEL1 is logic LOW. Absolute Maximum Ratings Symbol VDD VDDL(R) Vi Tstg Ta Parameter Supply for regulator input Supply for Left (Right) Channel Input Voltage Storage Temperature Ambient Operating Temperature Voltage Difference between VDDL and VDDR Voltage Difference between VDDL(VDDR) and DVDD/AVDD VDDL(VDDR) Power-on Voltage Ramp Min 0 0 -0.3 -65 0 -1 -3 Max 5.5 5.5 3.6 150 70 1 3 0.2 Units V V V o C o C V V V/μs Recommended Operating Conditions Symbol VDD VDDL(R) Ta Parameter Supply for regulator input Supply for Driver Stage Ambient Operating Temperature Typ 4.5~5.5 3.0~5.0 0~70 Units V V o C Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.3 3/15