F25L004A-100PG

ESMT 4Mbit (512Kx8) F25L004A 3V Only Serial Flash Memory FEATURES Single supply voltage 2.7~3.6V Speed - Read max frequency : 33MHz - Fast Read max frequency : 50MHz; 75MHz; 100MHz Low power consumption - typical active current - 15 μ A typical standby current Reliability - 100,000 typical program/erase cycles - 20 years Data Retention Program - Byte program time 7 μ s(typical) Erase - Chip erase time 4s(typical) - Sector erase time 60ms(typical), block erase time 1sec (typical) Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte-Program operations SPI Serial Interface - SPI Compatible : Mode 0 and Mode3 End of program or erase detection Write Protect ( WP ) Hold Pin ( HOLD ) Package available - 8-pin SOIC 150-mil - 8-pin SOIC 200-mil ORDERING INFORMATION Part No. F25L004A -50PG Speed 50MHz Package 8 lead SOIC 8 lead SOIC 8 lead SOIC 150 mil 150 mil 200 mil COMMENTS Pb-free Pb-free Pb-free Part No. Speed Package 8 lead SOIC 8 lead PDIP 8 lead PDIP 200 mil 300 mil 300 mil COMMENTS Pb-free Pb-free Pb-free F25L004A –100PAG 100MHz F25L004A –50DG 50MHz F25L004A -100PG 100MHz F25L004A -50PAG 50MHz F25L004A –100DG 100MHz GENERAL DESCRIPTION The F25L004A is a 4Megablt, 3V only CMOS Serial Flash memory device organized as 512K bytes of 8 bits. This device is packaged in 8-lead SOIC 200mil. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles. The F25L004A features a sector erase architecture. The device memory array is divided into 128 uniform sectors with 4K byte each ; 8 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 1/32 ESMT PIN CONFIGURATIONS 8-PIN SOIC F25L004A 0 CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI 8-PIN PDIP CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 2/32 ESMT PIN Description Symbol SCK SI Pin Name Serial Clock Serial Data Input Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. F25L004A SO CE WP Serial Data Output Chip Enable Write Protect HOLD VDD VSS Hold Power Supply Ground Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 3/32 ESMT SECTOR STRUCTURE F25L004A Table1 : F25L004A Sector Address Table Block 7 Sector 127 : 112 111 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB Address range 07F000H – 07FFFFH : 070000H – 070FFFH 06F000H – 06FFFFH : 060000H – 060FFFH 05F000H – 05FFFFH : 050000H – 050FFFH 04F000H – 04FFFFH : 040000H – 040FFFH 03F000H – 03FFFFH : 030000H – 030FFFH 02F000H – 02FFFFH : 020000H – 020FFFH 01F000H – 01FFFFH : 010000H – 010FFFH 00F000H – 00FFFFH : 000000H – 000FFFH Block Address A18 A17 A16 1 1 1 6 : 96 95 1 1 0 5 : 80 79 1 0 1 4 : 64 63 1 0 0 3 : 48 47 0 1 1 2 : 32 31 0 1 0 1 : 16 15 0 0 1 0 : 0 0 0 0 Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 4/32 ESMT Table2 : F25L004A Block Protection Table TOP Protection Level 0 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks All Blocks 0 0 0 0 1 1 1 1 Status Register Bit BP2 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protected Memory Area Block Range None Block 7 Block 6~7 Block 4~7 Block 0~7 Block 0~7 Block 0~7 Block 0~7 Address Range None 70000H – 7FFFFH 60000H – 7FFFFH 40000H – 7FFFFH 00000H – 7FFFFH 00000H – 7FFFFH 00000H – 7FFFFH 00000H – 7FFFFH F25L004A BOTTOM Protection Level 0 Bottom 1/8 Bottom 1/4 Bottom 1/2 All Blocks All Blocks All Blocks All Blocks 0 0 0 0 1 1 1 1 Status Register Bit BP2 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protected Memory Area Block Range None Block 0 Block 0~1 Block 0~3 Block 0~7 Block 0~7 Block 0~7 Block 0~7 Address Range None 00000H – 0FFFFH 00000H – 1FFFFH 00000H – 3FFFFH 00000H – 7FFFFH 00000H – 7FFFFH 00000H – 7FFFFH 00000H – 7FFFFH Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP2, P1, BP0 bits as long as WP is high or the Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1. Block Protection Lock-Down (BPL) WP pin driven low (VIL), enables the Block-Protection -Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 5/32 ESMT FUNTIONAL BLOCK DIAGRAM F25L004A Address Buffers and Latches X-Decoder Flash Y-Decoder Control Logic I/O Butters and Data Latches Serial Interface CE SCK SI SO WP HOLD Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 6/32 ESMT Hold Operation HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not F25L004A coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 18 for Hold timing. S CK HO L D A ctive Ho ld A ctive Ho ld A ctive Figure 1 : HOLD CONDITION WAVEFORM Write Protection F25L004A provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description. TABLE3: CONDITIONS TO EXECUTE WRITE-STATUS- REGISTER (WRSR) INSTRUCTION WP BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed L L Write Protect Pin ( WP ) The Write Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP is high, the lock-down function of the BPL bit is disabled. H Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 7/32 ESMT Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, F25L004A the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. TABLE 4: SOFTWARE STATUS REGISTER Bit 0 1 2 3 4 5 6 7 Name BUSY WEL BP0 BP1 BP2 RESERVED AAI BPL Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP2,BP1,BP0 are read-only bits 0 = BP2,BP1,BP0 are read/writable Default at Power-up 0 0 1 1 1 0 0 0 Read/Write R R R/W R/W R/W N/A R R/W Note1 : Only BP0,BP1,BP2 and BPL are writable Note2 : All register bits are volatility Note3 : All area are protected at power-on (BP2=BP1=BP0=1) Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming reached its highest memory address • Sector-Erase instruction completion • Block-Erase instruction completion • Chip-Erase instruction completion • • • • • Write-Status-Register instructions Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 8/32 ESMT Instructions Instructions are used to Read, Write (Erase and Program), and configure the F25L004A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of F25L004A SCK starting with the most significant bit. CE must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first TABLE 5: DEVICE OPERATION INSTRUCTIONS Cycle Type/ 1,2 Operation Read High-Speed-Read Sector-Erase4,5 (4K Byte) Block-Erase (64K Byte) Chip-Erase6 Byte-Program Auto-Address-Increment-word programming (AAI) Read-Status-Register (RDSR) Enable-Write-Status-Register (EWSR)8 Write-Status-Register (WRSR)8 Write-Enable (WREN) 11 Write-Disable (WRDI) Read-Electronic-Signature (RES) Jedec-Read-ID (JEDEC-ID) 10 Read-ID (RDID) Enable SO to output RY/BY# Status during AAI (EBSY) Disable SO to output RY/BY# Status during AAI (DBSY) 1. 2. 3. 4. 5. 6. 7. 8. 100MHz 5 Max Freq 33 MHz 1 SIN 03H 0BH 20H D8H 60H C7H 02H ADH SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2 SIN A23-A16 A23-A16 A23-A16 A23-A16 SOUT Hi-Z Hi-Z Hi-Z Hi-Z - Bus Cycle 3 SIN SOUT A15-A8 Hi-Z A15-A8 Hi-Z A15-A8 Hi-Z A15-A8 Hi-Z Hi-Z Hi-Z Note7 20H(Top) 21H(Bottom) Hi-Z - 4 5 6 SIN SOUT SIN SOUT SIN SOUT A7-A0 Hi-Z X DOUT A7-A0 Hi-Z X X X DOUT A7-A0 Hi-Z A7-A0 Hi-Z DIN Hi-Z A7-A0 Hi-Z Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z X Data X X DOUT Hi-Z 12H 8CH X A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z -. X Note7 13H X Note7 8CH 12H X 12H 8CH 50MHz 05H 50H 01H 06H 04H ABH 9FH 90H (A0=0) Hi-Z A23-A16 Hi-Z A15-A8 90H (A0=1) 70H 80H Hi-Z Hi-Z - A7-A0 Hi-Z - Operation: SIN = Serial In, SOUT = Serial Out X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary) One bus cycle is eight clock periods. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be executed. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be programmed. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. 9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . 10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type and second byte 21H as Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 9/32 ESMT F25L004A bottom memory type ; third byte 13H as memory capacity. 11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN. Read (33 MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. CE MODE3 SCK MODE1 12345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70 SI MSB 03 ADD. MSB ADD. ADD. SO HIGH IMPENANCE MSB N DOUT N+1 DOUT N+2 DOUT N+3 DOUT N+4 D OUT Figure 2 : READ SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 10/32 ESMT Fast-Read (50 MHz ; 100 MHz) The High-Speed-Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE must remain active low for the duration of the High-Speed-Read cycle. See Figure 3 for the High-Speed-Read sequence. Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous F25L004A through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH has been read, the next output will be from address location 000000H. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI MSB 0B ADD. MSB HIGH IMPENANCE ADD. ADD. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT SO Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 3 : HIGH-SPEED-READ SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 11/32 ESMT Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Byte-Program instruction. The Byte-Program F25L004A instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 4 for the Byte-Program sequence. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 SI MSB 02 ADD. MSB HIGH IMPENANCE ADD. ADD. DIN MSB LSB SO Figure 4 : BYTE-PROGRAM SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 12/32 ESMT Auto Address Increment (AAI) WORD Program F25L004A The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware detection by reading the SO; software detection by polling the BUSY in the software status register or wait TBP. Refer to End-of-Write Detection section for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data is input sequentially. The data is input sequentially from MSB (bit 7) to LSB (bit 0). The first byte of data(DO) will be programmed into the initial address [A23-A1] with A0 =0; The second byte of data(D1) will be programmed into the initial address [A23-A1] with A0 =1. CE must be driven high before the AAI WORD program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the WRDI instruction, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command. Please refer to Figures 7 and Figures 8. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0). End of Write Detection There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The hardware end of write detection method is described in the section below. Hardware End of Write Detection The hardware end of write detection method eliminates the overhead of polling the BUSY bit in the software status register during an AAI Word PROGRAM OPERATION. The 8bit command, 70H, configures the SO to indicate Flash Busy status during AAI WORD programming (refer to figure5). The 8bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A “0” Indicates the device is busy ; a “1” Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to tri-state. The 8bit command, 80H,disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output software register data during AAI WORD programming (refer to figure6). FIGURE 5 : ENABLE SO AS HARDWARE RY / BY DURING AAI PROGRAMMING FIGURE 6 : DISABLE SO AS HARDWARE RY / BY DURING AAI PROGRAMMING Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 13/32 ESMT F25L004A FIGURE 7 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION FIGURE 8 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 14/32 ESMT 64K-Byte Block-Erase The 64K Byte Block-Erase instruction clears all bits in the selected block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits F25L004A [A23-A0]. Address bits [AMS-A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence. FIGURE 9 : 64-KBYTE BLOCK-ERASE SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 15/32 ESMT 4K-Byte-Sector-Erase The Sector-Erase instruction clears all bits in the selected sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits F25L004A [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 10 for the Sector-Erase sequence. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 SI MSB 20 ADD. MSB HIGH IMPENANCE ADD. ADD. SO FIGURE 10 : SEQUENCE-ERASE SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 16/32 ESMT Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, F25L004A 60H or C7H. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 11 for the Chip-Erase sequence. CE MODE3 SCK MODE0 01234567 SI MSB 60 or C7 SO HIGH IMPENANCE FIGURE 11 : CHIP-ERASE SEQUENCE Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE See Figure 12 for the RDSR instruction sequence. CE MODE3 SCK MODE1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SI MSB HIGH IMPENANCE 05 SO Bit7 MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out Figure12 : READ-STATUS-REGISTER (RDSR) SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 17/32 ESMT Write-Enable (WREN) The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE must be driven high before the WREN instruction is executed. F25L004A CE MODE3 SCK MODE0 01234567 SI MSB 06 SO HIGH IMPENANCE FIGURE 13 : WRITE ENABLE (WREN) SEQUENCE Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. CE must be driven high before the WRDI instruction is executed. CE MODE3 SCK MODE0 01234567 SI MSB 04 SO HIGH IMPENANCE Figure 14 : WRITE DISABLE (WRDI) SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 18/32 ESMT Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. F25L004A Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 15 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lockdown the status register, but cannot be reset from “1” to “0”. When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions. CE MODE3 SCK MODE0 STATUS REGISTER IN 76543210 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 SI MSB 50 or 06 MSB HIGH IMPENANCE 01 SO Figure 15 : ENABLE-WRITE-STATUS-REGISTER (EWSR) or WRITE-ENABLE(WREN) and WRITE-STATUS-REGISTER (WRSR) Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.2 19/32 ESMT ELECTRICAL SPECIFICATIONS F25L004A Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (