F25L08PA-100PAG

ESMT Flash FEATURES Single supply voltage 2.7~3.6V Standard, Dual SPI Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 100MHz (100MHz / 200MHz equivalent Dual SPI) Low power consumption - Active current: 35 mA - Standby current: 30 μ A Reliability - 100,000 typical program/erase cycles - 20 years Data Retention Program - Byte programming time: 7 μ s (typical) - Page programming time: 1.5 ms (typical) Erase - Chip erase time 10 sec (typical) - Block erase time 1 sec (typical) - Sector erase time 90 ms (typical) Page Programming - 256 byte per programmable page F25L08PA 3V Only 8 Mbit Serial Flash Memory with Dual Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte Program operations Lockable 4K bytes OTP security sector SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 End of program or erase detection Write Protect ( WP ) Hold Pin ( HOLD ) All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID F25L08PA –50PG F25L08PA –100PG F25L08PA –50PAG F25L08PA –100PAG F25L08PA –50DG F25L08PA –100DG Speed 50MHz 100MHz 50MHz 100MHz 50MHz 100MHz Package 8 lead SOIC 8 lead SOIC 8 lead SOIC 8 lead SOIC 8 lead PDIP 8 lead PDIP 150mil 150mil 200mil 200mil 300mil 300mil COMMENTS Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free GENERAL DESCRIPTION The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 4,096 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device also can be programmed to decrease total chip programming time with Auto Address Increment (AAI) programming. The device features sector erase architecture. The memory array is divided into 256 uniform sectors with 4K byte each; 16 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 1/32 ESMT PIN CONFIGURATIONS F25L08PA 8-PIN SOIC CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI 8-PIN PDIP CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 2/32 ESMT PIN DESCRIPTION Symbol SCK SI Pin Name Serial Clock Serial Data Input Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. F25L08PA SO CE WP Serial Data Output Chip Enable Write Protect HOLD VDD VSS Hold Power Supply Ground FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches X-Decoder Flash Y-Decoder Control Logic I/O Butters and Data Latches Serial Interface CE SCK SI SO WP HOLD Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 3/32 ESMT SECTOR STRUCTURE Table 1: F25L08PA Sector Address Table Block Sector 255 15 : 240 239 14 : 224 223 13 : 208 207 12 : 192 191 11 : 176 175 10 : 160 159 9 : 144 143 8 : 128 127 7 : 112 111 6 : 96 95 5 : 80 79 4 : 64 63 3 : 48 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB Address range 0FF000H – 0FFFFFH : 0F0000H – 0F0FFFH 0EF000H – 0EFFFFH : 0E0000H – 0E0FFFH 0DF000H – 0DFFFFH : 0D0000H – 0D0FFFH 0CF000H – 0CFFFFH : 0C0000H – 0C0FFFH 0BF000H – 0BFFFFH : 0B0000H – 0B0FFFH 0AF000H – 0AFFFFH : 0A0000H – 0A0FFFH 09F000H – 09FFFFH : 090000H – 090FFFH 08F000H – 08FFFFH : 080000H – 080FFFH 07F000H – 07FFFFH : 070000H – 070FFFH 06F000H – 06FFFFH : 060000H – 060FFFH 05F000H – 05FFFFH : 050000H – 050FFFH 04F000H – 04FFFFH : 040000H – 040FFFH 03F000H – 03FFFFH : 030000H – 030FFFH 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Block Address A19 A18 A17 A16 F25L08PA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 4/32 ESMT Table 1: F25L08PA Sector Address Table - Continued Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB Block Address A19 A18 0 0 A17 1 A16 0 Block Sector 47 2 : 32 31 1 : 16 15 0 : 0 Address range 02F000H – 02FFFFH : 020000H – 020FFFH 01F000H – 01FFFFH : 010000H – 010FFFH 00F000H – 00FFFFH : 000000H – 000FFFH 0 0 0 0 0 0 0 1 F25L08PA STATUS REGISTER The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the software status register. Table 2: Software Status Register Bit 0 1 2 3 4 5 6 7 Note: 1. Only BP0, BP1, BP2 and BPL are writable. 2. All register bits are volatility 3. All area are protected at power-on (BP2=BP1=BP0=1) Name BUSY WEL BP0 BP1 BP2 RESERVED AAI BPL Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Page Program mode 1 = BP2,BP1,BP0 are read-only bits 0 = BP2,BP1,BP0 are read/writable Default at Power-up 0 0 1 1 1 0 0 0 Read/Write R R R/W R/W R/W N/A R R/W Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 5/32 ESMT WRITE ENABLE LATCH (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If this bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions: • • • • • • • • Power-up Write Disable (WRDI) instruction completion Page Program instruction completion Auto Address Increment (AAI) Programming is completed and reached its highest unprotected memory address Sector Erase instruction completion Block Erase instruction completion Chip Erase instruction completion Write Status Register instructions F25L08PA BUSY The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Auto Address Increment (AAI) The Auto-Address-Increment-Programming-Status bit provides status on whether the device is in AAI Programming mode or Page Program mode. The default at power up is Page Program mode. Table 3: F25L08PA Block Protection Table Protection Level 0 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks 0 0 0 0 1 1 1 1 Status Register Bit BP2 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protected Memory Area Block Range None Block 15 Block 14~15 Block 12~15 Block 8~15 Block 0~15 Block 0~15 Block 0~15 Address Range None F0000H – FFFFFH E0000H – FFFFFH C0000H – FFFFFH 80000H – FFFFFH 00000H – FFFFFH 00000H – FFFFFH 00000H – FFFFFH Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table 3, to be software protected against any memory Write (Program or Erase) operations. The Write Status Register (WRSR) instruction is used to program the BP2, BP1, BP0 bits as long as WP is high or the BlockProtection-Look (BPL) bit is 0. Chip Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1. Block Protection Lock-Down (BPL) WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 6/32 ESMT HOLD OPERATION HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not coincide with the SCK active low state, then the device exits in F25L08PA Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 26 for Hold timing. S CK HO L D A ctive Ho ld A ctive Ho ld A ctive Figure 1: HOLD Condition Waveform WRITE PROTECTION F25L08PA provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 3 for Block-Protection description. Table 4: Conditions to Execute Write-Status-Register (WRSR) Instruction WP BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed L L H Write Protect Pin ( WP ) The Write-Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write Status Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4). When WP is high, the lock-down function of the BPL bit is disabled. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 7/32 ESMT INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25L08PA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Auto Address Increment (AAI) Programming, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE must be driven F25L08PA low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. Table 5: Device Operation Instructions Operation Read Fast Read Fast Read Dual 12,13 Output Sector Erase4 (4K Byte) Block Erase4, (64K Byte) Chip Erase Page Program (PP) Auto Address Increment word programming5 (AAI) Read Status Register 6 (RDSR) Enable Write Status 7 Register (EWSR) 50MHz Write Status Register 7 (WRSR) Write Enable (WREN) 10 Write Disable (WRDI)/ Exit secured OTP mode Enter secured OTP mode (ENSO) 100MHz Read Electronic 8 Signature (RES) RES in secured OTP mode & not lock down RES in secured OTP mode & lock down Jedec Read ID 9 (JEDEC-ID) Read ID (RDID) 11 Enable SO to output RY/ Status during AAI (EBSY) Disable SO to output Status during AAI RY/ (DBSY) Max. Freq Bus Cycle 1~3 4 SOUT SIN SOUT SIN SOUT SIN Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X 3 A15-A8 A7-A0 DIN0 DIN0 X X - 1 2 SOUT SIN Hi-Z A23-A16 Hi-Z A23-A16 5 SOUT DOUT0 X X Hi-Z Hi-Z 8CH 13H DIN1 DIN1 X X SIN X X 6 SOUT DOUT1 DOUT0 Hi-Z Hi-Z 13H 8CH SIN N SOUT SIN 33 MHz 03H 0BH 20H D8H 60H / C7H 02H ADH 05H 50H 01H 06H 04H B1H ABH ABH ABH 9FH 90H 70H X X - cont. cont. - 3BH A23-A16 DOUT0~1 cont. Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z - Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z X DIN X X X X 00H DOUT Hi-Z 13H 33H 73H 8CH Hi-Z X 00H 20H Hi-Z -. -. -. -. X 00H 01H 14H Hi-Z Hi-Z - Up to 256 Hi-Z bytes - 80H Hi-Z - - - - - - - - - - - - Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 8/32 ESMT Note: 1. 2. 3. 4. 5. 6. 7. F25L08PA Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous One bus cycle is eight clock periods. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be programmed. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. 8. 9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 14H as memory capacity. 10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN. 11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 12. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in. 13. Dual output data: IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1) DOUT0 DOUT1 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 9/32 ESMT Read (33MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 8Mbit density, once F25L08PA the data from address location FFFFFH had been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23 -A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. Figure 2: Read Sequence Fast Read (50 MHz; 100 MHz) The Fast Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read cycle. See Figure 3 for the Fast Read sequence. Following a dummy byte (8 clocks input dummy cycle), the Fast Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 8Mbit density, once the data from address location FFFFFH has been read, the next output will be from address location 000000H. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI MSB 0B ADD. MSB HIGH IMPENANCE ADD. ADD. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT SO Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 3: Fast Read Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 10/32 ESMT Fast Read Dual Output (50 MHz; 100 MHz) The Fast Read Dual Output (3BH) instruction is similar to the standard Fast Read (0BH) instruction except the data is output on SI and SO pins. This allows data to be transferred from the device at twice the rate of standard SPI devices. This instruction is for quickly downloading code from Flash to RAM upon power-up or for applications that cache code- segments to RAM for execution. F25L08PA The Fast Read Dual Output instruction is initiated by executing an 8-bit command, 3BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence. Figure 4: Fast Read Dual Output Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 11/32 ESMT Page Program (PP) The Page Program instruction allows many bytes to be programmed in the memory. The bytes must be in the erased state (FFH) when initiating a Program operation. A Page Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Page Program instruction. The Page Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, at least one byte Data is input (the maximum of input data can be up to 256 bytes). If the 8 least significant address bits [A7-A0] are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [A7-A0] are all zero). If more than 256 bytes Data are sent to the device, previously F25L08PA latched data are discarded and the last 256 bytes Data are guaranteed to be programmed correctly within the same page. If less than 256 bytes Data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TPP for the completion of the internal self-timed Page Program operation. While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the Busy bit. It is recommended to wait for a duration of TBP before reading the status register to check the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished, the Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 7 for the Page Program sequence. Figure 7: Page Program Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 12/32 ESMT Auto Address Increment (AAI) WORD Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware detection by reading the SO; software detection by polling the BUSY in the software status register or wait TBP. Refer to End of Write Detection section for details. Prior to any write operation, the Write Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23 -A0]. Following the addresses, two bytes of data is input sequentially. The data is input sequentially from MSB (bit F25L08PA 7) to LSB (bit 0). The first byte of data (D0) will be programmed into the initial address [A23 -A1] with A0 =0; the second byte of data (D1) will be programmed into the initial address [A23 -A1] with A0 =1. CE must be driven high before the AAI WORD program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the WRDI instruction, to terminate AAI. User must check BUSY status after WRDI to determine if the device is ready for any command. Please refer to Figure 10 and Figure 11. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0). End of Write Detection There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The Hardware End of Write Detection method is described in the section below. Hardware End of Write Detection The Hardware End of Write Detection method eliminates the overhead of polling the BUSY bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the SO pin to indicate Flash Busy status during AAI WORD programming (refer to Figure 8). The 8-bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A “0” Indicates the device is busy; a “1” Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to tri-state. The 8-bit command, 80H,disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output Software Status Register data during AAI WORD programming (refer to Figure 9). Figure 8: Enable SO as Hardware RY/ BY during AAI Programming Figure 9: Disable SO as Hardware RY/ BY during AAI Programming Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 13/32 ESMT F25L08PA Figure 10: AAI Word Program Sequence with Hardware End of Write Detection Figure 11: AAI Word Program Sequence with Software End of Write Detection Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 14/32 ESMT 64K Byte Block Erase The 64K-byte Block Erase instruction clears all bits in the selected block to FFH. A Block Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23 F25L08PA -A0]. Address bits [AMS -A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TBE for the completion of the internal self-timed Block Erase cycle. See Figure 13 for the Block Erase sequence. Figure 13: 64K-byte Block Erase Sequence 4K Byte Sector Erase The Sector Erase instruction clears all bits in the selected sector to FFH. A Sector Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23 -A0]. Address bits [AMS -A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TSE for the completion of the internal self-timed Sector Erase cycle. See Figure 14 for the Sector Erase sequence. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 SI MSB 20 ADD. MSB HIGH IMPENANCE ADD. ADD. SO Figure 14: 32K-byte Sector Erase Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 15/32 ESMT Chip Erase The Chip Erase instruction clears all bits in the device to FFH. A Chip Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip F25L08PA Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TCE for the completion of the internal self-timed Chip Erase cycle. See Figure 15 for the Chip Erase sequence. CE MODE3 SCK MODE0 01234567 SI MSB 60 or C7 SO HIGH IMPENANCE Figure 15: Chip Erase Sequence Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read Status Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE . See Figure 16 for the RDSR instruction sequence. Figure 16: Read Status Register (RDSR) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 16/32 ESMT Write Enable (WREN) The Write Enable (WREN) instruction sets the Write-EnableLatch bit in the Software Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write F25L08PA (Program/Erase) operation. CE must be driven high before the WREN instruction is executed. CE MODE3 SCK MODE0 01234567 SI MSB 06 SO HIGH IMPENANCE Figure 17: Write Enable (WREN) Sequence Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write-EnableLatch bit to 0 disabling any new Write operations from occurring or exits from OTP mode to normal mode. CE must be driven high before the WRDI instruction is executed. CE MODE3 SCK MODE0 01234567 SI MSB 04 SO HIGH IMPENANCE Figure 18: Write Disable (WRDI) Sequence Enable Write Status Register (EWSR) The Enable Write Status Register (EWSR) instruction arms the Write Status Register (WRSR) instruction and opens the status register for alteration. The Enable Write Status Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write Status Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 17/32 ESMT Write Status Register (WRSR) The Write Status Register instruction writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN and WRSR instruction sequences. Executing the Write Status Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lock down the status register, but cannot be reset from “1” to “0”. F25L08PA When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0; BP1 and BP2 bits at the same time. See Table 4 for a summary description of WP and BPL functions. CE MODE3 SCK MODE0 STATUS REGISTER IN 76543210 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 SI MSB 50 or 06 MSB HIGH IMPENANCE 01 SO Figure 19: Enable Write Status Register (EWSR) or Write Enable (WREN) and Write Status Register (WRSR) Enter Secured OTP Mode (ENSO) The ENSO (B1H) instruction is for entering the additional 4K bytes secured OTP mode. The additional 4K bytes secured OTP sector is independent from main array, which may use to store unique serial number for system identifier. User must unprotect whole array (BP0=BP1=BP2=0), prior to any Program operation in OTP sector. After entering the secured OTP mode, only the secured OTP sector can be accessed and user can only follow the Read or Program procedure with OTP address range (address bits [A23 –A12] must be “0”). The secured OTP data cannot be updated again once it is lock down or has been programmed. In secured OTP mode, WRSR command will ignore the input data and lock down the secured OTP sector (OTP_lock bit =1). To exit secured OTP mode, user must execute WRDI command. RES can be used to verify the secured OTP status as shown in Table 6. Figure 20: Enter OTP Mode (ENSO) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 18/32 ESMT OTP Sector Address Size 4K bytes Address Range 000000H ~ 000FFFH F25L08PA Note: The OTP sector is an independent Sector. Read-Electronic-Signature (RES) The RES instruction can be used to read the 8-bit Electronic Signature of the device on the SO pin. The RES instruction can provide access to the Electronic Signature of the device (except while an Erase, Program or WRSR cycle is in progress), Any RES instruction executed while an Erase, Program or WRSR cycle is in progress is no decoded, and has no effect on the cycle in progress. In OTP mode, user also can execute RES to confirm the status. Figure 21: Read-Electronic-Signature (RES) Instruction Table 6: Electronic Signature Data Command Mode Normal RES In secured OTP mode & non lock down (OTP_lock =0) In secured OTP mode & lock down (OTP_lock =1) Electronic Signature Data 13H 33H 73H Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 19/32 ESMT JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as F25L08PA and the manufacturer as ESMT. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 14H, identifies the device as F25L08PA F25L08PA. The instruction sequence is shown in Figure 22. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH). Figure 22: JEDEC Read-ID Sequence Table 7: JEDEC Read-ID Data Device ID Memory Type (Byte 2) 20H Memory Capacity (Byte 3) 14H Manufacturer’s ID (Byte 1) 8CH Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 20/32 ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L08PA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, followed by address bits [A23 -A0]. Following the Read-ID F25L08PA instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE . Figure 23: Read-ID Sequence Table 8: Product ID Data Address 00000H Byte1 8CH Manufacturer’s ID 13H 00001H Device ID ESMT F25L08PA Byte2 13H Device ID ESMT F25L08PA 8CH Manufacturer’s ID Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.7 21/32 ESMT ELECTRICAL SPECIFICATIONS F25L08PA Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (