F25S04PA-86DG

ESMT Flash FEATURES Single supply voltage 2.3~3.3V Standard, Dual SPI (Preliminary) F25S04PA 2.5V Only 4 Mbit Serial Flash Memory with Dual Output Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 86MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 86MHz/ 100MHz (100MHz / 172MHz/ 200MHz equivalent Dual SPI) Low power consumption - Active current: 25 mA - Standby current: 5 μ A - Deep Power Down current: 3 μ A Reliability - 100,000 typical program/erase cycles - 20 years Data Retention Program - Byte programming time: 7 μ s (typical) - Page programming time: 0.8 ms (typical) Erase - Chip erase time 3 sec (typical) - Block erase time 0.4 sec (typical) - Sector erase time 40 ms (typical) Page Programming - 256 byte per programmable page SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 End of program or erase detection Write Protect ( WP ) Hold Pin ( HOLD ) All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID F25S04PA –50PG F25S04PA –86PG F25S04PA –100PG F25S04PA –50PAG F25S04PA –86PAG F25S04PA –100PAG F25S04PA –50DG F25S04PA –86DG F25S04PA –100DG F25S04PA –50HG F25S04PA –86HG F25S04PA –100HG Speed 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz Package 8-lead SOIC 8-lead SOIC 8-lead SOIC 8-lead SOIC 8-lead SOIC 8-lead SOIC 8-lead PDIP 8-lead PDIP 8-lead PDIP 8-lead DFN 8-lead DFN 8-lead DFN 150 mil 150 mil 150 mil 200 mil 200 mil 200 mil 300 mil 300 mil 300 mil 5x6 mm 5x6 mm 5x6 mm COMMENTS Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 1/34 ESMT GENERAL DESCRIPTION (Preliminary) F25S04PA The F25S04PA is a 4Megabit, 2.5V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 2,048 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device features sector erase architecture. The memory array is divided into 128 uniform sectors with 4K byte each; 8 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. PIN CONFIGURATIONS 8- LEAD SOIC CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 2/34 ESMT 8- LEAD PDIP (Preliminary) F25S04PA CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI 8- LEAD DFN CE 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 3/34 ESMT PIN DESCRIPTION Symbol SCK SI (Preliminary) F25S04PA Pin Name Serial Clock Serial Data Input Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. SO CE WP Serial Data Output Chip Enable Write Protect HOLD VDD VSS Hold Power Supply Ground FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches X-Decoder Flash Y-Decoder Control Logic I/O Butters and Data Latches Serial Interface CE SCK SI SO WP HOLD Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 4/34 ESMT SECTOR STRUCTURE (Preliminary) F25S04PA Table 1: F25S04PA Sector Address Table Block Sector 127 7 : 112 111 6 : 96 95 5 : 80 79 4 : 64 63 3 : 48 47 2 : 32 31 1 : 16 15 0 : 0 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB Address range 07F000H – 07FFFFH : 070000H – 070FFFH 06F000H – 06FFFFH : 060000H – 060FFFH 05F000H – 05FFFFH : 050000H – 050FFFH 04F000H – 04FFFFH : 040000H – 040FFFH 03F000H – 03FFFFH : 030000H – 030FFFH 02F000H – 02FFFFH : 020000H – 020FFFH 01F000H – 01FFFFH : 010000H – 010FFFH 00F000H – 00FFFFH : 000000H – 000FFFH 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Block Address A18 A17 A16 Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 5/34 ESMT STATUS REGISTER (Preliminary) F25S04PA The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the software status register. Table 2: Software Status Register Bit 0 1 2 3 4 5 6 7 Note: 1. Only BP0, BP1, BP2, TB and BPL are writable. 2. BP0, BP1, BP2, TB and BPL are non-volatile; others volatile. 3. All area are protected at power-on (BP2=BP1=BP0=1) Name BUSY WEL BP0 BP1 BP2 TB RESERVED BPL Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Top / Bottom write protect Reserved for future use 1 = BP2,BP1,BP0 and TB are read-only bits 0 = BP2,BP1,BP0 and TB are read/writable Default at Power-up 0 0 0 0 0 0 0 0 Read/Write R R R/W R/W R/W R/W N/A R/W WRITE ENABLE LATCH (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If this bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions: BUSY The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. • • • • • • • Power-up Write Disable (WRDI) instruction completion Page Program instruction completion Sector Erase instruction completion Block Erase instruction completion Chip Erase instruction completion Write Status Register instructions Top/Bottom Block Protect (TB) The Top/Bottom bit (TB) controls if the Block-Protection (BP2, BP1, BP0) bits protect from the Top (TB=0) or the Bottom (TB=1) of the array as show in Table 3, The TB bit can be set with Write Status Register (WRSR) instruction. The TB bit can not be written to if the Block- Protection-Look (BPL) bit is 1 or WP is low. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 6/34 ESMT Protection Level 0 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/8 Lower 1/4 Lower 1/2 All Blocks (Preliminary) Table 3: F25S04PA Block Protection Table Status Register Bit TB X 0 0 0 1 1 1 X BP2 0 0 0 0 0 0 0 1 BP1 0 0 1 1 0 1 1 X BP0 0 1 0 1 1 0 1 X F25S04PA Protected Memory Area Block Range None Block 7 Block 6~7 Block 4~7 Block 0 Block 0~1 Block 0~3 Block 0~7 Address Range None 070000H – 07FFFFH 060000H – 07FFFFH 040000H – 07FFFFH 000000H – 00FFFFH 000000H – 01FFFFH 000000H – 03FFFFH 000000H – 07FFFFH Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table 3, to be software protected against any memory Write (Program or Erase) operations. The Write Status Register (WRSR) instruction is used to program the BP2, BP1, BP0 bits as long as WP is high or the BlockProtection-Look (BPL) bit is 0. Chip Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to 0. Block Protection Lock-Down (BPL) WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the TB, BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 7/34 ESMT HOLD OPERATION (Preliminary) F25S04PA HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 22 for Hold timing. SCK HO LD A c t iv e H o ld A c ti v e H old A c t iv e Figure 1: HOLD Condition Waveform WRITE PROTECTION The device provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for Block-Protection description. Table 4: Conditions to Execute Write-Status-Register (WRSR) Instruction WP BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed L L H Write Protect Pin ( WP ) The Write-Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write Status Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4). When WP is high, the lock-down function of the BPL bit is disabled. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 8/34 ESMT INSTRUCTIONS (Preliminary) F25S04PA Instructions are used to Read, Write (Erase and Program), and configure the F25S04PA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. Table 5: Device Operation Instructions Operation Read Fast Read Fast Read Dual 11,12 Output Sector Erase4 (4K Byte) Block Erase4, (64K Byte) Chip Erase Page Program (PP) Read Status Register (RDSR) 6 Write Status Register (WRSR) Write Enable (WREN) 9 Write Disable (WRDI) Deep Power Down (DP) Release from Deep Power Down (RDP) Read Electronic 7 Signature (RES) Jedec Read ID (JEDEC-ID) 8 Read ID (RDID) 10 50MHz ~ SIN 33 MHz 03H 0BH 20H D8H 60H / C7H 02H 05H 01H 100MHz 06H 04H B9h ABH ABH 9FH 90H Max. Freq 1 2 SOUT SIN Hi-Z A23-A16 Hi-Z A23-A16 Bus Cycle 1~3 4 SOUT SIN SOUT SIN SOUT SIN Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X 3 A15-A8 A7-A0 DIN0 X X X 5 SOUT DOUT0 X X Hi-Z 12H 8CH 12H DIN1 X X 6 SIN X X SOUT DOUT1 DOUT0 Hi-Z 12H 8CH N SIN SOUT X X - cont. cont. - 3BH A23-A16 DOUT0~1 cont. Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z - Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z X DIN X X 00H DOUT Hi-Z X 8CH Hi-Z X X 00H X 20H Hi-Z -. X X 00H 01H X 13H Hi-Z Hi-Z Up to 256 Hi-Z bytes - Note: 1. 2. 3. 4. 5. 6. 7. 8. 9. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous One bus cycle is eight clock periods. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be programmed. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as memory capacity. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 9/34 ESMT (Preliminary) F25S04PA instructions effective. WREN can enable WRSR, user just need to execute it. A successful WRSR can reset WREN. 10. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 11. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in. 12. Dual output data: IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1) DOUT0 DOUT1 Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 10/34 ESMT Read (33MHz) (Preliminary) F25S04PA The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23 -A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. Figure 2: Read Sequence Fast Read (50 MHz ~ 100 MHz) The Fast Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read cycle. See Figure 3 for the Fast Read sequence. Following a dummy byte (8 clocks input dummy cycle), the Fast Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH has been read, the next output will be from address location 000000H. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI MSB 0B ADD. MSB HIGH IMPENANCE ADD. ADD. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT SO Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 3: Fast Read Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 11/34 ESMT Fast Read Dual Output (50 MHz ~ 100 MHz) (Preliminary) F25S04PA The Fast Read Dual Output (3BH) instruction is similar to the standard Fast Read (0BH) instruction except the data is output on SI and SO pins. This allows data to be transferred from the device at twice the rate of standard SPI devices. This instruction is for quickly downloading code from Flash to RAM upon power-up or for applications that cache code- segments to RAM for execution. The Fast Read Dual Output instruction is initiated by executing an 8-bit command, 3BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence. Figure 4: Fast Read Dual Output Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 12/34 ESMT Page Program (PP) (Preliminary) F25S04PA The Page Program instruction allows many bytes to be programmed in the memory. The bytes must be in the erased state (FFH) when initiating a Program operation. A Page Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Page Program instruction. The Page Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, at least one byte Data is input (the maximum of input data can be up to 256 bytes). If the 8 least significant address bits [A7-A0] are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [A7-A0] are all zero). If more than 256 bytes Data are sent to the device, previously latched data are discarded and the last 256 bytes Data are guaranteed to be programmed correctly within the same page. If less than 256 bytes Data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TPP for the completion of the internal self-timed Page Program operation. While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the Busy bit. It is recommended to wait for a duration of TBP before reading the status register to check the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished, the Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 7 for the Page Program sequence. Figure 7: Page Program Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 13/34 ESMT 64K Byte Block Erase (Preliminary) F25S04PA The 64K-byte Block Erase instruction clears all bits in the selected block to FFH. A Block Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23 -A0]. Address bits [AMS -A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TBE for the completion of the internal self-timed Block Erase cycle. See Figure 8 for the Block Erase sequence. Figure 8: 64K-byte Block Erase Sequence 4K Byte Sector Erase The Sector Erase instruction clears all bits in the selected sector to FFH. A Sector Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23 -A0]. Address bits [AMS -A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TSE for the completion of the internal self-timed Sector Erase cycle. See Figure 9 for the Sector Erase sequence. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 SI MSB 20 ADD. MSB HIGH IMPENANCE ADD. ADD. SO Figure 9: 4K-byte Sector Erase Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 14/34 ESMT Chip Erase (Preliminary) F25S04PA The Chip Erase instruction clears all bits in the device to FFH. A Chip Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TCE for the completion of the internal self-timed Chip Erase cycle. See Figure 10 for the Chip Erase sequence. CE MODE3 SCK MODE0 01234567 SI MSB 60 or C7 SO HIGH IMPENANCE Figure 10: Chip Erase Sequence Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read Status Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE . See Figure 11 for the RDSR instruction sequence. Figure 11: Read Status Register (RDSR) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 15/34 ESMT Write Enable (WREN) (Preliminary) F25S04PA The Write Enable (WREN) instruction sets the Write-EnableLatch bit in the Software Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE must be driven high before the WREN instruction is executed. CE MODE3 SCK MODE0 01234567 SI MSB 06 SO HIGH IMPENANCE Figure 12: Write Enable (WREN) Sequence Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write-EnableLatch bit to 0 disabling any new Write operations from occurring. CE must be driven high before the WRDI instruction is executed. CE MODE3 SCK MODE0 01234567 SI MSB 04 SO HIGH IMPENANCE Figure 13: Write Disable (WRDI) Sequence CE Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 16/34 ESMT Write-Status-Register (WRSR) (Preliminary) F25S04PA The Write Status Register instruction writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 14 for WREN and WRSR instruction sequences. Executing the Write Status Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lock down the status register, but cannot be reset from “1” to “0”. When WP is high, the lock-down function of the BPL bit is disabled and the BPL, TB, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the TB, BP0; BP1 and BP2 bits at the same time. See Table 4 for a summary description of WP and BPL functions. CE MODE3 SCK MODE0 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Stauts Register Da ta In SI MSB SO HIGH IMPENANCE 06 01 7654 3210 MSB Figure 14: Write-Enable (WREN) and Write-Status-Register (WRSR) Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 17/34 ESMT Deep Power Down (DP) (Preliminary) F25S04PA The Deep Power Down instruction is for minimizing power consumption (the standby current is reduced from ISB1 to ISB2.). This instruction is initiated by executing an 8-bit command, B9H, and then CE must be driven high. After CE is driven high, the device will enter to deep power down within the duration of TDP. Once the device is in deep power down status, all instructions will be ignored except the Release from Deep Power Down instruction (RDP) and Read Electronic Signature instruction (RES). The device always power-up in the normal operation with the standby current (ISB1). See Figure 15 for the Deep Power Down instruction. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 T DP SI MSB B9 Standard Current Deep Power Down Current (ISB2) Figure 15: Deep Power Down Instruction Release from Deep Power Down (RDP) and Read-Electronic-Signature (RES) The Release form Deep Power Down and Read-ElectronicSignature instruction is a multi-purpose instruction. The instruction can be used to release the device from the deep power down status. This instruction is initiated by driving CE low and executing an 8-bit command, ABH, and then drive CE high. See Figure 16 for RDP instruction. Release from the deep power down will take the duration of TRES1 before the device will resume normal operation and other instructions are accepted. CE must remain high during TRES1. The instruction also can be used to read the 8-bit ElectronicSignature of the device on the SO pin. It is initiated by driving CE low and executing an 8-bit command, ABH, followed by 3 dummy bytes. The Electronic-Signature byte is then output from the device. The Electronic-Signature can be read continuously until CE go high. See Figure 17 for RES sequence. After driving CE high, it must remain high during for the duration of TRES2, and then the device will resume normal operation and other instructions are accepted. The instruction is executed while an Erase, Program or WRSR cycle is in progress is ignored and has no effect on the cycle in progress. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 18/34 ESMT CE MODE3 SCK MODE0 0 1 2 (Preliminary) F25S04PA 3 4 5 6 7 T RES1 SI MSB AB HIGH IMPEDANCE SO Deep Power Down Current ( ISB2) Standby Current Figure 16: Release from Deep Power Down (RDP) Instruction CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 30 31 32 33 34 35 36 37 38 TRES2 SS SI MSB SO AB 3 Dummy Bytes SS HIGH IMPEDANCE SS MSB Electronic-Signature Data Out Deep Power Down Current (ISB2) Standby Current Figure 17: Read Electronic -Signature (RES) Sequence Table 6: Electronic Signature Data Command RES Electronic Signature Data 12H Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 19/34 ESMT JEDEC Read-ID (Preliminary) F25S04PA The JEDEC Read-ID instruction identifies the device as F25S04PA and the manufacturer as ESMT. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 13H, identifies the device as F25S04PA. The instruction sequence is shown in Figure 18. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH). CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031 SI MSB SO 9F HIGH IMPENANCE MSB 8C MSB 20 MSB 13 Figure 18: JEDEC Read-ID Sequence Table 7: JEDEC READ-ID Data Device ID Memory Type (Byte 2) 20H Manufacturer’s ID (Byte 1) 8CH Memory Capacity (Byte 3) 13H Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 20/34 ESMT Read-ID (RDID) (Preliminary) F25S04PA The Read-ID instruction (RDID) identifies the devices as F25 S04PA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, followed by address bits [A23 -A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE . CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 4 8 55 56 63 SI MSB 90 00 00 MSB ADD 1 SO HIGH IMPENANCE MSB 8C 12 8C 12 HIGH IMPENA NCE Note: The Manufacture’s an d Device ID o utput stream i s continu ous until terminated by a low to high transition on CE. 1. 00H will output the Manufacture’s ID first a nd 01H will output Device ID first b efore toggling between the two. . Figure 19: Read-ID Sequence Table 8: Product ID Data Address 00000H Byte1 8CH Manufacturer’s ID 12H Byte2 12H Device ID ESMT F25S04PA 8CH Manufacturer’s ID 00001H Device ID ESMT F25S04PA Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 21/34 ESMT ELECTRICAL SPECIFICATIONS (Preliminary) F25S04PA Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (